Design for test, debug and manufacturability; built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures, low power DfT techniques, DfT for secure systems, Dft economics. Testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, board, system; testing 3D (TSV-based) chips; Network-on-Chip test; system-level debug and validation; hardware/software system test; processor-based test; infrastructure IP; industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies.
