Architecture, modelling and design techniques for network on chip; design methods for the on-chip interconnection network: interconnect topology, switching, routing and flow control methods; architecture and design for fault-tolerance, reliability enhancement, quality of service, dynamic voltage and frequency scaling; techniques and methodologies for NoC testing; GALS synchronization architectures for networks-on-chip; physical design techniques and methodologies; hardware/software communication abstraction, component-based modelling, platform-based design and methodologies, NoC exploration frameworks; design for on-chip networks based on alternative technologies such as photonics/optics, wireless, 3D stacking.
