High-Level and architectural level issues in SoC design and tools: architectural trade-offs, design, performance and synthesis issues; performance, cost and power driven architectural level synthesis; high level synthesis (scheduling, allocation, binding); datapath, control and memory synthesis and optimisation; HDL-driven architectural synthesis. Design reuse methods, IP management, IP qualification and assessment, Portability, retargetability, IP data management/IP transfer, IP watermarking, IP protection.