Plenary : Keynote Session
1A: Architectural-Level Power Management
1B: Formal Verification Using Functional and Structural Information
1C: Power, Timing and Diagnosis Constrained Testing
1D: Mixed-Signal Circuits and Systems
1E: Communication-Centric and Source-Level Optimisations for High-Level Synthesis
1F: Panel Session: SystemC and System Verilog: Where do They Fit? Where are They Going?
2A: Low Power Systems and Architectures
2B: Advanced Formal Verification Techniques
2C: New Algorithms for TPG
2E: Optimisation of Memory Hierarchies
2F: Hot Topic -- High Security Smartcards
3A: New Directions in Low-Power Design
3B: Advances in SAT
3C: Analogue and High-Frequency Test
3E: Energy Efficient Memory Usage
3F: Hot Topic -- How Can System Level Design Solve the Interconnect Technology Scaling Problem?
4A: System Level Design Methodology
4B: System Level Modelling and Analysis
4C: Advances in SoC Testing
4E: New Issues in Analogue System- and Circuit-Level Performance Modelling
4F: Fabrics and Scheduling for Reconfigurable Computing
4G: Power Aware Design and Synthesis
5A: System Level Design: Case Studies, Exploration and Optimisation
5B: Recent Advances in Digital Systems Simulation
5C: On-Line Testing and Reliability for Nanometric Technology
5E: Parasitic-Aware Analogue Design
5F: Hardware/Software System Design and Architecture Exploration
5G: Hot Topic -- Extremely Low-Power Logic
IP1: Interactive Presentations
IP2: Interactive Presentations
IP3: Interactive Presentations
6A: Performances Analysis for MPSoC
6B: Synthesis for Noise and Manufacturability
6C: Support for BIST
6E: Modelling, Simulation and Optimisation in Power/Ground/Substrate
6F: Panel Session -- Chips of the Future: Soft, Crunchy or Hard?
6G: Power-Aware Networks and Interfaces (Low Power Special Day)
7A: Networks on Chip Design
7B: Advances in Technology Mapping and Circuit Sizing
7C: Panel Session -- Nanometer Design: What are the Requirements for Manufacturing Test?
7E: Issues in Interconnect Simulation and Model Order Reduction
7F: Emerging Technologies: From Sensors to Qubits
7G: Embedded Tutorial -- Architectures and Design Techniques for Energy Efficient Embedded DSP and Multimedia Processing
8A: Platform-Based Design and VC Reuse Methods
8B: Real-Time Issues in Embedded Systems
8C: Real-Life Defect Modelling and Detection
8E: Optimisation in Physical Design
8G: Hot Topic -- Platforms and Tools for Energy-Efficient Design of Multimedia Systems
9A: Communication Design for MPSoC
9B: Combining Static and Dynamic Software Optimisation
9C: Hot Topic -- The Status of the New IEEE Test Standards
9E: Modelling and Estimation in Circuit Layout
9G: Applications of Reconfigurability
10A: Interconnect Modelling for MPSoC
10B: Embedded Software Generation and Optimisation
10C: Scan-Based Testing
10E: Novel Approaches to Analogue Simulation
10F: Embedded Tutorial -- System Verilog for VHDL Users
10G: Hot Topic -- Quo Vadis Multimedia? From Desktop Multimedia to Distributed Multimedia Systems
IP4: Interactive Presentations
IP5: Interactive Presentations
IP6: Interactive Presentations