DATE 2002 SESSION INDEX
Plenary --
Keynote Session
1A:
Hot Topic -- How to Choose Semiconductor IP?
1B:
Formal Verification of Complex Designs
1C:
Cooling Layout Arrangements
1D:
Defect Oriented Test
1E:
Power Analysis and Management in Networks and Processors
2A:
Panel -- What is the Right IP Business Model?
2B:
SAT and BDD Techniques
2C:
Technology and Interconnect Issues in Low Power Design
2D:
Advanced Mixed Signal Test
2E:
Collaborative Design -- Web-Services, Infrastructure, Applications
2F:
Panel -- Who Owns the Platform?
3A:
Embedded Tutorial -- The Need for Infrastructure IP in SoCs
3B:
Advances in Logic Synthesis
3C:
Novel Applications of Symbolic Techniques to Analogue and Digital Circuit Design
3D:
Hot Topic -- EDA Tools for RF: Myth or Reality?
3E:
Platform-Based Design and Virtual-Component Reuse
3F2:
Analogue Circuit Characterisation and Simulation
4A:
Panel -- MEDEA+ and ITRS Roadmaps
4B:
Asynchronous Circuits and Clock Scheduling
4C:
Analogue and Mixed-Signal Systems
4D:
BIST Diagnosis and DFT
4E:
Code and Memory Optimization in Co-Design
5A:
Hot Topic -- Network on a Chip
5B:
Low Power Architectures and Software
5C:
Nitty Gritty Details of Layout Design
5D:
SoC and System Test
5E:
Modelling and Synthesis of Embedded Systems
6A:
Panel -- Power Crisis in SoC Design: Strategies for Constructing Low-Power,
High-Performance SoC Designs
6B:
Reconfigurable Architectures
6C:
Analogue Modelling, Layout and Sizing
6D:
Test Resource Partitioning for Embedded Cores
6E:
System Level Simulation and Modelling
6F:
Hot Topic -- Deep Submicron Design and Timing Closure
7A:
Panel -- Reconfigurable SoC -- What Will it Look Like?
7B:
Layout Aware Logic Synthesis
7C:
Buffering and Tapering
7D:
Automatic Design Debug and TPG
7E:
Object Oriented System Specification and Design
8A:
Hot Topic -- UML: Using the Unified Modeling Language for
Embedded System Specification
8B:
Real-Time Embedded Systems
8C:
Interconnect Modelling
8D:
On-Line Testing and Fault Tolerance
8E:
Design Space Evaluation
9A:
Hot Topic -- From System Specification to Layout: Seamless Top-Down Design
Methods for Analogue and Mixed Signal Applications
9B:
Architectural Level Synthesis
9C:
Advanced Linear Modelling Techniques
9D:
Memory Testing and ATPG Issues
9E:
Embedded Software Performance Analysis and Optimization
9G:
Technical Plenary -- 40 Years of EDA
10A:
Hot Topic -- Design Technology for Networked Reconfigurable FPGA Platforms
10B:
High-Level Synthesis and Asynchronous Pipelines
10C:
Coupling and Switching Noise Modelling within Integrated Circuits
10D:
Panel -- Formal Verification Techniques: Industrial Status and Perspectives
10E:
Power Optimization for Embedded Processors
Poster Sessions
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