Session 1A:
Embedded Software Generation
This session deals with optimisations on different layers in software
generation. The first paper presents a novel code selection technique to
exploit SIMD instructions in media processors. The next presentation shows
the applicability and effectiveness of source-level optimisations for address
computations in the context of multimedia applications. New optimisation
techniques for embedded software based on Free Multi-valued Decision Diagrams
are described in the last paper.
Session 1B:
Low-Power Issues in System-Level Design
Papers in this session address three different aspects of system-level design
for low power: dynamic power management, HW/SW power estimation and battery
modelling.
Session 1C:
Circuit Analysis and Synthesis
New developments in circuit analysis and synthesis are discussed both at the
level of basic circuits and higher levels. The first paper deals with combined
circuit sizing and design centering. The second deals with symbolic analysis.
The third paper combines layout synthesis and circuit sizing, while the last
paper addresses analogue synthesis for Field-Programmable Gate Arrays.
Embedded Tutorial -
Design Practices for Better Reliability and Yield
Thanks to the swift advance of semiconductor technology companies continually
do introduce new embedded functions in their integrated circuits. Embedded
support functions, such as for Design-for-Testability, have already become
traditional. Today, advanced embedded functions, beyond DFT, are being
introduced into our designs to enhance the overall reliability of an IC, to
contribute to the analysis of its defects, and to help optimise the yield. This
embedded tutorial will discuss a variety of advanced design practices meant to
improve reliability and yield.
Session 2A:
Embedded Tutorial -- System Level Design Using C++
In system-level design, the required functionality can be mapped to hardware or
software, either on a given architectural platform, or on an architecture that
is being designed concurrently. Modelling both hardware and software in a
high-level programming language, such as C or C++, is clearly beneficial for
systems in which a large portion will be implemented as compiled software.
Moreover, significant simulation speed-up can be achieved by modelling hardware
directly in C++, appropriately enhanced with concurrency and synthesis
capabilities. In this session, speakers from industry and academia will review
the basic technology and the most recent trends in system-level modelling,
simulation and synthesis based on C++ libraries.
Session 2B:
IP and Design Reuse
This session addresses several aspects of IP and Design Reuse. The first paper
presents a method for performance loss optimisation when using bus mappers. The
second one addresses optimisation methods for design reuse at several levels of
abstraction. The last one focuses on distributed internet-based IP protection
techniques during selection and design, applied on system test methods.
Session 2C:
Layout
A number of problems, defined a long time ago, still require efficient
up-to-date solutions. This session touches upon such "classical" layout
problems.
Session 2D:
Heterogeneous Aspects in SOC Testing
This session deals with various aspects of SOC testing, including test
synthesis for mixed-signal paths, combination of BIST and external testing,
a test access mechanism, and an exploration of test in design space.
Session 3A:
System Specification
This session addresses current issues in embedded system specification. The
first two papers present a mathematical foundation and application of the
interoperability of sampled data and event driven simulation. The third paper
introduces an algebraic formalism for the specification of delay insensitive
module interfacing.
Session 3B:
Implementation of Telecom Systems
The first paper discusses a 50 Mbit/s turbo decoder implemented using a true
single phase clock running at 1 GHz. The second paper shows a single chip
solution for GSM baseband processing. The third paper describes the concept
and implementation of a telegram emulator.
Session 3C:
Logic Synthesis: Combination
The papers in this session show an important trend in logic synthesis: the
combined optimisation of two or more previously separate optimisation steps.
Session 3D:
BIST for Mixed-Signal Applications
This session presents different BIST approaches for analogue and mixed-signal
circuits. The first two papers propose original solutions to test the static
specifications of analogue-to-digital converters. The third paper describes a
solution for defect-oriented-testing of an analogue filter.
Session 4A:
Decision Diagram Based Methods
This session proposes three papers that exploit structures derived from BDDs to
check satisfiability, to explore state spaces or to determine critical times in
real-time systems.
Session 4B:
Multi-Processor Architectures and Design Methods
In this session two new solutions for interprocessor communication are presented
. The first paper discusses on-chip packet switched network as an alternative
to classical bus interconnect. The second paper introduces a novel caching
scheme to limit the amount of on-chip buffering. The third paper discusses the
design of an engine management system using VCC.
Session 4C:
Logic Synthesis: Performance Optimization
This session shows three ways to optimise performance: FSM decomposition,
using CD Domino Logic implementation, or applying gate sizing.
Session 4D:
TPG and Diagnosis in BIST
The first paper presents a GA-based computation of optimal seeds for functional
BIST. Then a method for on-chip generation of weighted text sequences for
synchronous sequential circuits is introduced. Finally, diagnostic testing of
embedded memories using BIST is discussed.
Session 5A:
Architectural-Level Synthesis
This session deals with significant issues in architectural-level synthesis.
The first paper addresses synthesis from C specifications, including dynamic
memory allocation and pointers. The second and third papers present novel
partitioning approaches for reconfigurable architectures. The last paper
discusses cache and bus power estimation for systems-on-a-chip.
Session 5B:
Analysis of Communication Circuits
Papers presented in this session deal with specific aspects of communication
circuit design such as performance evaluation in clock recovery circuits,
timing jitter computation in PLL and non-linear distortion modelling.
Session 5C:
Logic Synthesis: Covering and PTL Circuits
The papers in this session address two increasingly important topics: the
efficient solution of large covering problems and a design style based on
pass transistor logic.
Session 5D:
Delay and Functional Testing
The papers in this session include incremental techniques to the Boolean
satisfiability problem, and the application of genetic and deterministic
methods for validation and testing.
Session 6A:
Co-Synthesis of Embedded Systems
The co-synthesis of embedded systems is addressed by three presentations. The
first paper deals with efficient buffer memory implementations starting from
synchronous dataflow specifications. The second paper is aimed at improving the
efficiency of synthesis by means of new cost metrics. The session is concluded
by a paper which emphasises co-synthesis based on programmable and
reconfigurable components.
Session 6B:
Hot Topic -- How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level?
Current processor architectures, both in the programmable and custom case,
become more and more dominated by the data access bottlenecks in the cache,
system bus and main memory subsystems. In order to provide sufficiently high
data throughput in the emerging era of highly parallel processors where many
arithmetic resources can work concurrently, novel solutions for the memory
access and data transfer will have to be introduced. The crucial question we
want to address in this hot topic session is where one can expect these novel
solutions to rely on: will they be mainly innovative processor architecture
ideas, or novel approaches in the application compiler/synthesis technology, or
a mix. This session is mainly intended for architecture designers dealing with
processors (programmable or custom) which include large amounts of memory or
for application designers who handle data-dominated applications. In addition,
we also target (system level) design tool developers and researchers who look
at design methodologies and tools which can support this type of processor
architecture and application design.
Session 6C:
Wire Performance
System performance is increasingly determined by the electrical properties of
interconnect. Different methods for analysis and optimisation are discussed
in this session.
Session 6D:
Analogue Aspects of System Testing Wire Performance
The papers in this session address several analogue aspects of IC and System
Testing ranging from delay test over new methods to use the IEEE 1149.4
analogue test bus to digital filter and MEMS test.
Session 7A:
Abstraction Techniques
The three papers in this session explore abstraction techniques to make
verification more efficient.
Session 7B:
Panel Session -- A Design Automation Roadmap for Europe
Design Automation in EUROPE needs to be revitalised through a more co-operative
approach to problems and solutions. MEDEA has been instrumental in bringing
co-operation between process and applications and showing weaknesses of design
automation solutions with present players. A new burgeoning explosion of start
ups in strategic areas shows good promise in Europe. The goal is to launch new
design solutions based on standard market tools complemented by new European
start-ups early offering in strategic areas. These design solutions will be
dedicated to European needs but addressing global worldwide markets. The aim of
this workshop is to debate on the MEDEA design automation roadmap as a European
permanent forum for exchange of ideas and new strategic developments for the
European Industry.
Session 7C:
Interconnect Modelling and Analysis
The emerging problems in Deep Submicron Design are caused by cross-talk and
inductive effects. The papers in this session address the issues of model
extraction, cross-talk estimation and measurement of interconnect
optimisation.
Session 7D:
Mixed A/D System Design
Analogue and mixed-signal circuits, either as a single chip or as a combination
of ICs and high quality off-chip passive components are increasingly important
in front-ends for many applications, e.g. digital telecommunications. This
session covers design methodologies for mixed-signal systems.
Session 8A:
Scheduling and Timing Analysis for Real-Time Embedded Systems
The first paper in this session provides efficient abstract models for software
performance on modern pipelined processors with caches. The second and third
paper deal with scheduling of computation and communication resources under
real-time constraints.
Session 8B:
Hot Topic -- Standards for System Level Design: Practical Reality or
Solution in Search of a Question?
In this session, we will address the issue of standards in the system-level
design space. This issue has drawn a great deal of interest in the past year,
but has also revealed its share of skeptics. We will present three standards
in the system-level space, and describe three distinct industrial case-studies
which support the practicality of these standards. We will then open the
discussion: Will system-level standards scale to full industry adoption, or
are they just a niche design-religion?
Session 8D:
Dependability Issues in Advanced ICs and Systems
Dependability evaluation in advanced ICs and systems, timing and transient
fault threats and solutions in very deep submicron or nanometer technologies
and on-line testing of sensors are addressed in this session.
Session 9A:
High-Level Power Optimization
The papers in this session propose power optimisation techniques applicable to
designs described at the RTL level and above.
Session 9B:
Panel Session -- The Optimal Architecture Platform for System Design
Flexible hardware platform architectures have emerged as a competitor to
specialized SOC designs. Important applications are mobile systems or
multimedia devices. Design cost and design time reduction are the main benefits
of such platforms while cost and power efficiency are the main concerns. The
panel brings together outstanding representatives from computer architecture,
compiler technology, system design, and EDA. They will discuss the controversial
issue of suitable hardware architectures ranging from weakly programmable
processors to VLIW systems, they will present their different views on the
platform design process using fixed or parameterisable cores, and the required
tool chain and methodology which shall guarantee efficiency for a set of
applications under flexibility constraints. All these aspects are key to the
success of hardware platform architectures.
Session 9C:
Embedded Tutorial: How Thin Is The Ice? -- Designing Closer to the Edge
Why do digital integrated circuits fail? It used to be that defects accounted
for the lion's share of failures, but as we descent into the deep sub-micron
regime, parametric failures are becoming the dominant source of yield loss.
Parametric failures occur because of process variability that manifests itself
as fluctuations in the electrical parameters of active and passive devices on
chip. The conventional method for modeling process variability is worst-case
analysis where a the performance is bounded by a set of extreme-case
parameters; thus the "fast" and "slow" corner cases common for many digital
design methodologies. A key assumption is that the variability is independent
of the details of the design, which results in a paradigm where variability is
imposed upon the design by the process. In deep sub-micron, variability is
co-generated by the design and the process, meaning that details of the
physical implementation (layout) of the design play a substantial part in
determining the observed fluctuation in electrical and physical parameters. For
example, variations in metal wire layout density result in variations in metal
and inter-layer-dielectric thickness which directly determine wire resistance
and capacitance and hence wire delay. This tutorial will describe process
variability sources and trends, existing and new methods for analysis of such
variability, and ways in which a design may be made less sensitive to
process-induced variability.
Session 9D:
Defect Oriented Test
In this session the importance of process variations and spot defects on test
is explored through IDDQ measurements and parametric analogue simulations.
Defect level modelling is accounted for using a new clustering technique.
Session 10A:
Simulation and Emulation
Parallel and distributed simulation as well as emulation with FPGAs or DSPs
are key methods for simulation acceleration. Application areas range from
transistor up to system level.
Session 10B:
Embedded System Design Frameworks
This session is devoted to methodologies and tools for system-level design. The
first three papers deal with system modelling and architecture selection,
including resource allocation and scheduling, real-time hardware scheduling and
processor selection. The last paper describes an ASIP design environment for
efficient Java execution.
Session 10D:
Power and Cost Issues in Testing
The session deals with various aspects of power and cost in testing. A new model
to predict the cost and benefits of BIST, a technique to reduce the power
consumption caused by scan shifting, and a new approach to detect redundant
system faults by power monitoring are presented. The session concludes with a
new method for redundancy identification.