12.3 Aging, calibration circuits and yield

Time	Label	Presentation Title Authors
16:00	12.3.1	PACKAGE AND CHIP ACCELERATED AGING TESTS FOR POWER MOSFET RELIABILITY EVALUATION Speaker: Tingyou Lin, Department of LAD Technology, Vanguard International Semiconductor, TW Authors: Tingyou Lin¹, Chauchin Su¹, Chung-Chih Hung¹, Karuna Nidhi², Chily Tu² and Shao-Chang Huang² ¹National Chiao Tung University, TW; ²Vanguard International Semiconductor Corporation, TW Abstract This paper investigates power MOSFET stress conditions for package aging and chip aging evaluation. It is used to reduce the measurement time to obtain the characterization shift while component aging. For the reliability of semiconductor devices, the lifetime is related to the device operating temperature and its electric field. In the power semiconductor, the junction temperature is related to the power pulse time, the chip size, and the heat sink of the self-heating effect of the device. To model the power MOSFET lifetime, a new method is proposed to accelerate aging with the pulse time and the power dissipation controlling. A test chip is designed and fabricated in a 0.15μm BCD process. The measured results demonstrate the 10kμm width of the power MOSFET with Rds,on increasing of 72% after the total stress time of 6.3hr for the package aging. In the chip aging, the measured results show the MOSFET by increasing Ron for 12% after 600 times stress pulse. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately. Download Paper (PDF; Only available from the DATE venue WiFi)
16:30	12.3.2	BAYESIAN OPTIMIZED IMPORTANCE SAMPLING FOR HIGH SIGMA FAILURE RATE ESTIMATION Speaker: Dennis Weller, Karlsruhe Institute of Technology, DE Authors: Dennis Weller, Michael Hefenbrock, Mohammad Saber Golanbari, Michael Beigl and Mehdi Tahoori, Karlsruhe Institute of Technology, DE Abstract Due to aggressive technology downscaling, process and runtime variations have a strong impact on the correct functionality in the field as well as manufacturing yield. The assessment of the yield and failure rate is extremely crucial for design optimization. The common practice is to use Monte Carlo simulations in order to account for device variations and estimate failure rate. However, Monte Carlo methods are infeasible for estimating rare events such as high sigma failure rates, and hence, various importance sampling methods have been proposed. In this paper, we present an efficient importance sampling approach based on Bayesian optimization. Its advantages include constant complexity independent of the dimensions of design space, the potential to find the global extrema, and higher trustworthiness of the estimated failure rate. We evaluated the approach on a 6T SRAM cell based on a 28nm FDSOI process. The results show significant speedup and more than two orders of magnitude better accuracy in failure rate estimation, compared to the best state-of-the-art technique. Download Paper (PDF; Only available from the DATE venue WiFi)
17:00	12.3.3	WAFER-LEVEL ADAPTIVE VMIN CALIBRATION SEED FORECASTING Speaker: Yiorgos Makris, The University of Texas at Dallas, US Authors: Constantinos Xanthopoulos¹, Deepika Neethirajan¹, Sirish Boddikurapati², Amit Nahar³ and Yiorgos Makris¹ ¹The University of Texas at Dallas, US; ²Texas Instruments Inc., US; ³Texas Instruments inc., US Abstract To combat the effects of process variation in modern, high-performance integrated Circuits (ICs), various post-manufacturing calibrations are typically performed. These calibrations aim to bring each device within its specification limits and ensure that it abides by current technology standards. Moreover, with the increasing popularity of mobile devices that usually depend on finite energy sources, power consumption has been introduced as an additional constraint. As a result, post-silicon calibration is often performed to identify the optimal operating voltage (Vmin) of a given IC. This calibration is time-consuming, as it requires the device to be tested in a wide range of voltage inputs across a large number of tests. In this work, we propose a machine learning-based methodology for reducing the cost of performing the Vmin calibration search, by identifying an optimal wafer-level starting voltage (seed). The effectiveness of the proposed methodology is demonstrated on an industrial dataset. Download Paper (PDF; Only available from the DATE venue WiFi)
17:15	12.3.4	SINGLE-EVENT DOUBLE-UPSET SELF-RECOVERABLE AND SINGLE-EVENT TRANSIENT PULSE FILTERABLE LATCH DESIGN FOR LOW POWER APPLICATIONS Speaker: Aibin Yan, Anhui University, CN Authors: Aibin Yan¹, Yuanjie Hu¹, Jie Song¹ and Xiaoqing Wen² ¹Anhui University, CN; ²Kyushu Institute of Technology, JP Abstract This paper presents a single-event double-upset (SEDU) self-recoverable and single-event transient (SET) pulse filterable latch design for low power applications in 22nm CMOS technology. The latch mainly consists of eight mutually feeding back C-elements and a Schmitt trigger. Simulation results have demonstrated both the SEDU self-recoverability and SET pulse filterability for the latch using redundant silicon area. Using clock gating technology, the latch saves about 54.85% power dissipation on average compared with the up-to-date SEDU self-recoverable latch designs which are not SET pulse filterable at all. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30		End of session

Time

Label

Presentation Title
Authors

16:00

12.3.1

PACKAGE AND CHIP ACCELERATED AGING TESTS FOR POWER MOSFET RELIABILITY EVALUATION
Speaker:
Tingyou Lin, Department of LAD Technology, Vanguard International Semiconductor, TW
Authors:
Tingyou Lin¹, Chauchin Su¹, Chung-Chih Hung¹, Karuna Nidhi², Chily Tu² and Shao-Chang Huang²
¹National Chiao Tung University, TW; ²Vanguard International Semiconductor Corporation, TW
Abstract
This paper investigates power MOSFET stress conditions for package aging and chip aging evaluation. It is used to reduce the measurement time to obtain the characterization shift while component aging. For the reliability of semiconductor devices, the lifetime is related to the device operating temperature and its electric field. In the power semiconductor, the junction temperature is related to the power pulse time, the chip size, and the heat sink of the self-heating effect of the device. To model the power MOSFET lifetime, a new method is proposed to accelerate aging with the pulse time and the power dissipation controlling. A test chip is designed and fabricated in a 0.15μm BCD process. The measured results demonstrate the 10kμm width of the power MOSFET with Rds,on increasing of 72% after the total stress time of 6.3hr for the package aging. In the chip aging, the measured results show the MOSFET by increasing Ron for 12% after 600 times stress pulse. The measurement verifies that the accelerated aging in the package and the chip can be controlled separately.
Download Paper (PDF; Only available from the DATE venue WiFi)

16:30

12.3.2

BAYESIAN OPTIMIZED IMPORTANCE SAMPLING FOR HIGH SIGMA FAILURE RATE ESTIMATION
Speaker:
Dennis Weller, Karlsruhe Institute of Technology, DE
Authors:
Dennis Weller, Michael Hefenbrock, Mohammad Saber Golanbari, Michael Beigl and Mehdi Tahoori, Karlsruhe Institute of Technology, DE
Abstract
Due to aggressive technology downscaling, process and runtime variations have a strong impact on the correct functionality in the field as well as manufacturing yield. The assessment of the yield and failure rate is extremely crucial for design optimization. The common practice is to use Monte Carlo simulations in order to account for device variations and estimate failure rate. However, Monte Carlo methods are infeasible for estimating rare events such as high sigma failure rates, and hence, various importance sampling methods have been proposed. In this paper, we present an efficient importance sampling approach based on Bayesian optimization. Its advantages include constant complexity independent of the dimensions of design space, the potential to find the global extrema, and higher trustworthiness of the estimated failure rate. We evaluated the approach on a 6T SRAM cell based on a 28nm FDSOI process. The results show significant speedup and more than two orders of magnitude better accuracy in failure rate estimation, compared to the best state-of-the-art technique.
Download Paper (PDF; Only available from the DATE venue WiFi)

17:00

12.3.3

WAFER-LEVEL ADAPTIVE VMIN CALIBRATION SEED FORECASTING
Speaker:
Yiorgos Makris, The University of Texas at Dallas, US
Authors:
Constantinos Xanthopoulos¹, Deepika Neethirajan¹, Sirish Boddikurapati², Amit Nahar³ and Yiorgos Makris¹
¹The University of Texas at Dallas, US; ²Texas Instruments Inc., US; ³Texas Instruments inc., US
Abstract
To combat the effects of process variation in modern, high-performance integrated Circuits (ICs), various post-manufacturing calibrations are typically performed. These calibrations aim to bring each device within its specification limits and ensure that it abides by current technology standards. Moreover, with the increasing popularity of mobile devices that usually depend on finite energy sources, power consumption has been introduced as an additional constraint. As a result, post-silicon calibration is often performed to identify the optimal operating voltage (Vmin) of a given IC. This calibration is time-consuming, as it requires the device to be tested in a wide range of voltage inputs across a large number of tests. In this work, we propose a machine learning-based methodology for reducing the cost of performing the Vmin calibration search, by identifying an optimal wafer-level starting voltage (seed). The effectiveness of the proposed methodology is demonstrated on an industrial dataset.
Download Paper (PDF; Only available from the DATE venue WiFi)

17:15

12.3.4

SINGLE-EVENT DOUBLE-UPSET SELF-RECOVERABLE AND SINGLE-EVENT TRANSIENT PULSE FILTERABLE LATCH DESIGN FOR LOW POWER APPLICATIONS
Speaker:
Aibin Yan, Anhui University, CN
Authors:
Aibin Yan¹, Yuanjie Hu¹, Jie Song¹ and Xiaoqing Wen²
¹Anhui University, CN; ²Kyushu Institute of Technology, JP
Abstract
This paper presents a single-event double-upset (SEDU) self-recoverable and single-event transient (SET) pulse filterable latch design for low power applications in 22nm CMOS technology. The latch mainly consists of eight mutually feeding back C-elements and a Schmitt trigger. Simulation results have demonstrated both the SEDU self-recoverability and SET pulse filterability for the latch using redundant silicon area. Using clock gating technology, the latch saves about 54.85% power dissipation on average compared with the up-to-date SEDU self-recoverable latch designs which are not SET pulse filterable at all.
Download Paper (PDF; Only available from the DATE venue WiFi)

17:30

End of session