Date: Tuesday 26 March 2019
Time: 14:30 - 16:00
Location / Room: Room 6
Chair:
Valentin Gherman, CEA-Leti, FR
Co-Chair:
Borzoo Bonakdarpour, Iowa State University, US
This session explores solutions for reliable memories at different levels. The first paper introduces a process-variation-resilient space allocation scheme for open-channel SSD with 3D charge-trap flash memory. The second paper presents an architecture-independent framework to mitigate read disturbance errors in STT-RAM. Finally, the third paper proposes a wear leveling aware memory allocator for PCM memories. The IP presentation deals with memory dependency speculation and how to take advantage of it during the Dynamic Binary Translation process by using VLIW cores.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:30 | 3.6.1 | PATCH: PROCESS-VARIATION-RESILIENT SPACE ALLOCATION FOR OPEN-CHANNEL SSD WITH 3D FLASH Speaker: Yi Wang, Shenzhen University, CN Authors: Jing Chen1, Yi Wang1, Amelie Chi Zhou1, Rui Mao1 and Tao Li2 1Shenzhen University, CN; 2University of Florida, US Abstract Advanced three-dimensional (3D) flash memory adopts charge-trap technology that can effectively improve the bit density and reduce the coupling effect. Despite these advantages, 3D charge-trap flash brings a number of new challenges. First, current etching process is unable to manufacture perfect channels with identical feature size. Second, the cell current in 3D chargetrap flash is only 20% compared to planar flash memory, making it difficult to give a reliable sensing margin. These issues are affected by process variation, and they pose threats to the integrity of data stored in 3D charge-trap flash. This paper presents PATCH, a process-variation-resilient space allocation scheme for open-channel SSD with 3D charge-trap flash memory. PATCH is a novel hardware and file system interface that can transparently allocate physical space in the presence of process variation. PATCH utilizes the rich functionalities provided by the system infrastructure of open-channel SSD to reduce the uncorrectable bit errors. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that PATCH can effectively enhance the reliability with negligible extra erase operations in comparison with representative schemes. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 3.6.2 | COMPILER-DIRECTED AND ARCHITECTURE-INDEPENDENT MITIGATION OF READ DISTURBANCE ERRORS IN STT-RAM Speaker: Chengmo Yang, University of Delaware, US Authors: Fateme Sadat Hosseini and Chengmo Yang, University of Delaware, US Abstract High density, negligible leakage power, and fast read speed have made Spin-Transfer Torque Random Access Memory (STT-RAM) one of the most promising candidates for next generation on-chip memories. However, STT-RAM suffers from read-disturbance errors, that is, read operations might accidentally change the value of the accessed memory location. Although these errors could be mitigated by applying a restore-after-read operation, the energy overhead would be significant. This paper presents an architecture-independent framework to mitigate read disturbance errors while reducing the energy overhead, by selectively inserting restore operations under the guidance of the compiler. For that purpose, the vulnerability of load operations to read disturbance errors is evaluated using a specifically designed fault model; a code transformation technique is developed to reduce the number of vulnerable loads; and, an algorithm is proposed to selectively insert restore operations. The evaluation results show that the proposed technique can effectively reduce up to 97% of restore operations and 66% of the energy overhead while maintaining 99.8% coverage of read disturbance errors. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | 3.6.3 | A WEAR LEVELING AWARE MEMORY ALLOCATOR FOR BOTH STACK AND HEAP MANAGEMENT IN PCM-BASED MAIN MEMORY SYSTEMS Speaker: Qingan Li, Wuhan University, CN Authors: Wei Li1, Ziqi Shuai1, Chun Xue2, Mengting Yuan1 and Qingan Li1 1Wuhan University, CN; 2City University of Hong Kong, HK Abstract Phase change memory (PCM) has been considered as a replacement of DRAM, due to its potentials in high storage density and low leakage power. However, the limited write endurance presents critical challenges. Various wear leveling techniques have been proposed to mitigate this issue from different perspectives, including both hardware and software levels. This paper proposes a wear leveling aware memory allocator, which (1) always prefers allocating memory blocks with less writes upon memory requests, and (2) leaves blocks allocated more than a threshold value unallocable temporarily. Furthermore, for the first time, this allocator provides a uniform management scheme for both stack and heap areas, thus could better balance writes in stack and heap areas. Experimental evaluations show that, compared to state-of-the-art memory allocators (i.e., glibc malloc, NVMalloc and Walloc), the proposed memory allocator improves the PCM wear leveling, in terms of CoV (a wear leveling indicator) by 41.9%, 30.3%, and 35.8%, respectively. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | IP1-21, 233 | AGGRESSIVE MEMORY SPECULATION IN HW/SW CO-DESIGNED MACHINES Speaker: Simon Rokicki, INRIA, FR Authors: Simon Rokicki, Erven Rohou and Steven Derrien, IRISA, Rennes, FR Abstract Single-ISA heterogeneous systems (such as ARM big.LITTLE) are an attractive solution for embedded platforms as they expose many performance and energy consumption trade-offs directly to the operating system. Recent works have demonstrated the ability to increase their efficiency by using VLIW cores, supported through Dynamic Binary Translation (DBT). Such an approach exposes even more heterogeneity while maintaining the illusion of a single-ISA system. However, VLIW cores cannot rival with Out-of-Order (OoO) cores when it comes to performance. One of the reason is that OoO cores heavily rely on speculative execution. In this work, we study how it is possible to take advantage of memory dependency speculation during the DBT process. More specifically, our approach builds on a hardware accelerated DBT framework, which enables fine-grained dynamic iterative optimizations. This is achieved through a combination of hardware and software, following the principles of co-designed machines. The experimental study conducted demonstrates that our approach leads to a geo-mean speed-up of 20% while keeping the hardware overhead low. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | End of session Coffee Break in Exhibition Area
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
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