Date: Tuesday 26 March 2019
Time: 14:30 - 16:00
Location / Room: Room 2
Organisers:
Partha Pande, Washington State University, US
Jörg Henkel, KIT, DE
Chair:
Petru Eles, Linkoping University, SE
Co-Chair:
Sudeep Pasricha, Colorado State University, US
We experience a phenomenal growth in exciting, yet demanding, application areas such as deep learning, graph analytics, and scientific computing. These application areas have driven a demand for new devices that package high-performance computing into smaller form-factors that operate in heavily constrained application scenarios (e.g., deep learning inference in embedded systems). Naturally, this presents new design challenges to meet ever increasing performance, cost, and energy efficiency requirements. This special session will consider a holistic approach to the broad topic of heterogeneous architectures. Towards this end, it consists of three forward-looking talks addressing the fundamental challenges, existing proposals, and new approaches for designing and exploring heterogeneous systems. The first talk will focus on utilizing various learning techniques to achieve thermal efficiency in a heterogeneous system. The second talk will shift the discussion toward the problems of designing these heterogeneous systems to accelerate applications. We will present innovative machine learning techniques that can be used to make efficient application-specific hardware design as easy and inexpensive as developing the corresponding application software. Finally, achieving stringent performance requirements under tight thermal constraints require a systematic stability analysis due to the positive feedback between leakage power and temperature. The third talk will present a power-temperature stability and safety analysis technique that reveals the sufficient conditions under which the power-temperature trajectory converges to a stable fixed point. The following paragraphs briefly outline each topic that will be covered in this special session.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:30 | 3.2.1 | SMART THERMAL MANAGEMENT FOR HETEROGENEOUS MULTICORES Speaker: Joerg Henkel, Chair for Embedded Systems (CES), Karlsruhe Institute of Technology (KIT), DE Authors: Joerg Henkel1, Heba Khdr2 and Martin Rapp2 1Karlsruhe Institute of Technology, DE; 2KIT, DE Abstract Abstract: Due to the discontinuation of Dennard scaling, on-chip power densities are continuously increasing along with technology scaling, and hence on-chip temperatures are elevated. Therefore, several thermal management techniques have emerged to keep the temperature of the chip within safe limits. These techniques, however, lead to performance losses which become quite significant when heterogeneous multicore architectures are considered. This might ultimately erase a big portion of the expected performance gains from the heterogeneous architectures. Thus, it is indispensable to deploy thermal management techniques that are able to make efficient decisions that satisfy temperature constraints while at the same time maximizing the performance. This talk presents smart thermal management techniques for heterogeneous multicores that exploit relevant information diverse applications scenarios to maximize the performance under temperature constraints. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 3.2.2 | DESIGN AND OPTIMIZATION OF HETEROGENEOUS MANYCORE SYSTEMS ENABLED BY EMERGING INTERCONNECT TECHNOLOGIES: PROMISES AND CHALLENGES Speaker: Ryan Kim, Colorado State University, US Authors: Biresh Kumar Joardar1, Ryan Kim2, Janardhan Rao Doppa1 and Partha Pratim Pande1 1Washington State University, US; 2Colorado State University, US Abstract Due to the growing needs of Big Data computing applications (e.g., deep learning, graph analytics, and scientific computing) and the ending of Moore's law, there is a great need for low-cost, high-performance, and energy-efficient commodity many-core systems. However, with more stringent design objectives, application specialization, and more cores on a single chip, design-time optimization decisions become more complex. Moreover, with the advent of emerging interconnect technologies, like 3D integration makes the design optimization process more challenging. This increases the need for a holistically optimized design process that makes design decisions across multiple layers of the system, e.g., memory, compute, interconnect technology and network infrastructure. In this paper, we will present various challenges of designing heterogeneous manycore architectures using emerging interconnect technologies and associated optimization techniques. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | 3.2.3 | POWER AND THERMAL ANALYSIS OF COMMERCIAL MOBILE PLATFORMS: EXPERIMENTS AND CASE STUDIES Speaker: Umit Ogras, Arizona State University, US Authors: Ganapati Bhat1, Suat Gumussoy2 and Umit Ogras1 1Arizona State University, US; 2Mathworks, US Abstract State-of-the-art mobile processors can deliver fast response time and high throughput to maximize the user experience. However, high performance also comes at the expense of increasing power consumption and chip temperature which severely limit applications from utilizing the full capabilities of the system. Higher operating temperatures also drive up the skin temperature, further deteriorating the user experience. Therefore, there is a strong need for analysis of power consumption and thermal behavior in mobile processors. In this paper, we present power and thermal models to analyze the power and thermal dynamics. We illustrate our models with experiments and case studies on two commercial system-on-chips used in Galaxy S4 and Nexus 6P smartphones. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | End of session Coffee Break in Exhibition Area
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
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