Date: Tuesday 26 March 2019
Time: 11:30 - 13:00
Location / Room: Room 5
Chair:
Georges Gielen, KU Leuven, BE
Co-Chair:
Manuel Barragan, TIMA, FR
The session presents techniques to analyse and optimize analog/mixed-signal circuits towards high reliability and security, addressing IR-aware routing, lifetime-aware optimization as well as securing mixed-signal circuits via logic locking.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:30 | 2.5.1 | (Best Paper Award Candidate) IR-AWARE POWER NET ROUTING FOR MULTI-VOLTAGE MIXED-SIGNAL DESIGN Speaker: Mark Po-Hung Lin, National Chung Cheng University, TG Authors: Shuo-Hui Wang, Yen-Yu Su, Guan-Hong Liou and Mark Po-Hung Lin, National Chung Cheng University, TW Abstract Modern mixed-signal design usually contains multiple power signals with different supply voltages driving different sets of mixed-signal circuit blocks. As the process technology advances to nanometer era, IR drop becomes very significant, which may have great impact on circuit performance and reliability. Insufficient power supply to a circuit block will lead to performance degradation or even functional failure. Although such IR-drop problem can be minimized by widening metal wires or applying mesh routing structures of the power network, extra metal usage of those power nets with different supply voltages will significantly increase both chip area and cost. This paper presents a new IR-aware routing method to route multiple power nets simultaneously with the considerations of routing congestion, routing tree splitting, wire tapering, and metal layer optimization. Experimental results show that the presented method can effectively reduce total metal usage and satisfy IR-drop constraints. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:00 | 2.5.2 | GENERATION OF LIFETIME-AWARE PARETO-OPTIMAL FRONTS USING A STOCHASTIC RELIABILITY SIMULATOR Authors: Antonio Toro-Frias1, Pablo Saraza-Canflanca1, Fabio Passos1, Pablo Martin-Lloret1, Rafael Castro-Lopez1, Elisenda Roca1, Javier Martin-Martinez2, Rosana Rodriguez2, Montserrat Nafria2 and Francisco Vidal Fernandez1 1Instituto de Microelectrónica de Sevilla, ES; 2Universitat Autonoma de Barcelona, ES Abstract Process variability and time-dependent variability have become major concerns in deeply-scaled technologies. Two of the most important time-dependent variability phenomena are Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI), which can critically shorten the lifetime of circuits. Both BTI and HCI reveal a discrete and stochastic behavior in the nanometer scale, and, while process variability has been extensively treated, there is a lack of design methodologies that address the joint impact of these two phenomena on circuits. In this work, an automated and time-efficient design methodology that takes into account both process and time-dependent variability is presented. This methodology is based on the utilization of lifetime-aware Pareto-Optimal Fronts (POFs). The POFs are generated with a multi-objective optimization algorithm linked to a stochastic simulator. Both the optimization algorithm and the simulator have been specifically tailored to reduce the computational cost of the accurate evaluation of the impact on a circuit of both sources of variability. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | 2.5.3 | MIXLOCK: SECURING MIXED-SIGNAL CIRCUITS VIA LOGIC LOCKING Speaker: Julian Leonhard, Sorbonne Université, CNRS, LIP6, FR Authors: Julian Leonhard1, Muhammad Yasin2, Shadi Turk3, Mohammed Thari Nabeel4, Marie-Minerve Louërat1, Roselyne Chotin-Avot1, Hassan Aboushady1, Ozgur Sinanoglu4 and Haralampos-G. Stratigopoulos1 1Sorbonne Université, CNRS, LIP6, FR; 2New York University, US; 3Seamless Waves, FR; 4New York University Abu Dhabi, AE Abstract In this paper, we propose a hardware security methodology for mixed-signal Integrated Circuits (ICs). The proposed methodology can be used as a countermeasure for IC piracy, including counterfeiting and reverse engineering. It relies on logic locking of the digital section of the mixed-signal IC, such that unless the correct key is provided, the mixed-signal performance will be pushed outside of the acceptable specification range. We employ a state-of-the-art logic locking technique, called Stripped Functionality Logic Locking (SFLL). We show that strong security levels are achieved in both mixed-signal and digital domains. In addition, the proposed methodology presents several appealing properties. It is non-intrusive for the analog section, it incurs reasonable area and power overhead, it can be fully automated, and it is virtually applicable to a wide range of mixed-signal ICs. We demonstrate it on a Sigma-Delta Analog-to-Digital Converter (ADC). Download Paper (PDF; Only available from the DATE venue WiFi) |
| 13:00 | IP1-7, 364 | ON THE USE OF CAUSAL FEATURE SELECTION IN THE CONTEXT OF MACHINE-LEARNING INDIRECT TEST Speaker: Manuel Barragán, TIMA laboraory, FR Authors: Manuel Barragan1, Gildas Leger2, Florent Cilici3, Estelle Lauga-Larroze4, Sylvain Bourdel4 and Salvador Mir3 1TIMA Laboratory, FR; 2Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES; 3TIMA, FR; 4RFICLab, FR Abstract The test of analog, mixed-signal and RF (AMS-RF) circuits is still considered as a matter of human creativity, and although many attempts have been made towards their automation, no accepted and complete solution is yet available. Indeed, capturing the design knowledge of an experienced analog designer is one of the key challenges faced by the Electronic Design Automation (EDA) community. In this paper we explore the use of causal inference tools in the context of AMS-RF design and test with the goal of defining a methodology for uncovering the root causes of performance variation in these systems. We believe that such an analysis can be a promising first step for future EDA algorithms for AMS-RF systems. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 13:00 | End of session Lunch Break in Lunch Area
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
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