Date: Thursday 28 March 2019
Time: 11:00 - 12:30
Location / Room: Room 5
Chair:
Olivier Sentieys, INRIA, FR
Co-Chair:
Hamid Tabani, Barcelona Supercomputing Center, BSC, ES
This session deals with some solutions to improve memory and storage throughput and latency. The first two papers propose solutions for SSD-based storage while the latter covers data placement and management in CPU-FPGA multicore systems.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 10.5.1 | (Best Paper Award Candidate) HOTR: ALLEVIATING READ/WRITE INTERFERENCE WITH HOT READ DATA REPLICATION FOR FLASH STORAGE Speaker: Hong Jiang, The University of Texas at Arlington, US Authors: Suzhen Wu1, Weiwei Zhang1, Bo Mao1 and Hong Jiang2 1Xiamen University, CN; 2The University of Texas at Arlington, US Abstract The read/write interference problem of flash storage remains a critical concern under workloads with a mixture of read and write requests. To significantly improve the read performance in face of read/write interference, we propose a Hot Data Replication scheme for flash storage, called HotR. HotR utilizes the asymmetric read and write performance characteristics of flash-based SSDs and outsources the popular read data to a surrogate space such as a dedicated spare flash chip or an over-provisioned space within an SSD. By servicing some conflicted read requests on the surrogate flash space, HotR can alleviate, if not entirely eliminate, the contention between the read requests and the on-going write requests. The evaluation results show that HotR improves the state-of-the-art scheme in the system performance and cost efficiency significantly. Consequently, the tail-latency of the flash-based storage systems is also reduced. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 11:30 | 10.5.2 | RAFS: A RAID-AWARE FILE SYSTEM TO REDUCE THE PARITY UPDATE OVERHEAD FOR SSD RAID Speaker: Chenlei Tang, Huazhong University of Science and Technology, CN Authors: Chenlei Tang1, Jiguang Wan1, Yifeng Zhu2, Zhiyuan Liu1, Peng Xu1, Fei Wu1 and Changsheng Xie1 1Huazhong University of Science and Technology, CN; 2University of Maine, US Abstract In a parity-based SSD RAID, small write requests not only accelerate the wear-out of SSDs due to extra writes for updating parities but also deteriorate performance due to associated expensive garbage collection. To mitigate the problem of small writes, a buffer is often added at the RAID controller to absorb overwrites and writes performed to the same stripe. However, this approach achieves only suboptimal efficiency because file layout information is invisible at the block level. This paper proposes RAFS, a RAID-aware file system, which utilizes a RAID-friendly data layout to improve the reliability and performance of SSD-based RAID 5. By leveraging delayed allocation of modern file systems, RAFS employs a stripe-aware buffer policy to coalesce writes to the same file. To reduce parity updates, RAFS compacts buffered updates and flushes back in stripe units to mitigate the parity update overhead. RAFS adopts a stripe-granularity allocation scheme to align writes to stripe boundaries. Experimental results show that RAFS can improve throughput by up to 90%, compared to Ext4. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:00 | 10.5.3 | AUTOMATIC DATA PLACEMENT FOR CPU-FPGA HETEROGENEOUS MULTIPROCESSOR SYSTEM-ON-CHIPS Speaker: Shiqing Li, Shandong University, CN Authors: Shiqing Li, Yixun Wei and Lei Ju, Shandong University, CN Abstract Efficient utilization of restrained memory resources is of paramount importance in CPU-FPGA heterogeneous multiprocessor system-on-chip (HMPSoC) based system design for memory-intensive applications. State-of-the-art high level synthesis (HLS) tools rely on the system programmers to manually determine the data placement within the complex memory hierarchy. In this paper, we propose an automatic data placement framework which can be seamlessly integrated with the commercial Vivado HLS. We first show counter-intuitive results that traditional frequency and locality based data placement strategy designed for CPU architecture leads to non-optimal system performance in CPU-FPGA HMPSoCs. Built on top of our memory latency analysis model, the proposed integer linear programming (ILP) based framework determines whether each array object should be access via the on-chip BRAM, shared CPU L2-cache, or DDR memory directly. Experimental results on the Zedboard platform show an average 1.39X performance speedup compared with a greedy-based allocation strategy. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | IP5-5, 482 | IGNORETM: OPPORTUNISTICALLY IGNORING TIMING VIOLATIONS FOR ENERGY SAVINGS USING HTM Speaker: Dimitra Papagiannopoulou, University of Massachusetts Lowell, US Authors: Dimitra Papagiannopoulou1, Sungseob Whang2, Tali Moreshet3 and Iris Bahar4 1University of Massachusetts Lowell, US; 2CloudHealth Technologies, US; 3Boston University, US; 4Brown University, US Abstract Energy consumption is the dominant factor in many computing systems. Voltage scaling is a widely used technique to lower energy consumption, which exploits supply voltage margins to ensure reliable circuit operation. Aggressive voltage scaling will slow signal propagation; without coherent frequency relaxation, timing violations may be generated. Hardware Transactional Memory (HTM) offers an error recovery mechanism that allows reliable execution and power savings with modest overhead. We propose IgnoreTM, an adaptive error management framework, that tolerates (i.e., opportunistically ignores) timing violations, allowing for more aggressive voltage scaling. Our experimental results show that IgnoreTM allows up to 47% total energy savings with negligible impact on runtime. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | End of session Lunch Break in Lunch Area
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
|