Date: Thursday 28 March 2019
Time: 11:00 - 12:30
Location / Room: Room 1
Chair:
Andreas Gerstlauer, University of Texas at Austin, US
Co-Chair:
Patricia Derler, National Instruments, US
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 10.1.1 | EMBEDDED SYSTEMS' AUTOMATION FOLLOWING OMG'S MODEL DRIVEN ARCHITECTURE VISION Speaker: Wolfgang Ecker, Infineon Technologies AG, DE Authors: Wolfgang Ecker1, Keerthikumara Devarajegowda2, Michael Werner3, Zhao Han3 and Lorenzo Servadei4 1Infineon Technologies AG / TU Munich, DE; 2Infineon Technologies AG/TU Kaiserslautern, DE; 3Infineon Technologies AG / TU Munich, DE; 4Infineon Technologies AG/Johannes Kepler University Linz, DE Abstract This paper presents an automated process for end- to-end embedded system design following OMG's model driven architecture (MDA) vision. It tackles a major challenge in automation: bridging the large semantic gap between the specifi- cation and the target code. The shown MDA adaption proposes an uniform and systematic way by splitting the translation process into multiple layers and introducing design platform independent and implementation independent views. In our adaption of MDA, we start with a formalized specification and we end with code (view) generation. The code is then compiled (software) or synthesized (hardware) and finally as- sembled to the embedded system design. We split the translation process in Model-of-Thing (MoT), Model-of-Design (MoD) and Model-of-View (MoV) layers. MoTs represent the formalized specification, MoDs contain the implementation architecture in a view independent way, and MoVs are implementation dependent and view dependent, i.e., specific details in target language. MoT is translated to MoD, MoD is translated to MoV and MoV is finally used to generate views. The translation between the Models is based on templates, that reflect design and coding blueprints. The final step of the view generation is itself part of generation. The Model MoV and the unparse method are generated from a view language description. The approach has been successfully adapted for generating digital hardware (RTL), properties for verification (SVA), and snippets of firmware that have been successfully synthesized to an FPGA. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 11:30 | 10.1.2 | FORMAL COMPUTATION MODELS IN NEUROMORPHIC COMPUTING: CHALLENGES AND OPPORTUNITIES Speaker and Author: Orlando Moreira, GrAI Matter Labs, NL Abstract Neuromorphic computing is expected to enable ultra-low power solutions for inference-based computational functions, especially for real-time event-based systems. At the heart of the approach is the concept of Spiking Neural Networks (SNNs). SNNs can be thought of as a family of models of computation, each representing a different trade-off between computational efficiency and functional accuracy. In this talk, we will review SNN models and we will have a look at their fundamental analytical properties. We will discuss the challenge of selecting an adequate SNN model for hardware implementation, and the need for new approaches to analysis, functional composability, verification and testing. This is, at least partially, because in SNNs, contrary to popular concurrency models like Kahn Process Networks or Data Flow, event arrival times are intrinsic to the functional behavior of a graph. |
| 12:00 | 10.1.3 | AUTOMATED SIGNAL PROCESSING DESIGN THROUGH BAYESIAN MODEL-BASED MACHINE LEARNING Speaker and Author: Bert de Vries, GN ReSound, NL |
| 12:30 | End of session Lunch Break in Lunch Area
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
|