Date: Wednesday 11 March 2020
Time: 14:30 - 16:00
Location / Room: Stendhal
Chair:
Avi Ziv, IBM, IL
Co-Chair:
Graziano Pravadelli, Università di Verona, IT
This session presents recent concerns and innovative solutions in verification and simulation, covering topics ranging from partial verification to lazy event prediction, till signal name disambiguation.They tackle these challenges by reducing complexity, exploiting GPUs, and using similarity-learning techniques.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:30 | 7.4.1 | VERIFICATION RUNTIME ANALYSIS: GET THE MOST OUT OF PARTIAL VERIFICATION Authors: Martin Ring1, Fritjof Bornbebusch1, Christoph Lüth2, Robert Wille3 and Rolf Drechsler2 1DFKI, DE; 2University of Bremen / DFKI, DE; 3Johannes Kepler University Linz, AT Abstract The design of modern systems has reached a complexity which makes it inevitable to apply verification methods in order to guarantee its correct and safe execution. The verification methods frequently produce proof obligations that can not be solved any more due to the huge search space. However, by setting enough variables to fixed values, the search space is obviously reduced and solving engines eventually may be able to complete the verification task. Although this results in a partial verification, the results may still be valuable --- in particular as opposed to the alternative of no verification at all. However, so far no systematic investigation has been conducted on which variables to fix in order to reduce verification runtime as much as possible while, at the same time, still getting most coverage. This paper addresses this question by proposing a corresponding verification runtime analysis. Experimental evaluations confirm the potential of this approach. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 7.4.2 | GPU-ACCELERATED TIME SIMULATION OF SYSTEMS WITH ADAPTIVE VOLTAGE AND FREQUENCY SCALING Speaker: Eric Schneider, University of Stuttgart, DE Authors: Eric Schneider and Hans-Joachim Wunderlich, University of Stuttgart, DE Abstract Timing validation of systems with adaptive voltage- and frequency scaling (AVFS) requires an accurate timing model under multiple operating points. Simulating such a model at gate level is extremely time-consuming, and the state-of-the-art compromises both accuracy and compute efficiency. This paper presents a method for dynamic gate delay modeling on graphics processing unit (GPU) accelerators which is based on polynomial approximation with offline statistical learning using regression analysis. It provides glitch-accurate switching activity information for gates and designs under varying supply voltages with negligible memory and performance impact. Parallelism from the evaluation of operating conditions, gates and stimuli is exploited simultaneously to utilize the high arithmetic computing throughput of GPUs. This way, large-scale design space exploration of AVFS-based systems is enabled. Experimental results demonstrate the efficiency and accuracy of the presented approach showing speedups of three orders of magnitude over conventional time simulation that supports static delays only. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | 7.4.3 | LAZY EVENT PREDICTION USING DEfiNING TREES AND SCHEDULE BYPASS FOR OUT-OF-ORDER PDES Speaker: Rainer Doemer, University of California, Irvine, US Authors: Daniel Mendoza, Zhongqi Cheng, Emad Arasteh and Rainer Doemer, University of California, Irvine, US Abstract Out-of-order parallel discrete event simulation (PDES) has been shown to be very effective in speeding up system design by utilizing parallel processors on multi- and many-core hosts. As the number of threads in the design model grows larger, however, the original scheduling approach does not scale. In this work, we analyze the out-of-order scheduler and identify a bottleneck with quadratic complexity in event prediction. We propose a more efficient lazy strategy based on defining trees and a schedule bypass with O(mlog2 m) complexity which shows sustained and improved performance gains in simulation of SystemC models with many processes. For models containing over 1000 processes, experimental results show simulation run time speedups of up to 90x using lazy event prediction against the original out-of-order PDES approach. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:45 | 7.4.4 | EMBEDDING HIERARCHICAL SIGNAL TO SIAMESE NETWORK FOR FAST NAME RECTIFICATION Speaker: Yi-An Chen, National Chiao Tung University, TW Authors: Yi-An Chen1, Gung-Yu Pan2, Che-Hua Shih2, Yen-Chin Liao1, Chia-Chih Yen2 and Hsie-Chia Chang1 1National Chiao Tung University, TW; 2Synopsys, TW Abstract EDA tools are necessary to assist complicated flow of advanced IC design and verification in nowadays industry. After synthesis or simulation, the same signal could be viewed as different hierarchical names, especially for mixed-language designs. This name mismatching problem blocks automation and needs experienced users to rectify manually with domain knowledge. Even rule-based rectification helps the process but still fails when encountering unseen mismatching types. In this paper, hierarchical name rectification is transformed into the similarity search problem where the most similar name becomes the rectified name. However, naïve full search in design with string comparison costs unacceptable time. Our proposed framework embeds name strings into vectors for representing distance relation in a latent space using character n-gram and locality-sensitive hashing (LSH), and then finds the most similar signal using nearest neighbor search (NNS) and detailed search. Learning similarity using Siamese network provides general name rectification regardless of mismatching types, while string-to-vector embedding for proximity search accelerates the rectification process. Our approach is capable of achieving 93.43% rectification rate with only 0.052s per signal, which outperforms the naïve string search with 2.3% higher accuracy and 4,500 times speed-up. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | IP3-9, 832 | TOWARDS SPECIFICATION AND TESTING OF RISC-V ISA COMPLIANCE Speaker: Vladimir Herdt, University of Bremen, DE Authors: Vladimir Herdt1, Daniel Grosse2 and Rolf Drechsler2 1University of Bremen, DE; 2University of Bremen / DFKI, DE Abstract Compliance testing for RISC-V is very important. Therefore, an official hand-written compliance test-suite is being actively developed. However, this requires significant manual effort in particular to achieve a high test coverage. In this paper we propose a test-suite specification mechanism in combination with a first set of instruction constraints and coverage requirements for the base RISC-V ISA. In addition, we present an automated method to generate a test-suite that satisfies the specification. Our evaluation demonstrates the effectiveness and potential of our method. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:01 | IP3-10, 702 | POST-SILICON VALIDATION OF THE IBM POWER9 PROCESSOR Speaker: Hillel Mendelson, IBM, IL Authors: Tom Kolan1, Hillel Mendelson1, Vitali Sokhin1, Kevin Reick2, Elena Tsanko2 and Gregory Wetli2 1IBM Research, IL; 2IBM Systems, US Abstract Due to the complexity of designs, post-silicon validation remains a major challenge with few systematic solutions. We provide an overview of the state-of-the-art post silicon validation process used by IBM to verify its latest IBM POWER9 processor. During the POWER9 post-silicon validation, we detected and handled 30% more logic bugs in 80% of the time, as compared to the previous IBMPOWER8 bring-up. This improvement is the result of lessons learned from previous designs, leading to numerous innovations. We provide bug analysis data and compare it to POWER8 results. We demonstrate our methodology by describing several bugs from fail detection to root cause. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | End of session | |