Date: Wednesday 11 March 2020
Time: 11:00 - 12:30
Location / Room: Lesdiguières
Chair:
Maria Micheal, University of Cyprus, CY
Co-Chair:
Sanchez Ernesto, Politecnico di Torino, IT
The session presents a variety of semiconductor test techniques, including a new design-for-testability scheme for FinFET SRAMs, a method to increase yield based on error-metric-independent signature analysis, and a synthesis method for fault-tolerant reconfigurable scan networks.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 6.6.1 | A DFT SCHEME TO IMPROVE COVERAGE OF HARD-TO-DETECT FAULTS IN FINFET SRAMS Speaker: Guilherme Cardoso Medeiros, TU Delft, NL Authors: Guilherme Cardoso Medeiros1, Cemil Cem Gürsoy2, Moritz Fieback1, Lizhou Wu1, Maksim Jenihhin2, Mottaqiallah Taouil1 and Said Hamdioui1 1TU Delft, NL; 2Tallinn University of Technology, EE Abstract Manufacturing defects can cause faults in FinFET SRAMs. Of them, easy-to-detect (ETD) faults always cause incorrect behavior, and therefore are easily detected by applying sequences of write and read operations. However, hard-to-detect (HTD) faults may not cause incorrect behavior, only parametric deviations. Detection of these faults is of major importance as they may lead to test escapes. This paper proposes a new design-for-testability (DFT) scheme for FinFET SRAMs to detect such faults by creating a mismatch in the sense amplifier (SA). This mismatch, combined with the defect in the cell, will incorrectly bias the SA and cause incorrect read outputs. Furthermore, post-silicon calibration schemes can be used to avoid over-testing or test escapes caused by process variation effects. Compared to the state of the art, this scheme introduces negligible overheads in area and test time while it significantly improves fault coverage and reduces the number of test escapes. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 11:30 | 6.6.2 | SYNTHESIS OF FAULT-TOLERANT RECONFIGURABLE SCAN NETWORKS Speaker: Sebastian Brandhofer, University of Stuttgart, DE Authors: Sebastian Brandhofer, Michael Kochte and Hans-Joachim Wunderlich, University of Stuttgart, DE Abstract On-chip instrumentation is mandatory for efficient bring-up, test and diagnosis, post-silicon validation, as well as in-field calibration, maintenance, and fault tolerance. Reconfigurable scan networks (RSNs) provide a scalable and efficient scan-based access mechanism to such instruments. The correct operation of this access mechanism is crucial for all manufacturing, bring-up and debug tasks as well as for in-field operation, but it can be affected by faults and design errors. This work develops for the first time fault-tolerant RSNs such that the resulting scan network still provides access to as many instruments as possible in presence of a fault. The work contributes a model and an algorithm to compute scan paths in faulty RSNs, a metric to quantify its fault tolerance and a synthesis algorithm that is based on graph connectivity and selective hardening of control logic in the scan network. Experimental results demonstrate that fault-tolerant RSNs can be synthesized with only moderate hardware overhead. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:00 | 6.6.3 | USING PROGRAMMABLE DELAY MONITORS FOR WEAR-OUT AND EARLY LIFE FAILURE PREDICTION Speaker: Chang Liu, Altran Deutschland, DE Authors: Chang Liu, Eric Schneider and Hans-Joachim Wunderlich, University of Stuttgart, DE Abstract Early life failures in marginal devices are a severe reliability threat in current nano-scaled CMOS devices. While small delay faults are an effective indicator of marginalities, their detection requires special efforts in testing by so-called Faster-than-At-Speed Test (FAST). In a similar way, delay degradation is an indicator that a device reaches the wear-out phase due to aging. Programmable delay monitors provide the possibility to detect gradual performance changes in a system and allow to observe device degradation. This paper presents a unified approach to test small delay faults related to wear-out and early-life failures by reuse of existing programmable delay monitors within FAST. The approach is complemented by a test-scheduling which optimally selects frequencies and delay configurations to significantly increase the fault coverage of small delays and to reduce the test time. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:15 | 6.6.4 | MAXIMIZING YIELD FOR APPROXIMATE INTEGRATED CIRCUITS Speaker: Marcello Traiola, Université de Montpellier, FR Authors: Marcello Traiola1, Arnaud Virazel1, Patrick Girard2, Mario Barbareschi3 and Alberto Bosio4 1LIRMM, FR; 2LIRMM / CNRS, FR; 3Università di Napoli Federico II, IT; 4Lyon Institute of Nanotechnology, FR Abstract Approximate Integrated Circuits (AxICs) have emerged in the last decade as an outcome of Approximate Computing (AxC) paradigm. AxC focuses on efficiency of computing systems by sacrificing some computation quality. As AxICs spread, consequent challenges to test them arose. On the other hand, the opportunity to increase the production yield emerged in the AxIC context. Indeed, some particular defects in the manufactured AxIC might not catastrophically impact the final circuit quality. Therefore, some defective AxICs might still be acceptable. Efforts to detect favorable conditions to consider defective AxICs as acceptable - with the goal to increase the production yield - have been done in last years. Unfortunately, the final achieved yield gain is often not as high as expected. In this work, we propose a methodology to actually achieve a yield gain as close as possible to expectations, by proposing a technique to suitably apply tests to AxICs. Experiments carried out on state-of-the-art AxICs show yield gain results very close to the expected ones (i.e., between 98% and 100% of the expectations). Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | IP3-6, 359 | FAULT DIAGNOSIS OF VIA-SWITCH CROSSBAR IN NON-VOLATILE FPGA Speaker: Ryutaro Doi, Osaka University, JP Authors: Ryutaro DOI1, Xu Bai2, Toshitsugu Sakamoto2 and Masanori Hashimoto1 1Osaka University, JP; 2NEC Corporation, JP Abstract FPGA that exploits via-switches, which are a kind of non-volatile resistive RAMs, for crossbar implementation is attracting attention due to its high integration density and energy efficiency. Via-switch crossbar is responsible for the signal routing by changing on/off-states of via-switches. To verify the via-switch crossbar functionality after manufacturing, fault testing that checks whether we can turn on/off via-switches normally is essential. This paper confirms that a general differential pair comparator successfully discriminates on/off-states of via-switches, and clarifies fault modes of a via-switch by transistor-level SPICE simulation that injects stuck-on/off faults to atom switch and varistor, where a via-switch consists of two atom switches and two varistors. We then propose a fault diagnosis methodology that diagnoses the fault modes of each via-switch using the comparator response difference between normal and faulty via-switches. The proposed method achieves 100% fault detection by checking the comparator responses after turning on/off the via-switch. In case that the number of faulty components in a via-switch is one, the ratio of the fault diagnosis, which exactly identifies the faulty varistor and atom switch inside the faulty via-switch, is 100%, and in case of up to two faults, the fault diagnosis ratio is 79%. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | End of session | |