Date: Wednesday 11 March 2020
Time: 11:00 - 12:30
Location / Room: Amphithéâtre Jean Prouve
Chair:
Carlo Reita, CEA, FR
Co-Chair:
Bernabe Linares-Barranco, CSIC, ES
This session focuses on the advantages and use of novel emerging nanotechnology devices and their use in designing circuits and systems for embedded AI hardware solutions.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 6.1.1 | IN-MEMORY RESISTIVE RAM IMPLEMENTATION OF BINARIZED NEURAL NETWORKS FOR MEDICAL APPLICATIONS Speaker: Damien Querlioz, University Paris-Saclay, FR Authors: Bogdan Penkovsky1, Marc Bocquet2, Tifenn Hirtzlin1, Jacques-Olivier Klein1, Etienne Nowak3, Elisa Vianello3, Jean-Michel Portal2 and Damien Querlioz4 1Université Paris-Saclay, FR; 2Aix-Marseille University, FR; 3CEA-Leti, FR; 4Université Paris-Sud, FR Abstract The advent of deep learning has considerably accelerated machine learning development, but its development at the edge is limited by its high energy cost and memory requirement. With new memory technology available, emerging Binarized Neural Networks (BNNs) are promising to reduce the energy impact of the forthcoming machine learning hardware generation, enabling machine learning on the edge devices and avoiding data transfer over the network. In this work, after presenting our implementation employing a hybrid CMOS -hafnium oxide resistive memory technology, we suggest strategies to apply BNNs to biomedical signals such as electrocardiography and electroencephalography, keeping accuracy level and reducing memory requirements. These results are obtained in binarizing solely the classifier part of a neural network. We also discuss how these results translate to the edge-oriented Mobilenet V1 neural network on the Imagenet task. The final goal of this research is to enable smart autonomous healthcare devices. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 11:22 | 6.1.2 | MIXED-SIGNAL VECTOR-BY-MATRIX MULTIPLIER CIRCUITS BASED ON 3D-NAND MEMORIES FOR NEUROMORPHIC COMPUTING Speaker: Dmitri Strukow, University of California, Santa Barbara, US Authors: Mohammad Bavandpour, Shubham Sahay, Mohammad Mahmoodi and Dmitri Strukov, University of California, Santa Barbara, US Abstract We propose an extremely dense, energy-efficient mixed-signal vector-by-matrix-multiplication (VMM) circuits based on the existing 3D-NAND flash memory blocks, without any need for their modification. Such compatibility is achieved using time-domain-encoded VMM design. We have performed rigorous simulations of such a circuit, taking into account non-idealities such as drain-induced barrier lowering, capacitive coupling, charge injection, parasitics, process variations, and noise. Our results, for example, show that the 4-bit VMM of 200-element vectors, using the commercially available 64-layer gate-all-around macaroni-type 3D-NAND memory blocks designed in the 55-nm technology node, may provide an unprecedented area efficiency of 0.14 μm 2 /byte and energy efficiency of ~11 fJ/Op, including the input/output and other peripheral circuitry overheads. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 11:44 | 6.1.3 | MODULAR RRAM BASED IN-MEMORY COMPUTING DESIGN FOR EMBEDDED AI Authors: Xinxin Wang, Qiwen Wang, Mohammed A. Zidan, Fan-Hsuan Meng, John Moon and Wei Lu, University of Michigan, US Abstract Deep Neural Networks (DNN) are widely used for many artificial intelligence applications with great success. However, they often come with high computation cost and complexity. Accelerators are crucial in improving energy efficiency and throughput, particularly for embedded AI applications. Resistive random-access memory (RRAM) has the potential to enable efficient AI accelerator implementation, as the weights can be mapped as the conductance values of RRAM devices and computation can be directly performed in-memory. Specifically, by converting input activations into voltage pulses, vector-matrix multiplications (VMM) can be performed in analog domain, in place and in parallel. Moreover, the whole model can be stored on-chip, thus eliminating off-chip DRAM access completely and achieving high energy efficiency during the end-to-end operation. In this presentation, we will discuss how practical DNN models can be mapped onto realistic RRAM arrays in a modular design. Challenges such as quantization effects, finite array size, and device non-idealities on the system performance will be analyzed through standard DNN models such as VGG-16 and MobileNet. System performance metrics such as throughput and energy/image will also be discussed. |
| 12:06 | 6.1.4 | NEUROMORPHIC COMPUTING: TOWARD DYNAMICAL DATA PROCESSING Author: Fabian Alibart, CNRS, Lille, FR Abstract While machine-learning approaches have done tremendous progresses these last years, more is expected with the third generation of neural networks that should sustain this evolution. In addition to unsupervised learning and spike-based computing capability, this new generation of computing machines will be intrinsically dynamical systems that will shift our conception of electronic. In this context, investigating new material implementation of neuromorphic concept seems a very attracting direction. In this presentation, I will present our recent efforts toward the development of neuromorphic synapses that present attractive features for both spike-based computing and unsupervised learning. From their basic physics, I will show how their dynamics can be used to implement time-dependent computing functions. I will also extend this idea of dynamical computing to the case of reservoir computing based on organic sensors in order to show how neuromorphic concepts can be applied to a large class of dynamical problems. |
| 12:30 | End of session | |