Date: Wednesday 11 March 2020
Time: 08:30 - 10:00
Location / Room: Amphithéâtre Jean Prouve
Chair:
Dmitri Strukov, University of California, Santa Barbara, US
Co-Chair:
Bernabe Linares-Barranco, CSIC, ES
This session aims to provide a more tutorial overview of hardware AI case studies and some proposed solutions, problems, and challenges.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 5.1.1 | NEURAL NETWORKS CIRCUITS BASED ON RESISTIVE MEMORIES Author: Carlo Reita, CEA, FR Abstract In recent years, the field of Neural Networks has found a new golden age after nearly twenty years of lessened interest. Under the heading of Artificial Intelligence (AI) a large number of Deep Neural Netwooks (DNNs) have recently found application in image processing, management of information in large databases, decision aids, natural language recognition, etc. Most of these applications rely on algorithms that run on standard computing systems and sometimes make use of specific accelerators like Graphic Processor Units (GPUs) or dedicated highly parallel processors. In effect, a common operation in all NN algorithms is the scalar product of two vectors and its optimisation is of paramount importance to reduce computational time and energy. In particular, the energy element is relevant for all embedded applications that cannot rely on cooling and/or unlimited power supply. The availability of resistive memories, with their unique capability of both storing computational values and of performing analog multiplication by the use of ohm's law, allows new circuit architectures where the latency, bandwidth limitations and power consumption issues associated to the use of conventional SRAM, DRAM and Flash memories can be greatly improved upon. In the presentation, some examples of advantageous use of resistive memories in NN circuits will be shown and some of their peculiarities will be discussed. |
| 09:15 | 5.1.2 | EXPLOITING ACTIVATION SPARSITY IN DRAM-BASED SCALABLE CNN AND RNN ACCELERATORS Author: Tobi Delbrück, ETH Zurich, CH Abstract Large deep neural networks (DNNs) need lots of fast memory for states and weights. Although DRAM is the dominant high-throughput, low-cost memory (costing 20X less than SRAM), its long random access latency is bad for the unpredictable access patterns in spiking neural networks (SNNs). But sparsely active SNNs are key to biological computational efficiency. This talk reports on our 5 year developments of convolutional and recurrent deep neural network hardware accelerators that exploit spatial and temporal sparsity like SNNs but achieve SOA throughput, power efficiency and latency using DRAM for the large weight and state memory required by powerful DNNs. |
| 10:00 | End of session | |