UB01 Session 1 Booth 11, Exhibition Area 1030 - 1230 1030 Fuzzing Embedded Binaries leveraging SystemC-based Virtual Prototypes Authors: Vladimir Herdt¹, Daniel Grosse² and Rolf Drechsler^{2 1}DFKI, DE; ²University of Bremen / DFKI GmbH, DE 1030 Skeletor: An Open Source EDA Tool Flow from Hierarchy Specification to HDL Development Authors: Ivan Rodriguez, Guillem Cabo, Javier Barrera, Jeremy Giesen, Alvaro Jover and Leonidas Kosmidis, BSC / UPC, ES 1030 Lagarto: First Silicon RISC-V Academic Processor Developed in Spain Authors: Guillem Cabo Pitarch¹, Cristobal Ramirez Lazo¹, Julian Pavon Rivera¹, Vatistas Kostalabros¹, Carlos Rojas Morales¹, Miquel Moreto¹, Jaume Abella¹, Francisco J. Cazorla¹, Adrian Cristal¹, Roger Figueras¹, Alberto Gonzalez¹, Carles Hernandez¹, Cesar Hernandez², Neiel Leyva², Joan Marimon¹, Ricardo Martinez³, Jonnatan Mendoza¹, Francesc Moll⁴, Marco Antonio Ramirez², Carlos Rojas¹, Antonio Rubio⁴, Abraham Ruiz¹, Nehir Sonmez¹, Lluis Teres³, Osman Unsal⁵, Mateo Valero¹, Ivan Vargas¹ and Luis Villa^{2 1}BSC / UPC, ES; ²CIC-IPN, MX; ³IMB-CNM (CSIC), ES; ⁴UPC, ES; ⁵BSC, ES 1030 Parallel Algorithm for CNN Inference and its Automatic Synthesis Authors: Takashi Matsumoto, Yukio Miyasaka, Xinpei Zhang and Masahiro Fujita, University of Tokyo, JP 1030 FasThermSim: Fast and Accurate Thermal Simulations from Chiplets to System Authors: Yu-Min Lee, Chi-Wen Pan, Li-Rui Ho and Hong-Wen Chiou, National Chiao Tung University, TW 1030 INTACT: A 96-core Processor with 6 Chiplets 3D-stacked on an Active Interposer and a 16-core Prototype Running Graphical Operating System Authors: Eric Guthmuller¹, Pascal Vivet¹, César Fuguet¹, Yvain Thonnart¹, Gaël Pillonnet² and Fabien Clermidy^{1 1}Université Grenoble Alpes / CEA List, FR; ²Université Grenoble Alpes / CEA-Leti, FR 1030 EEC: Energy Efficient Computing via Dynamic Voltage Scaling and In-Network Optical Processing Authors: Ryosuke Matsuo¹, Jun Shiomi¹, Yutaka Masuda² and Tohru Ishihara^{2 1}Kyoto University, JP; ²Nagoya University, JP 1030 CATANIS: CAD Tool for Automatic Network Synthesis Authors: Davide Quaglia, Enrico Fraccaroli, Filippo Nevi and Sohail Mushtaq, Università di Verona, IT 1030 Pre-Impact Fall Detection Architecture based on Neuromuscular Connectivity Statistics Authors: Giovanni Mezzina, Sardar Mehboob Hussain and Daniela De Venuto, Politecnico di Bari, IT 1030 JOINTER: JOining flexIble moNitors wiTh hEterogeneous architectuRes Authors: Giacomo Valente¹, Tiziana Fanni², Carlo Sau³, Claudio Rubattu², Francesca Palumbo² and Luigi Pomante^{1 1}Università degli Studi dell'Aquila, IT; ²Università degli Studi di Sassari, IT; ³Università degli Studi di Cagliari, IT UB02 Session 2 Booth 11, Exhibition Area 1230 - 1500 1230 Fletcher: Transparent Generation of Hardware Interfaces for Accelerating Big Data Applications Authors: Zaid Al-Ars, Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel and Joost Hoozemans, TU Delft, NL 1230 A Digital Microfluidics Bio-Computing Platform Authors: Georgi Tanev, Luca Pezzarossa, Winnie Edith Svendsen and Jan Madsen, TU Denmark, DK 1230 Virtual Platforms for Complex Software Stacks Authors: Lukas Jünger and Rainer Leupers, RWTH Aachen University, DE 1230 FPGA-DSP: A Prototype for High Quality Digital Audio Signal Processing based on an FPGA Authors: Bernhard Riess and Christian Epe, University of Applied Sciences Düsseldorf, DE 1230 At-speed DfT Architecture for Bundled-data Circuits Authors: Ricardo Aquino Guazzelli and Laurent Fesquet, Université Grenoble Alpes, FR 1230 INTACT: A 96-core Processor with 6 Chiplets 3D-stacked on an Active Interposer and a 16-core Prototype Running Graphical Operating System Authors: Eric Guthmuller¹, Pascal Vivet¹, César Fuguet¹, Yvain Thonnart¹, Gaël Pillonnet² and Fabien Clermidy^{1 1}Université Grenoble Alpes / CEA List, FR; ²Université Grenoble Alpes / CEA-Leti, FR 1230 Generating Asynchronous Circuits from Catapult Authors: Yoan Decoudu¹, Jean Simatic², Katell Morin-Allory³ and Laurent Fesquet^{3 1}University Grenoble Alpes, FR; ²HawAI.Tech, FR; ³Université Grenoble Alpes, FR 1230 Wallance: an Alternative to Blockchain for IoT Authors: Loic Dalmasso, Florent Bruguier, Pascal Benoit and Achraf Lamlih, Université de Montpellier, FR 1230 Pre-Impact Fall Detection Architecture based on Neuromuscular Connectivity Statistics Authors: Giovanni Mezzina, Sardar Mehboob Hussain and Daniela De Venuto, Politecnico di Bari, IT 1230 JOINTER: JOining flexIble moNitors wiTh hEterogeneous architectuRes Authors: Giacomo Valente¹, Tiziana Fanni², Carlo Sau³, Claudio Rubattu², Francesca Palumbo² and Luigi Pomante^{1 1}Università degli Studi dell'Aquila, IT; ²Università degli Studi di Sassari, IT; ³Università degli Studi di Cagliari, IT UB03 Session 3 Booth 11, Exhibition Area 1500 - 1730 1500 Fletcher: Transparent Generation of Hardware Interfaces for Accelerating Big Data Applications Authors: Zaid Al-Ars, Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel and Joost Hoozemans, TU Delft, NL 1500 Elsa: Eigenvalue based hybrid linear system abstraction: Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata Authors: Ahmad Tarraf and Lars Hedrich, University of Frankfurt, DE 1500 PAFUSI: Particle Filter Fusion ASIC for Indoor Positioning Authors: Christian Schott, Marko Rößler, Daniel Froß, Marcel Putsche and Ulrich Heinkel, TU Chemnitz, DE 1500 FPGA-DSP: A Prototype for High Quality Digital Audio Signal Processing based on an FPGA Authors: Bernhard Riess and Christian Epe, University of Applied Sciences Düsseldorf, DE 1500 LeaRnV: LeaRnV: a RISC-V based Embedded System Design Framework for Education and Research Development Authors: Noureddine Ait Said and Mounir Benabdenbi, TIMA Laboratory, FR 1500 CSI-REPUTE: A Low Power Embedded Device Clustering Approach to Genome Read Mapping Authors: Tousif Rahman¹, Sidharth Maheshwari¹, Rishad Shafik¹, Ian Wilson¹, Alex Yakovlev¹ and Amit Acharyya^{2 1}Newcastle University, GB; ²IIT Hyderabad, IN 1500 Fuzzing Embedded Binaries leveraging SystemC-based Virtual Prototypes Authors: Vladimir Herdt¹, Daniel Grosse² and Rolf Drechsler^{2 1}DFKI, DE; ²University of Bremen / DFKI GmbH, DE 1500 Wallance: an Alternative to Blockchain for IoT Authors: Loic Dalmasso, Florent Bruguier, Pascal Benoit and Achraf Lamlih, Université de Montpellier, FR 1500 RUMORE: A Framework for RUntime MOnitoring and TRacE Analysis for Component-based Embedded Systems Design Flow Authors: Vittoriano Muttillo¹, Luigi Pomante¹, Giacomo Valente¹, Hector Posadas², Javier Merino² and Eugenio Villar^{2 1}University of L'Aquila, IT; ²University of Cantabria, ES 1500 FasThermSim: Fast and Accurate Thermal Simulations from Chiplets to System Authors: Yu-Min Lee, Chi-Wen Pan, Li-Rui Ho and Hong-Wen Chiou, National Chiao Tung University, TW UB04 Session 4 Booth 11, Exhibition Area 1730 - 1930 1730 Fletcher: Transparent Generation of Hardware Interfaces for Accelerating Big Data Applications Authors: Zaid Al-Ars, Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel and Joost Hoozemans, TU Delft, NL 1730 Elsa: Eigenvalue based hybrid linear system abstraction: Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata Authors: Ahmad Tarraf and Lars Hedrich, University of Frankfurt, DE 1730 SRSN: Secure Reconfigurable Test Network Authors: Vincent Reynaud¹, Emanuele Valea², Paolo Maistri¹, Regis Leveugle¹, Marie-Lise Flottes², Sophie Dupuis², Bruno Rouzeyre² and Giorgio Di Natale^{1 1}TIMA Laboratory, FR; ²LIRMM, FR 1730 Lagarto: First Silicon RISC-V Academic Processor Developed in Spain Authors: Guillem Cabo Pitarch¹, Cristobal Ramirez Lazo¹, Julian Pavon Rivera¹, Vatistas Kostalabros¹, Carlos Rojas Morales¹, Miquel Moreto¹, Jaume Abella¹, Francisco J. Cazorla¹, Adrian Cristal¹, Roger Figueras¹, Alberto Gonzalez¹, Carles Hernandez¹, Cesar Hernandez², Neiel Leyva², Joan Marimon¹, Ricardo Martinez³, Jonnatan Mendoza¹, Francesc Moll⁴, Marco Antonio Ramirez², Carlos Rojas¹, Antonio Rubio⁴, Abraham Ruiz¹, Nehir Sonmez¹, Lluis Teres³, Osman Unsal⁵, Mateo Valero¹, Ivan Vargas¹ and Luis Villa^{2 1}BSC / UPC, ES; ²CIC-IPN, MX; ³IMB-CNM (CSIC), ES; ⁴UPC, ES; ⁵BSC, ES 1730 LeaRnV: LeaRnV: a RISC-V based Embedded System Design Framework for Education and Research Development Authors: Noureddine Ait Said and Mounir Benabdenbi, TIMA Laboratory, FR 1730 CSI-REPUTE: A Low Power Embedded Device Clustering Approach to Genome Read Mapping Authors: Tousif Rahman¹, Sidharth Maheshwari¹, Rishad Shafik¹, Ian Wilson¹, Alex Yakovlev¹ and Amit Acharyya^{2 1}Newcastle University, GB; ²IIT Hyderabad, IN 1730 Brook SC: High-level Certification-friendly Programming for GPU-powered Safety Critical Systems Authors: Marc Benito, Matina Maria Trompouki and Leonidas Kosmidis, BSC / UPC, ES 1730 Wallance: an Alternative to Blockchain for IoT Authors: Loic Dalmasso, Florent Bruguier, Pascal Benoit and Achraf Lamlih, Université de Montpellier, FR 1730 RUMORE: A Framework for RUntime MOnitoring and TRacE Analysis for Component-based Embedded Systems Design Flow Authors: Vittoriano Muttillo¹, Luigi Pomante¹, Giacomo Valente¹, Hector Posadas², Javier Merino² and Eugenio Villar^{2 1}University of L'Aquila, IT; ²University of Cantabria, ES 1730 Distributing Time-Sensitive Applications on Edge Computing Environments Authors: Eudald Sabaté Creixell¹, Unai Perez Mendizabal¹, Elli Kartsakli², Maria A. Serrano Gracia³ and Eduardo Quiñones Moreno^{3 1}BSC / UPC, ES; ²BSC, GR; ³BSC, ES UB05 Session 5 Booth 11, Exhibition Area 1000 - 1200 1000 TaPaSCo: The Open-Source Task-Parallel System Composer Framework Authors: Carsten Heinz, Lukas Sommer, Lukas Weber, Jaco Hofmann and Andreas Koch, TU Darmstadt, DE 1000 Elsa: Eigenvalue based hybrid linear system abstraction: Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata Authors: Ahmad Tarraf and Lars Hedrich, University of Frankfurt, DE 1000 Euclid-NIR GPU: An On-board Processing GPU-accelerated Space Case Study Demonstrator Authors: Ivan Rodriguez and Leonidas Kosmidis, BSC / UPC, ES 1000 BCFELEAM: BackFlow: Backward Edge Control Flow Enforcement for Low End ARM Real-Time Systems Authors: Bresch Cyril¹, David Héy¹, Roman Lysecky² and Stephanie Chollet^{1 1}LCIS, FR; ²University of Arizona, US 1000 UWB AckAtck: Hijacking Devices in UWB Indoor Positioning Systems Authors: Baptiste Pestourie, Vincent Beroulle and Nicolas Fourty, Université Grenoble Alpes, FR 1000 Design Automation for Extended Burst-Mode Automata in Workcraft Authors: Alex Chan, Alex Yakovlev, Danil Sokolov and Victor Khomenko, Newcastle University, GB 1000 At-speed DfT Architecture for Bundled-data Circuits Authors: Ricardo Aquino Guazzelli and Laurent Fesquet, Université Grenoble Alpes, FR 1000 CATANIS: CAD Tool for Automatic Network Synthesis Authors: Davide Quaglia, Enrico Fraccaroli, Filippo Nevi and Sohail Mushtaq, Università di Verona, IT 1000 Parallel Algorithm for CNN Inference and its Automatic Synthesis Authors: Takashi Matsumoto, Yukio Miyasaka, Xinpei Zhang and Masahiro Fujita, University of Tokyo, JP 1000 FU: Low Power and Accuracy Configurable Approximate Arithmetic Units Authors: Tomoaki Ukezono and Toshinori Sato, Fukuoka University, JP UB06 Session 6 Booth 11, Exhibition Area 1200 - 1400 1200 A Digital Microfluidics Bio-Computing Platform Authors: Georgi Tanev, Luca Pezzarossa, Winnie Edith Svendsen and Jan Madsen, TU Denmark, DK 1200 Elsa: Eigenvalue based hybrid linear system abstraction: Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata Authors: Ahmad Tarraf and Lars Hedrich, University of Frankfurt, DE 1200 Virtual Platforms for Complex Software Stacks Authors: Lukas Jünger and Rainer Leupers, RWTH Aachen University, DE 1200 SystemC-CT/DE: A Simulator with Fast and Accurate Continuous Time and Discrete Events Interactions on Top of SystemC. Authors: Breytner Joseph Fernandez-Mesa, Liliana Andrade and Frédéric Pétrot, Université Grenoble Alpes / CNRS / TIMA Laboratory, FR 1200 SRSN: Secure Reconfigurable Test Network Authors: Vincent Reynaud¹, Emanuele Valea², Paolo Maistri¹, Regis Leveugle¹, Marie-Lise Flottes², Sophie Dupuis², Bruno Rouzeyre² and Giorgio Di Natale^{1 1}TIMA Laboratory, FR; ²LIRMM, FR 1200 Generating Asynchronous Circuits from Catapult Authors: Yoan Decoudu¹, Jean Simatic², Katell Morin-Allory³ and Laurent Fesquet^{3 1}University Grenoble Alpes, FR; ²HawAI.Tech, FR; ³Université Grenoble Alpes, FR 1200 LeaRnV: LeaRnV: a RISC-V based Embedded System Design Framework for Education and Research Development Authors: Noureddine Ait Said and Mounir Benabdenbi, TIMA Laboratory, FR 1200 Wallance: an Alternative to Blockchain for IoT Authors: Loic Dalmasso, Florent Bruguier, Pascal Benoit and Achraf Lamlih, Université de Montpellier, FR 1200 JOINTER: JOining flexIble moNitors wiTh hEterogeneous architectuRes Authors: Giacomo Valente¹, Tiziana Fanni², Carlo Sau³, Claudio Rubattu², Francesca Palumbo² and Luigi Pomante^{1 1}Università degli Studi dell'Aquila, IT; ²Università degli Studi di Sassari, IT; ³Università degli Studi di Cagliari, IT UB07 Session 7 Booth 11, Exhibition Area 1400 - 1600 1400 DL PUF ENAU: Deep Learning Based Physically Unclonable Function Enrollment and Authenntication Authors: Amir Alipour¹, David Hely², Vincent Beroulle² and Giorgio Di Natale^{3 1}Grenoble INP / LCIS, FR; ²Grenoble INP, FR; ³CNRS / Grenoble INP / TIMA, FR 1400 BCFELEAM: BackFlow: Backward Edge Control Flow Enforcement for Low End ARM Real-Time Systems Authors: Bresch Cyril¹, David Héy¹, Roman Lysecky² and Stephanie Chollet^{1 1}LCIS, FR; ²University of Arizona, US 1400 A Binary Translation Framework for Automated Hardware Generation Authors: Nuno Paulino and João Canas Ferreira, INESC TEC / University of Porto, PT 1400 RETINE: A programmable 3D stacked vision chip enabling low latency image analysis Authors: Stéphane Chevobbe¹, Maria Lepecq¹ and Laurent Millet^{2 1}CEA LIST, FR; ²CEA-Leti, FR 1400 UWB AckAtck: Hijacking Devices in UWB Indoor Positioning Systems Authors: Baptiste Pestourie, Vincent Beroulle and Nicolas Fourty, Université Grenoble Alpes, FR 1400 Design Automation for Extended Burst-Mode Automata in Workcraft Authors: Alex Chan, Alex Yakovlev, Danil Sokolov and Victor Khomenko, Newcastle University, GB 1400 DeepSense-FPGA: FPGA Acceleration of a Multimodal Neural Network Authors: Mehdi Trabelsi Ajili and Yuko Hara-Azumi, Tokyo Institute of Technology, JP 1400 SubRISC+: Implementation and Evaluation of an Embedded Processor for Lightweight IoT eHealth Authors: Mingyu Yang and Yuko Hara-Azumi, Tokyo Institute of Technology, JP 1400 PA-HLS: High-level Annotation of Routing Congestion for Xilinx Vivado HLS Designs Authors: Osama Bin Tariq¹, Junnan Shan¹, Luciano Lavagno¹, Georgios Floros², Mihai Teodor Lazarescu¹, Christos Sotiriou² and Mario Roberto Casu^{1 1}Politecnico di Torino, IT; ²University of Thessaly, GR 1400 MDD-COP: A Preliminary Tool for Model-Driven Development extended with layer diagram for Context-Oriented Programming Authors: Harumi Watanabe¹, Chinatsu Yamamoto¹, Takeshi Ohkawa¹, Mikiko Sato¹, Nobuhiko Ogura² and Mana Tabei^{1 1}Tokai University, JP; ²Tokyo City University, JP UB08 Session 8 Booth 11, Exhibition Area 1600 - 1800 1600 Lagarto: First Silicon RISC-V Academic Processor Developed in Spain Authors: Guillem Cabo Pitarch¹, Cristobal Ramirez Lazo¹, Julian Pavon Rivera¹, Vatistas Kostalabros¹, Carlos Rojas Morales¹, Miquel Moreto¹, Jaume Abella¹, Francisco J. Cazorla¹, Adrian Cristal¹, Roger Figueras¹, Alberto Gonzalez¹, Carles Hernandez¹, Cesar Hernandez², Neiel Leyva², Joan Marimon¹, Ricardo Martinez³, Jonnatan Mendoza¹, Francesc Moll⁴, Marco Antonio Ramirez², Carlos Rojas¹, Antonio Rubio⁴, Abraham Ruiz¹, Nehir Sonmez¹, Lluis Teres³, Osman Unsal⁵, Mateo Valero¹, Ivan Vargas¹ and Luis Villa^{2 1}BSC / UPC, ES; ²CIC-IPN, MX; ³IMB-CNM (CSIC), ES; ⁴UPC, ES; ⁵BSC, ES 1600 A Digital Microfluidics Bio-Computing Platform Authors: Georgi Tanev, Luca Pezzarossa, Winnie Edith Svendsen and Jan Madsen, TU Denmark, DK 1600 Distributing Time-Sensitive Applications on Edge Computing Environments Authors: Eudald Sabaté Creixell¹, Unai Perez Mendizabal¹, Elli Kartsakli², Maria A. Serrano Gracia³ and Eduardo Quiñones Moreno^{3 1}BSC / UPC, ES; ²BSC, GR; ³BSC, ES 1600 LeaRnV: LeaRnV: a RISC-V based Embedded System Design Framework for Education and Research Development Authors: Noureddine Ait Said and Mounir Benabdenbi, TIMA Laboratory, FR 1600 SRSN: Secure Reconfigurable Test Network Authors: Vincent Reynaud¹, Emanuele Valea², Paolo Maistri¹, Regis Leveugle¹, Marie-Lise Flottes², Sophie Dupuis², Bruno Rouzeyre² and Giorgio Di Natale^{1 1}TIMA Laboratory, FR; ²LIRMM, FR 1600 RETINE: A programmable 3D stacked vision chip enabling low latency image analysis Authors: Stéphane Chevobbe¹, Maria Lepecq¹ and Laurent Millet^{2 1}CEA LIST, FR; ²CEA-Leti, FR 1600 FasThermSim: Fast and Accurate Thermal Simulations from Chiplets to System Authors: Yu-Min Lee, Chi-Wen Pan, Li-Rui Ho and Hong-Wen Chiou, National Chiao Tung University, TW 1600 PA-HLS: High-level Annotation of Routing Congestion for Xilinx Vivado HLS Designs Authors: Osama Bin Tariq¹, Junnan Shan¹, Luciano Lavagno¹, Georgios Floros², Mihai Teodor Lazarescu¹, Christos Sotiriou² and Mario Roberto Casu^{1 1}Politecnico di Torino, IT; ²University of Thessaly, GR 1600 MDD-COP: A Preliminary Tool for Model-Driven Development extended with layer diagram for Context-Oriented Programming Authors: Harumi Watanabe¹, Chinatsu Yamamoto¹, Takeshi Ohkawa¹, Mikiko Sato¹, Nobuhiko Ogura² and Mana Tabei^{1 1}Tokai University, JP; ²Tokyo City University, JP UB09 Session 9 Booth 11, Exhibition Area 1000 - 1200 1000 TaPaSCo: The Open-Source Task-Parallel System Composer Framework Authors: Carsten Heinz, Lukas Sommer, Lukas Weber, Jaco Hofmann and Andreas Koch, TU Darmstadt, DE 1000 RESCUED: A Rescue Demonstrator for Interdependent Aspects of Reliability, Security and Quality Towards a Complete EDA Flow Authors: Nevin George¹, Guilherme Cardoso Medeiros², Junchao Chen³, Josie Esteban Rodriguez Condia⁴, Thomas Lange⁵, Aleksa Damljanovic⁴, Raphael Segabinazzi Ferreira¹, Aneesh Balakrishnan⁵, Xinhui Lai⁶, Shayesteh Masoumian⁷, Dmytro Petryk³, Troya Cagil Koylu², Felipe Augusto da Silva⁸, Ahmet Cagri Bagbaba⁸, Cemil Cem Gürsoy⁶, Said Hamdioui², Mottaqiallah Taouil², Milos Krstic³, Peter Langendoerfer³, Zoya Dyka³, Marcelo Brandalero¹, Michael Hübner¹, Jörg Nolte¹, Heinrich Theodor Vierhaus¹, Matteo Sonza Reorda⁴, Giovanni Squillero⁴, Luca Sterpone⁴, Jaan Raik⁶, Dan Alexandrescu⁵, Maximilien Glorieux⁵, Georgios Selimis⁷, Geert-Jan Schrijen⁷, Anton Klotz⁸, Christian Sauer⁸ and Maksim Jenihhin^{6 1}Brandenburg University of Technology Cottbus-Senftenberg, DE; ²TU Delft, NL; ³Leibniz-Institut für innovative Mikroelektronik, DE; ⁴Politecnico di Torino, IT; ⁵IROC Technologies, FR; ⁶Tallinn University of Technology, EE; ⁷Intrinsic ID, NL; ⁸Cadence Design Systems GmbH, DE 1000 PAFUSI: Particle Filter Fusion ASIC for Indoor Positioning Authors: Christian Schott, Marko Rößler, Daniel Froß, Marcel Putsche and Ulrich Heinkel, TU Chemnitz, DE 1000 Skeletor: An Open Source EDA Tool Flow from Hierarchy Specification to HDL Development Authors: Ivan Rodriguez, Guillem Cabo, Javier Barrera, Jeremy Giesen, Alvaro Jover and Leonidas Kosmidis, BSC / UPC, ES 1000 SystemC-CT/DE: A Simulator with Fast and Accurate Continuous Time and Discrete Events Interactions on Top of SystemC. Authors: Breytner Joseph Fernandez-Mesa, Liliana Andrade and Frédéric Pétrot, Université Grenoble Alpes / CNRS / TIMA Laboratory, FR 1000 Parallel Algorithm for CNN Inference and its Automatic Synthesis Authors: Takashi Matsumoto, Yukio Miyasaka, Xinpei Zhang and Masahiro Fujita, University of Tokyo, JP 1000 EEC: Energy Efficient Computing via Dynamic Voltage Scaling and In-Network Optical Processing Authors: Ryosuke Matsuo¹, Jun Shiomi¹, Yutaka Masuda² and Tohru Ishihara^{2 1}Kyoto University, JP; ²Nagoya University, JP 1000 SubRISC+: Implementation and Evaluation of an Embedded Processor for Lightweight IoT eHealth Authors: Mingyu Yang and Yuko Hara-Azumi, Tokyo Institute of Technology, JP 1000 PA-HLS: High-level Annotation of Routing Congestion for Xilinx Vivado HLS Designs Authors: Osama Bin Tariq¹, Junnan Shan¹, Luciano Lavagno¹, Georgios Floros², Mihai Teodor Lazarescu¹, Christos Sotiriou² and Mario Roberto Casu^{1 1}Politecnico di Torino, IT; ²University of Thessaly, GR 1000 FU: Low Power and Accuracy Configurable Approximate Arithmetic Units Authors: Tomoaki Ukezono and Toshinori Sato, Fukuoka University, JP UB10 Session 10 Booth 11, Exhibition Area 1200 - 1430 1200 TaPaSCo: The Open-Source Task-Parallel System Composer Framework Authors: Carsten Heinz, Lukas Sommer, Lukas Weber, Jaco Hofmann and Andreas Koch, TU Darmstadt, DE 1200 RESCUED: A Rescue Demonstrator for Interdependent Aspects of Reliability, Security and Quality Towards a Complete EDA Flow Authors: Nevin George¹, Guilherme Cardoso Medeiros², Junchao Chen³, Josie Esteban Rodriguez Condia⁴, Thomas Lange⁵, Aleksa Damljanovic⁴, Raphael Segabinazzi Ferreira¹, Aneesh Balakrishnan⁵, Xinhui Lai⁶, Shayesteh Masoumian⁷, Dmytro Petryk³, Troya Cagil Koylu², Felipe Augusto da Silva⁸, Ahmet Cagri Bagbaba⁸, Cemil Cem Gürsoy⁶, Said Hamdioui², Mottaqiallah Taouil², Milos Krstic³, Peter Langendoerfer³, Zoya Dyka³, Marcelo Brandalero¹, Michael Hübner¹, Jörg Nolte¹, Heinrich Theodor Vierhaus¹, Matteo Sonza Reorda⁴, Giovanni Squillero⁴, Luca Sterpone⁴, Jaan Raik⁶, Dan Alexandrescu⁵, Maximilien Glorieux⁵, Georgios Selimis⁷, Geert-Jan Schrijen⁷, Anton Klotz⁸, Christian Sauer⁸ and Maksim Jenihhin^{6 1}Brandenburg University of Technology Cottbus-Senftenberg, DE; ²TU Delft, NL; ³Leibniz-Institut für innovative Mikroelektronik, DE; ⁴Politecnico di Torino, IT; ⁵IROC Technologies, FR; ⁶Tallinn University of Technology, EE; ⁷Intrinsic ID, NL; ⁸Cadence Design Systems GmbH, DE 1200 RETINE: A programmable 3D stacked vision chip enabling low latency image analysis Authors: Stéphane Chevobbe¹, Maria Lepecq¹ and Laurent Millet^{2 1}CEA LIST, FR; ²CEA-Leti, FR 1200 DL PUF ENAU: Deep Learning Based Physically Unclonable Function Enrollment and Authenntication Authors: Amir Alipour¹, David Hely², Vincent Beroulle² and Giorgio Di Natale^{3 1}Grenoble INP / LCIS, FR; ²Grenoble INP, FR; ³CNRS / Grenoble INP / TIMA, FR 1200 Lagarto: First Silicon RISC-V Academic Processor Developed in Spain Authors: Guillem Cabo Pitarch¹, Cristobal Ramirez Lazo¹, Julian Pavon Rivera¹, Vatistas Kostalabros¹, Carlos Rojas Morales¹, Miquel Moreto¹, Jaume Abella¹, Francisco J. Cazorla¹, Adrian Cristal¹, Roger Figueras¹, Alberto Gonzalez¹, Carles Hernandez¹, Cesar Hernandez², Neiel Leyva², Joan Marimon¹, Ricardo Martinez³, Jonnatan Mendoza¹, Francesc Moll⁴, Marco Antonio Ramirez², Carlos Rojas¹, Antonio Rubio⁴, Abraham Ruiz¹, Nehir Sonmez¹, Lluis Teres³, Osman Unsal⁵, Mateo Valero¹, Ivan Vargas¹ and Luis Villa^{2 1}BSC / UPC, ES; ²CIC-IPN, MX; ³IMB-CNM (CSIC), ES; ⁴UPC, ES; ⁵BSC, ES 1200 SRSN: Secure Reconfigurable Test Network Authors: Vincent Reynaud¹, Emanuele Valea², Paolo Maistri¹, Regis Leveugle¹, Marie-Lise Flottes², Sophie Dupuis², Bruno Rouzeyre² and Giorgio Di Natale^{1 1}TIMA Laboratory, FR; ²LIRMM, FR 1200 DeepSense-FPGA: FPGA Acceleration of a Multimodal Neural Network Authors: Mehdi Trabelsi Ajili and Yuko Hara-Azumi, Tokyo Institute of Technology, JP 1200 Generating Asynchronous Circuits from Catapult Authors: Yoan Decoudu¹, Jean Simatic², Katell Morin-Allory³ and Laurent Fesquet^{3 1}University Grenoble Alpes, FR; ²HawAI.Tech, FR; ³Université Grenoble Alpes, FR 1200 PA-HLS: High-level Annotation of Routing Congestion for Xilinx Vivado HLS Designs Authors: Osama Bin Tariq¹, Junnan Shan¹, Luciano Lavagno¹, Georgios Floros², Mihai Teodor Lazarescu¹, Christos Sotiriou² and Mario Roberto Casu^{1 1}Politecnico di Torino, IT; ²University of Thessaly, GR 1200 ATECES: Automated testing the energy consumption of embedded systems Author: Eduard Enoiu, Mälardalen University, SE UB11 Session 11 Booth 11, Exhibition Area 1430 - 1630 1430 ATECES: Automated testing the energy consumption of embedded systems Author: Eduard Enoiu, Mälardalen University, SE 1430 Brook SC: High-level Certification-friendly Programming for GPU-powered Safety Critical Systems Authors: Marc Benito, Matina Maria Trompouki and Leonidas Kosmidis, BSC / UPC, ES 1430 Distributing Time-Sensitive Applications on Edge Computing Environments Authors: Eudald Sabaté Creixell¹, Unai Perez Mendizabal¹, Elli Kartsakli², Maria A. Serrano Gracia³ and Eduardo Quiñones Moreno^{3 1}BSC / UPC, ES; ²BSC, GR; ³BSC, ES 1430 DL PUF ENAU: Deep Learning Based Physically Unclonable Function Enrollment and Authenntication Authors: Amir Alipour¹, David Hely², Vincent Beroulle² and Giorgio Di Natale^{3 1}Grenoble INP / LCIS, FR; ²Grenoble INP, FR; ³CNRS / Grenoble INP / TIMA, FR 1430 Lagarto: First Silicon RISC-V Academic Processor Developed in Spain Authors: Guillem Cabo Pitarch¹, Cristobal Ramirez Lazo¹, Julian Pavon Rivera¹, Vatistas Kostalabros¹, Carlos Rojas Morales¹, Miquel Moreto¹, Jaume Abella¹, Francisco J. Cazorla¹, Adrian Cristal¹, Roger Figueras¹, Alberto Gonzalez¹, Carles Hernandez¹, Cesar Hernandez², Neiel Leyva², Joan Marimon¹, Ricardo Martinez³, Jonnatan Mendoza¹, Francesc Moll⁴, Marco Antonio Ramirez², Carlos Rojas¹, Antonio Rubio⁴, Abraham Ruiz¹, Nehir Sonmez¹, Lluis Teres³, Osman Unsal⁵, Mateo Valero¹, Ivan Vargas¹ and Luis Villa^{2 1}BSC / UPC, ES; ²CIC-IPN, MX; ³IMB-CNM (CSIC), ES; ⁴UPC, ES; ⁵BSC, ES 1430 SRSN: Secure Reconfigurable Test Network Authors: Vincent Reynaud¹, Emanuele Valea², Paolo Maistri¹, Regis Leveugle¹, Marie-Lise Flottes², Sophie Dupuis², Bruno Rouzeyre² and Giorgio Di Natale^{1 1}TIMA Laboratory, FR; ²LIRMM, FR 1430 LeaRnV: LeaRnV: a RISC-V based Embedded System Design Framework for Education and Research Development Authors: Noureddine Ait Said and Mounir Benabdenbi, TIMA Laboratory, FR 1430 Generating Asynchronous Circuits from Catapult Authors: Yoan Decoudu¹, Jean Simatic², Katell Morin-Allory³ and Laurent Fesquet^{3 1}University Grenoble Alpes, FR; ²HawAI.Tech, FR; ³Université Grenoble Alpes, FR 1430 RUMORE: A Framework for RUntime MOnitoring and TRacE Analysis for Component-based Embedded Systems Design Flow Authors: Vittoriano Muttillo¹, Luigi Pomante¹, Giacomo Valente¹, Hector Posadas², Javier Merino² and Eugenio Villar^{2 1}University of L'Aquila, IT; ²University of Cantabria, ES