FM01.1 PhD Forum 1800 - 2100 1.1 Opening Session: Plenary, Awards Ceremony & Keynote Addresses Amphithéâtre Dauphine 0830 - 1030 Chair:Giorgio Di Natale, DATE 2020 General Chair, FR Co-Chair:Cristiana Bolchini, DATE 2020 Programme Chair, IT 0815 Welcome Addresses Speakers: Giorgio Di Natale¹ and Cristiana Bolchini² ¹TIMA, FR; ²Politecnico di Milano, IT 0825 Presentation of Awards 0915 Plenary Keynote: The Industrial IoT microelectronics revolution Speaker: Philippe Magarshack, STMicroelectronics, FR 0955 Plenary Keynote: Open Parallel Ultra-Low Power Platforms for Extreme Edge AI Speaker: Luca Benini, ETH Zurich, CH 2.1 Executive Session: Memories for Emerging Applications Amphithéâtre Jean Prouve 1130 - 1300 Chair:Pierre-Emmanuel Gaillardon, University of Utah, US Co-Chair:Kvatinsky Shahar, Technion, IL Memories play a prime role in virtually every modern computing systems. While memory technology has been able to follow the aggressive trend of scaling and keep up with the most stringent demands, there exists new applications for which traditional memories struggle to deliver viable solutions. In this context, and more than ever, novel memory technologies are required. Identifying a close match between a killer application and a supporting emerging memory technology will ensure unprecedented capabilities and open durable new horizons for computing systems. In this executive session, we will explore specific cases where novel memories (OxRAM and SOT MRAM in particular) are opening such novel applications unachievable with standard memories. 1130 Resistive RAM and its Dense 3D Integration for the N3XT 1,000X Author: Subhasish Mitra, Stanford University, US 1200 Emerging Memories for Von Neumann and for Neuromorphic Computing Author: Jamil Kawa, Synopsys, US 1230 ReRAM Technology for next generation AI and cost-effective embedded memory Author: Amir Regev, Weebit Nano, AU 2.2 Hardware-assisted Secure Systems Chamrousse 1130 - 1300 Chair:Prabhat Mishra, University of Florida, US Co-Chair:Kavun Elif Bilge, University of Sheffield, GB This session covers state-of-the-art hardware-assisted techniques for secure systems such as random number generators, PUFs, and logic locking & obfuscation. In addition, novel detection methods for hardware Trojans are presented. 1130 Backtracking Search for Optimal Parameters of a PLL-based True Random Number Generator Speaker: Brice Colombier, Université de Lyon, FR Authors: Brice Colombier¹, Nathalie Bochard¹, Florent BERNARD² and Lilian Bossuet¹ ¹Université de Lyon, FR; ²Laboratory Hubert Curien, University of Lyon, UJM Saint-Etienne, FR 1200 Long-term Continuous Assessment of SRAM PUF and Source of Random Numbers Speaker: Rui Wang, Intrinsic-ID, NL Authors: Rui Wang, Georgios Selimis, Roel Maes and Sven Goossens, Intrinsic-ID, NL 1215 Rescuing Logic Encryption in Post-SAT Era by Locking & Obfuscation Speaker: Hai Zhou, Northwestern University, US Authors: Amin Rezaei, Yuanqi Shen and Hai Zhou, Northwestern University, US 1230 Selective Concolic Testing for Hardware Trojan Detection in Behavioral SystemC Designs Speaker: Bin Lin, Portland State University, US Authors: Bin Lin¹, Jinchao Chen² and Fei Xie¹ ¹Portland State University, US; ²Northwestern Polytechnical University, CN 1245 Test Pattern Superposition to Detect Hardware Trojans Speaker: Alex Orailoglu, University of California, San Diego, US Authors: Chris Nigh and Alex Orailoglu, University of California, San Diego, US IPs IP1-1 2.3 Fueling the future of computing: 3D, TFT, or disruptive memories? Autrans 1130 - 1300 Chair:Yvain Thonnart, CEA-Leti, FR Co-Chair:Marco Vacca, Politecnico di Torino, IT In the post-CMOS era, the future of computing relies more and more on emerging technologies, like resistive memories, TFT and 3D integration or their combination, to continue performance improvements: from a novel accelerating solution for deep neural networks with ferroelectric transistor technology, to a physical design methodology for face-to-face 3D ICs to enable commercial-quality IC layouts. Furthermore, the monolithic 3D advantage obtained combining TFT and RRAM technology is quantified using a novel open-source CAD flow. 1130 Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks Speaker: Sandeep Krishna Thirumala, Purdue University, US Authors: Sandeep Krishna Thirumala, Shubham Jain, Sumeet Gupta and Anand Raghunathan, Purdue University, US 1200 Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs Speaker: Lennart Bamberg, University of Bremen, DE / GrAi Matter Labs, NL Authors: Lennart Bamberg¹, Lingjun Zhu², Sai Pentapati², Da Eun Shim², Alberto Garcia-Ortiz³ and Sung Kyu Lim² ¹GrAi Matter Labs, NL; ²Georgia Tech, US; ³University of Bremen, DE 1230 Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAM Speaker: Abdallah Felfel, Zewail City of Science and Technology, EG Authors: Abdallah M Felfel¹, Kamalika Datta¹, Arko Dutt¹, Hasita Veluri², Ahmed Zaky¹, Aaron Thean² and Mohamed M Sabry Aly¹ ¹Nanyang Technological University, SG; ²National University of Singapore, SG 1245 Organic-Flow: An Open-Source Organic Standard Cell Library and Process Development Kit Speaker: Ting-Jung Chang, Princeton University, US Authors: Ting-Jung Chang, Zhuozhi Yao, Barry P. Rand and David Wentzlaff, Princeton University, US IPs IP1-2, IP1-3 2.4 Challenges in Analog Design Automation & Security Stendhal 1130 - 1300 Chair:Manuel Barragan, TIMA, FR Co-Chair:Haralampos Stratigopoulos, LIP6, FR Producing reliable and secure analog circuits is a challenging task. This session addresses novel and systematic approaches to analog security, based on key sequencing, and analog design, from automatic netlist annotation to Bayesian modeling optimization. 1130 GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits Speaker: Kishor Kunal, University of Minnesota, IN Authors: Kishor Kunal¹, Tonmoy Dhar², Meghna Madhusudan², Jitesh Poojary¹, Arvind Sharma¹, Wenbin Xu³, Steven Burns⁴, Jiang Hu³, Ramesh Harjani¹ and Sachin S. Sapatnekar¹ ¹University of Minnesota, US; ²University of Minnesota Twin Cities, US; ³Texas A&M University, US; ⁴Intel Corporation, US 1200 Securing Programmable Analog ICs Against Piracy Speaker: Mohamed Elshamy, Sorbonne Université, CNRS, LIP6, FR Authors: Mohamed Elshamy, Alhassan Sayed, Marie-Minerve Louerat, Amine Rhouni, Hassan Aboushady and Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR 1230 An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling Speaker: Biao He, Fudan University, CN Authors: Biao He¹, Shuhan Zhang¹, Fan Yang², Changhao Yan¹, Dian Zhou³ and Xuan Zeng¹ ¹Fudan university, CN; ²Fudan University, CN; ³University of Texas at Dallas, US IPs IP1-4, IP1-5, IP1-6 2.5 Pruning Techniques for Embedded Neural Networks Bayard 1130 - 1300 Chair:Marian Verhelst, KU Leuven, BE Co-Chair:Dirk Ziegenbein, Robert Bosch GmbH, DE Network pruning has been applied successfully to reduce the computational and memory footprint of neural network processing. This session presents three innovations to better exploit pruning in embedded processing architectures. The solutions presented extend the sparsity concept to the bit level with an enhanced bit-level pruning technique based on CSD representations, introduce a novel group-level pruning technique, demonstrating an improved trade-off between hardware-execution cost and accuracy loss, and explore a sparsity-aware cache architecture to reduce cache miss rate and execution time. 1130 Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks Speaker: Byungmin Ahn, Seoul National University, KR Authors: Byungmin Ahn and Taewhan Kim, Seoul National University, KR 1200 Flexible Group-Level Pruning of Deep Neural Networks for On-Device Machine Learning Speaker: Dongkun Shin, Sungkyunkwan University, KR Authors: Kwangbae Lee, Hoseung Kim, Hayun Lee and Dongkun Shin, Sungkyunkwan University, KR 1230 Sparsity-Aware Caches to Accelerate Deep Neural Networks Speaker: Vinod Ganesan, IIT Madras, IN Authors: Vinod Ganesan¹, Sanchari Sen², Pratyush Kumar¹, Neel Gala¹, Kamakoti Veezhinatha¹ and Anand Raghunathan² ¹IIT Madras, IN; ²Purdue University, US IPs IP1-7 2.6 Improving reliability and fault tolerance of advanced memories Lesdiguières 1130 - 1300 Chair:Mounir Benabdenbi, TIMA Laboratory, FR Co-Chair:Said Hamdioui, TU Delft, NL This session discusses reliability issues for different memory technologies; addressing fault tolerance of memristors, how to reduce simulations with importance sampling and advance metrics as measure for the reliability of NAND flash memories. 1130 On Improving Fault Tolerance of Memristor Crossbar Based Neural Network Designs by Target Sparsifying Speaker: Yu Wang, North China Electric Power University, CN Authors: Song Jin¹, Songwei Pei² and Yu Wang¹ ¹North China Electric Power University, CN; ²School of Computer Science, Beijing University of Posts and Telecommunications, CN 1200 An Efficient Yield Analysis of SRAM Using Scaled-Sigma Adaptive Importance Sampling Speaker: Liang Pang, Southeast University, CN Authors: Liang Pang¹, Mengyun Yao² and Yifan Chai¹ ¹School of Electronic Science & Engineering, Southeast University, CN; ²School of Microelectronics, Southeast University, CN 1230 Fast and Accurate High-Sigma Failure Rate Estimation through Extended Bayesian Optimized Importance Sampling Speaker: Michael Hefenbrock, Karlsruhe Institute of Technology, DE Authors: Michael Hefenbrock, Dennis Weller, Michael Beigl and Mehdi Tahoori, Karlsruhe Institute of Technology, DE 1245 Valid Window: A New Metric to Measure the Reliability of NAND Flash Memory Speaker: Min Ye, City University of Hong Kong, HK Authors: Min Ye¹, Qiao Li¹, Jianqiang Nie², Tei-Wei Kuo¹ and Chun Jason Xue¹ ¹City University of Hong Kong, HK; ²YEESTOR Microelectronics Co., Ltd, CN IPs IP1-8, IP1-9 2.7 Optimizing emerging applications for power-efficient computing Berlioz 1130 - 1300 Chair:Theocharis Theocharides, University of Cyprus, CY Co-Chair:Shafique Muhammad, TU Wien, AT This session focuses on emerging applications for power-efficient computing, such as bioinformatics and few-shot learning. Methods such as Hyperdimensional computing or computing in memory are applied to process DNA pattern matching or to perform few-shot learning in a more power-efficient way. 1130 GenieHD: Efficient DNA Pattern Matching Accelerator Using Hyperdimensional Computing Speaker: Mohsen Imani, University of California, San Diego, US Authors: Yeseong Kim, Mohsen Imani, Niema Moshiri and Tajana Rosing, University of California, San Diego, US 1200 REPUTE: An OpenCL based Read Mapping Tool for Embedded Genomics Speaker: Sidharth Maheshwari, Newcastle University, GB Authors: Sidharth Maheshwari¹, Rishad Shafik¹, Alex Yakovlev¹, Ian Wilson¹ and Amit Acharyya² ¹Newcastle University, GB; ²IIT Hyderabad, IN 1230 A Fast and Energy Efficient Computing-in-Memory Architecture for Few-Shot Learning Applications Speaker: Dayane Reis, University of Notre Dame, US Authors: Dayane Reis, Ann Franchesca Laguna, Michael Niemier and X. Sharon Hu, University of Notre Dame, US 3.0 LUNCHTIME KEYNOTE SESSION Amphithéâtre Jean Prouve 1350 - 1420 Chair:Marco Casale-Rossi, Synopsys, IT Co-Chair:Giovanni De Micheli, EPFL, CH 1350 Neuromorphic Computing: Past, Present, and Future Author: Catherine Schuman, Oak Ridge National Laboratory, US 3.1 Special Session: Architectures for Emerging Technologies Amphithéâtre Jean Prouve 1430 - 1600 Chair:Pierre-Emmanuel Gaillardon, University of Utah, US Co-Chair:Michael Niemier, University of Notre Dame, US The past five decades have witnessed transformations happening at an ever-growing pace thanks to the sustained increase of capabilities of electronics systems. We are now at the dawn of a new revolution where emerging technologies, understand beyond silicon complementary metal oxide semiconductors, are going to further revolutionize the way we design electronics. In this hot topic session, we intend to elaborate on the architectural opportunities and challenges brought by non-standard semiconductor technologies. In addition to provide new perspectives to the DATE community beyond the currently hot novel architectures, such as neuromorphic or in-memory computing, this proposal also serve the purpose of tightening the link between DATE and the EDA community at large with the mission and roles of the IEEE Rebooting Computing Initiative - https://rebootingcomputing.ieee.org. 1430 Cryo-CMOS interfaces for a scalable quantum computer Authors: Edoardo Charbon¹, Andrei Vladimirescu², Fabio Sebastiano³ and Masoud Babaie³ ¹EPFL, CH; ²University of California, Berkeley, US; ³TU Delft, NL 1445 The N3XT 1,000X for the Coming Superstorm of Abundant Data: Carbon Nanotube FETs, Resistive RAM, Monolithic 3D Authors: Gage Hills¹ and Mohamed M. Sabry² ¹Massachusetts Institute of Technology, US; ²Nanyang Technological University, SG 1500 Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic Speaker: Eleonora Testa, EPFL, CH Authors: Eleonora Testa¹, Samantha Lubaba Noor², Odysseas Zografos³, Mathias Soeken¹, Francky Catthoor³, Azad Naeemi² and Giovanni Demicheli¹ ¹EPFL, CH; ²Georgia Tech, US; ³IMEC, BE 1515 Quantum Computer Architecture: Towards Full-Stack Quantum Accelerators Speaker: Koen Bertels, TU Delft, BE Authors: Koen Bertels, Aritra Arkar, T. Hubregtsen, M. Serrao, Abid A. Mouedenne, A. Yadav, A. Krol, Imran Ashraf and Carmen G. Almudever, TU Delft, NL 1530 Utilizing buried power rails and backside PDN to further CMOS scaling below 5nm nodes Authors: Odysseas Zografos, Sudhir Patli, Satadru Sarkar, Bilal Chehab, Doyoung Jang, Rogier Baert, Peter Debacker, Myung-Hee Na and Julien Ryckaert, IMEC, BE 1545 A RRAM-based FPGA for Energy-efficient Edge Computing Authors: Xifan Tang, Ganesh Gore, Patsy Cadareanu, Edouard Giacomin and Pierre-Emmanuel Gaillardon, University of Utah, US 3.2 Accelerating Design Space Exploration Chamrousse 1430 - 1600 Chair:Christian Pilato, Politecnico di Milano, IT Co-Chair:Luca Carloni, Columbia University, US Accelerating Design Space Exploration efficiently is needed to optimize hardware accelerators. At high level, learning techniques can provide ways to either recognize previously synthesized kernels or to model the hidden dependences between synthesis directive costs and performances. At a lower level, speeding up RTL simulations based on data dependencies analysis can speed up one of the most time consuming steps. 1430 Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization Authors: Zi Wang, Jianqi Chen and Benjamin Carrion Schaefer, University of Texas at Dallas, US 1500 Prospector: Synthesizing Efficient Accelerators via Statistical Learning Speaker: Aninda Manocha, Princeton University, US Authors: Atefeh Mehrabi, Aninda Manocha, Benjamin Lee and Daniel Sorin, Duke University, US 1530 Tango: An Optimizing Compiler for Just-In-Time RTL Simulation Speaker: Blaise-Pascal Tine, Georgia Tech, US Authors: Blaise Tine, Sudhakar Yalamanchili and Hyesoon Kim, Georgia Tech, US IPs IP1-10, IP1-11, IP1-12 3.3 EU/ESA projects on Heterogeneous Computing Autrans 1430 - 1600 Chair:Carles Hernandez, UPV, ES Co-Chair:Francisco J. Cazorla, BSC, ES In the scope of this session the presented EU/ESA projects cover topics related to the control electronics and data processing architecture and functionality of the Wide Field Imager, one of two scientific instruments of the next European X-ray observatory ATHENA; task-based programming models to provide a software ecosystem for heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines; and a framework to allow Big Data solutions to dynamically and transparently exploit heterogeneous hardware accelerators. 1430 ESA Athena WFI Onboard Electronics - Distributed Control and Data Processing (work in progress in the project) Speaker: Markus Plattner, Max Planck Institute for extraterrestrial Physics, DE Authors: Markus Plattner¹, Sabine Ott¹, Jintin Tran¹, Christopher Mandla¹, Manfred Steller², Harald Jeszensky², Roland Ottensamer³, Jan-Christoph Tenzer⁴, Thomas Schanz⁴, Samuel Pliego⁴, Konrad Skup⁵, Denis Tcherniak⁶, Chris Thomas⁷, Julian Thornhill⁷ and Sebastian Albrecht¹ ¹Max Planck Institute for extraterrestrial Physics, DE; ²IWF - Space Research Institute, AT; ³TU Wien, AT; ⁴University of Tübingen, DE; ⁵CBK Warsaw, PL; ⁶Technical University of Denmark, DK; ⁷University of Leicester, GB 1500 LEGaTO: Low-Energy, Secure, and ResilientToolset for Heterogeneous Computing Speaker: Valerio Schiavoni, University of Neuchâtel, CH Authors: Behzad Salami¹, Konstantinos Parasyris¹, Adrian Cristal¹, Osman Unsal¹, Xavier Martorell¹, Paul Carpenter¹, Raul De La Cruz¹, Leonardo Bautista¹, Daniel Jimenez¹, Carlos Alvarez¹, Saber Nabavi¹, Sergi Madonar¹, Miquel Pericàs², Pedro Trancoso², Mustafa Abduljabbar², Jing Chen², Pirah Noor Soomro², Madhavan Manivannan², Micha von dem Berge³, Stefan Krupop³, Frank Klawonn⁴, Amani Mihklafi⁴, Sigrun May⁴, Tobias Becker⁵, Georgi Gaydadjiev⁵, Hans Salomonsson⁶, Devdatt Dubhashi⁶, Oron Port⁷, Yoav Etsion⁸, Le Quoc Do⁹, Christof Fetzer⁹, Martin Kaiser¹⁰, Nils Kucza¹⁰, Jens Hagemeyer¹⁰, René Griessl¹⁰, Lennart Tigges¹⁰, Kevin Mika¹⁰, Arne Hüffmeier¹⁰, Marcelo Pasin¹¹, Valerio Schiavoni¹¹, Isabelly Rocha¹¹, Christian Göttel¹¹ and Pascal Felber¹¹ ¹BSC, ES; ²Chalmers, SE; ³Christmann Informationstechnik + Medien GmbH & Co. KG, DE; ⁴Helmholtz-Zentrum für Infektionsforschung GmbH, DE; ⁵MAXELER, GB; ⁶MIS, SE; ⁷TECHNION, IL; ⁸Technion, IL; ⁹TU Dresden, DE; ¹⁰UNIBI, DE; ¹¹UNINE, CH 1530 Efficient Compilation and Execution of JVM-Based Data Processing Frameworks on Heterogeneous Co-Processors Speaker: Athanasios Stratikopoulos, The University of Manchester, GB Authors: Christos Kotselidis¹, Ioannis Komnios², Orestis Akrivopoulos³, Sebastian Bress⁴, Katerina Doka⁵, Hazeef Mohammed⁶, Georgios Mylonas⁷, Vassilis Spitadakis⁸, Daniel Strimpel⁹, Juan Fumero¹, Foivos S. Zakkak¹, Michail Papadimitriou¹, Maria Xekalaki¹, Nikos Foutris¹, Athanasios Stratikopoulos¹, Nectarios Koziris⁵, Ioannis Konstantinou⁵, Ioannis Mytilinis⁵, Constantinos Bitsakos⁵, Christos Tsalidis⁸, Christos Tselios³, Nikolaos Kanakis³, Clemens Lutz⁴, Viktor Rosenfeld⁴ and Volker Markl⁴ ¹The University of Manchester, GB; ²Exus Ltd., US; ³Spark Works ITC Ltd., GB; ⁴German Research Center for Artificial Intelligence, DE; ⁵National TU Athens, GR; ⁶Kaleao Ltd., GB; ⁷Computer Technology Institute & Press Diophantus, GR; ⁸Neurocom Luxembourg, LU; ⁹IProov Ltd., GB 3.4 Accelerating Neural Networks and Vision Workloads Stendhal 1430 - 1600 Chair:Leonidas Kosmidis, BSC, ES Co-Chair:Georgios Keramidas, Aristotle University of Thessaloniki/Think Silicon S.A., GR This session presents different solutions to accelerate emerging applications. The papers include various microarchitecture techniques as well as complete SoC and RISC-V based solutions. More fine-grained techniques are also presented like fast computations on sparse matrices. Vision applications are represented by the popular VSLAM, while various types and forms of emerging Neural Networks (such as Recurrent, Quantized, and Siamese NNs ) are considered. 1430 PSB-RNN: A Processing-in-Memory Systolic ArrayArchitecture using Block Circulant Matrices for Recurrent Neural Networks Speaker: Nagadastagiri Challapalle, Pennsylvania State University, US Authors: Nagadastagiri Challapalle¹, Sahithi Rampalli¹, Makesh Tarun Chandran¹, Gurpreet Singh Kalsi², John (Jack) Sampson¹, Sreenivas Subramoney² and Vijaykrishnan Narayanan¹ ¹Pennsylvania State University, US; ²Intel Labs, IN 1500 XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions Speaker: Angelo Garofalo, Università di Bologna, IT Authors: Angelo Garofalo¹, Giuseppe Tagliavini¹, Francesco Conti², Davide Rossi¹ and Luca Benini² ¹Università di Bologna, IT; ²ETH Zurich, CH / Università di Bologna, CH 1530 SNA: A Siamese Network Accelerator to Exploit the Model-Level Parallelism of Hybrid Network Structure Speaker: Xingbin Wang, Chinese Academy of Sciences, CN Authors: Xingbin Wang, Boyan Zhao, Rui Hou and Dan Meng, Chinese Academy of Sciences, CN 1545 HcveAcc: A High-Performance and Energy-Efficient Accelerator for Tracking Task in VSLAM System Speaker: Meng Liu, Chinese Academy of Sciences, CN Authors: Li Renwei, Wu Junning, Liu Meng, Chen Zuding, Zhou Shengang and Feng Shanggong, Chinese Academy of Sciences, CN IPs IP1-13, IP1-14 3.5 Parallel real-time systems Bayard 1430 - 1600 Chair:Liliana Cucu-Grosjean, Inria, FR Co-Chair:Antoine Bertout, ENSMA, FR This session presents novel techniques to enable parallel execution in real-time systems. More precisely, the papers are solving limitations of previous DAG models, devising tool chains to ensure WCET bounds, correcting results on heterogeneous processors, and considering wireless networks with application-oriented scheduling. 1430 On the Volume Calculation for Conditional DAG Tasks: Hardness and Algorithms Speaker: Jinghao Sun, Northeastern University, CN Authors: Jinghao Sun¹, Yaoyao Chi¹, Tianfei Xu¹, Lei Cao¹, Nan Guan², Zhishan Guo³ and Wang Yi⁴ ¹Northeastern University, CN; ²The Hong Kong Polytechnic University, CN; ³University of Central Florida, US; ⁴Uppsala universitet, SE 1500 WCET-aware Code Generation and Communication Optimization for Parallelizing Compilers Speaker: Simon Reder, Karlsruhe Institute of Technology, DE Authors: Simon Reder and Juergen Becker, Karlsruhe Institute of Technology, DE 1530 Template schedule construction for global real-time scheduling on unrelated multiprocessor platforms Authors: Antoine Bertout¹, Joel Goossens², Emmanuel Grolleau³ and Xavier Poczekajlo⁴ ¹LIAS, Université de Poitiers, ISAE-ENSMA, FR; ²ULB, BE; ³LIAS, ISAE-ENSMA, Universite de Poitiers, FR; ⁴Université libre de Bruxelles, BE 1545 Application-Aware Scheduling of Networked Applications over the Low-Power Wireless Bus Speaker: Kacper Wardega, Boston University, US Authors: Kacper Wardega and Wenchao Li, Boston University, US IPs IP1-15, IP1-16 3.6 NoC in the age of neural network and approximate computing Lesdiguières 1430 - 1600 Chair:Romain Lemaire, CEA-Leti, FR To support innovative applications, new paradigms have been introduced, such as neural network and approximate computing. This session presents different NoC-based architectures that support these computing approaches. In these advanced architectures, NoC designs are no longer only a communication infrastructure but also part of the computing system. Different mechanisms are introduced at network-level to support the application and thus enhance the performance and power efficiency. As such, new NoC-based architectures must respond to highly demanding applications such as image segmentation and classification by taking advantage of new topologies (multiple layers, 3D…) and new technologies, such as ReRAM. 1430 GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation Speaker: Biresh Joardar, Washington State University, US Authors: Biresh Kumar Joardar¹, Nitthilan Kannappan Jayakodi¹, Jana Doppa¹, Partha Pratim Pande¹, Hai (Helen) Li² and Krishnendu Chakrabarty³ ¹Washington State University, US; ²Duke University, US / TU Munich, US; ³Duke University, US 1500 An approximate multiplane network-on-chip Speaker: Xiaohang Wang, South China University of Technology, CN Authors: Ling Wang¹, Xiaohang Wang² and Yadong Wang¹ ¹Harbin Institute of Technology, CN; ²South China University of Technology, CN 1530 Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chip Speaker: Bo Wang, National University of Singapore, SG Authors: Bo Wang, Jun Zhou, Weng-Fai Wong and Li-Shiuan Peh, National University of Singapore, SG IPs IP1-17 3.7 Augmented and Assisted Living: A reality Berlioz 1430 - 1600 Chair:Graziano Pravadelli, Università di Verona, IT Co-Chair:Vassilis Pavlidis, Aristotle University of Thessaloniki, GR Novel solutions for healthcare and ambient assistant living: innovative brain-computer interfaces, novel cancer prediction systems and energy-efficient ECG and wearable systems. 1430 Compressing Subject-Specific Brain-Computer Interface Models into One Model by Superposition in Hyperdimensional Space Speaker: Michael Hersche, ETH Zurich, CH Authors: Michael Hersche, Philipp Rupp, Luca Benini and Abbas Rahimi, ETH Zurich, CH 1500 A novel FPGA-based system for Tumor Growth Prediction Speaker: Yannis Papaefstathiou, Aristotle University of Thessaloniki, GR Authors: Konstantinos Malavazos¹, Maria Papadogiorgaki¹, PAVLOS MALAKONAKIS¹ and Ioannis Papaefstathiou² ¹TU Crete, GR; ²Aristotle University of Thessaloniki, GR 1530 An Event-Based System for Low-Power ECG QRS Complex Detection Speaker: Silvio Zanoli, EPFL, CH Authors: Silvio Zanoli¹, Tomas Teijeiro¹, Fabio Montagna² and David Atienza¹ ¹EPFL, CH; ²Università di Bologna, IT 1545 Semi-Autonomous Personal Care Robots Interface driven by EEG Signals Digitization Speaker: Daniela De Venuto, Politecnico di Bari, IT Authors: Giovanni Mezzina and Daniela De Venuto, Politecnico di Bari, IT IPs IP1-18, IP1-19 IP1 Interactive Presentations Poster Area 1600 - 1630 Interactive Presentations run simultaneously during a 30-minute slot. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session IP1-1 DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys Speaker: Nimisha Limaye, New York University, US Authors: Nimisha Limaye¹ and Ozgur Sinanoglu² ¹New York University, US; ²New York University Abu Dhabi, AE IP1-2 CMOS Implementation of Switching Lattices Speaker: Levent Aksoy, Istanbul TU, TR Authors: Ismail Cevik, Levent Aksoy and Mustafa Altun, Istanbul TU, TR IP1-3 A Timing Uncertainty-Aware Clock Tree Topology Generation Algorithm for Single Flux Quantum Circuits Speaker: Massoud Pedram, University of Southern California, US Authors: Soheil Nazar Shahsavani, Bo Zhang and Massoud Pedram, University of Southern California, US IP1-4 Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP Speaker: Antonios Pavlidis, Sorbonne Université, CNRS, LIP6, FR Authors: Antonios Pavlidis¹, Marie-Minerve Louerat¹, Eric Faehn², Anand Kumar³ and Haralampos-G. Stratigopoulos¹ ¹Sorbonne Université, CNRS, LIP6, FR; ²STMicroelectronics, FR; ³STMicroelectronics, IN IP1-5 Range Controlled Floating-Gate Transistors: A Unified Solution for Unlocking and Calibrating Analog ICs Speaker: Yiorgos Makris, University of Texas at Dallas, US Authors: Sai Govinda Rao Nimmalapudi, Georgios Volanis, Yichuan Lu, Angelos Antonopoulos, Andrew Marshall and Yiorgos Makris, University of Texas at Dallas, US IP1-6 Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability Cancellation Speaker: Koutaro Hachiya, Teikyo Heisei University, JP Authors: Koutaro Hachiya¹ and Atsushi Kurokawa² ¹Teikyo Heisei University, JP; ²Hirosaki University, JP IP1-7 TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPU Speaker: Zdenek Vasicek, Brno University of Technology, CZ Authors: Filip Vaverka, Vojtech Mrazek, Zdenek Vasicek and Lukas Sekanina, Brno University of Technology, CZ IP1-8 Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities Speaker: Valentin Gherman, CEA, FR Authors: Valentin Gherman, Samuel Evain and Bastien Giraud, CEA, FR IP1-9 BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory Speaker: Meng Zhang, Huazhong University of Science & Technology, CN Authors: Meng Zhang, Fei Wu, Qin Yu, Weihua Liu, Lanlan Cui, Yahui Zhao and Changsheng Xie, Huazhong University of Science & Technology, CN IP1-10 Poisoning the (Data) Well in ML-based CAD: A Case Study of Hiding Lithographic Hotspots Speaker: Kang Liu, New York University, US Authors: Kang Liu, Benjamin Tan, Ramesh Karri and Siddharth Garg, New York University, US IP1-11 SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware Speaker: Milind Srivastava, IIT Madras, IN Authors: Milind Srivastava¹, PATANJALI SLPSK¹, Indrani Roy¹, Chester Rebeiro¹, Aritra Hazra² and Swarup Bhunia³ ¹IIT Madras, IN; ²IIT Kharagpur, IN; ³University of Florida, US IP1-12 Formal Synthesis of Monitoring and Detection Systems for Secure CPS Implementations Speaker: Ipsita Koley, IIT Kharagpur, IN Authors: Ipsita Koley¹, Saurav Kumar Ghosh¹, Dey Soumyajit¹, Debdeep Mukhopadhyay¹, Amogh Kashyap K N², Sachin Kumar Singh², Lavanya Lokesh², Jithin Nalu Purakkal² and Nishant Sinha² ¹IIT Kharagpur, IN; ²Robert Bosch Engineering and Business Solutions Private Limited, IN IP1-13 ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory Speaker: Bahar Asgari, Georgia Tech, US Authors: Bahar Asgari, Ramyad Hadidi and Hyesoon Kim, Georgia Tech, US IP1-14 Acceleration of probabilistic reasoning through custom processor architecture Speaker: Nimish Shah, KU Leuven, BE Authors: Nimish Shah, Laura I. Galindez Olascoaga, Wannes Meert and Marian Verhelst, KU Leuven, BE IP1-15 A Performance Analysis Framework for Real-Time Systems Sharing Multiple Resources Speaker: Shayan Tabatabaei Nikkhah, Eindhoven University of Technology, NL Authors: Shayan Tabatabaei Nikkhah¹, Marc Geilen¹, Dip Goswami¹ and Kees Goossens² ¹Eindhoven University of Technology, NL; ²Eindhoven university of technology, NL IP1-16 Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core Systems Speaker: Matheus Schuh, Verimag / Kalray, FR Authors: Matheus Schuh¹, Maximilien Dupont de Dinechin², Matthieu Moy³ and Claire Maiza⁴ ¹Verimag / Kalray, FR; ²ENS Paris / ENS Lyon / LIP, FR; ³ENS Lyon / LIP, FR; ⁴Grenoble INP / Verimag, FR IP1-17 Lightweight Anonymous Routing in NoC based SoCs Speaker: Prabhat Mishra, University of Florida, US Authors: Subodha Charles, Megan Logan and Prabhat Mishra, University of Florida, US IP1-18 A Non-invasive Wearable Bioimpedance System to Wirelessly Monitor Bladder Filling Speaker: Michele Magno, ETH Zurich, CH Authors: Markus Reichmuth, Simone Schuerle and Michele Magno, ETH Zurich, CH IP1-19 InfiniWolf: Energy Efficient Smart Bracelet for Edge Computing with Dual Source Energy Harvesting Speaker: Michele Magno, ETH Zurich, CH Authors: Michele Magno¹, Xiaying Wang¹, Manuel Eggimann¹, Lukas Cavigelli¹ and Luca Benini² ¹ETH Zurich, CH; ²Università di Bologna and ETH Zurich, IT 4.1 Hardware-enabled security Amphithéâtre Jean Prouve 1700 - 1830 Chair:Marchand Cedric, Ecole Centrale de Lyon, FR Co-Chair:Hai Zhou, Northwestern University, US This session covers solutions in hardware-based design to improve security. The papers in the session propose a NTT (Number Theoretic Transform) technique enabling faster polynomial multiplication, a reliable key-PUF for key generation, and a runtime circuit de-obfuscating solution. Post-Quantum cryptography and new attacks will be discussed along this session. 1700 A Flexible and Scalable NTT Hardware: Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography Speaker: Ahmet Can Mert, Sabanci University, TR Authors: Ahmet Can Mert¹, Emre Karabulut², Erdinc Ozturk¹, Erkay Savas¹, Michela Becchi² and Aydin Aysu² ¹Sabanci University, TR; ²North Carolina State University, US 1730 Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture Speaker: Jeong-Hyeon Kim, Sungkyunkwan University, KR Authors: Jeong-Hyeon Kim¹, Ho-Jun Jo¹, Kyung-kuk Jo¹, Sunghee Cho¹, Jaeyong Chung² and Joon-Sung Yang¹ ¹Sungkyunkwan University, KR; ²Incheon National University, KR 1800 Estimating the Circuit De-obfuscation Runtime based on Graph Deep Learning Speaker: Gaurav Kolhe, George Mason University, US Authors: Zhiqian Chen¹, Gaurav Kolhe², Setareh Rafatirad², Chang-Tien Lu¹, Sai Manoj Pudukotai Dinakarrao², Houman Homayoun² and Liang Zhao² ¹Virginia Tech, US; ²George Mason University, US IPs IP2-1, IP2-2 4.2 Timing in System-Level Modeling and Simulation Chamrousse 1700 - 1830 Chair:Jorn Janneck, Lund University, SE Co-Chair:Gianluca Palermo, Politecnico di Milano, IT Given the importance of time in specifying and modeling systems, this session presents three contributions at different levels of abstraction, from transaction-level to system level. While the first two contributions attempt to give fast and accurate simulation models for DRAM memories and analog mixed systems, the last one models uncertainties at higher-level for reasoning and formal verification purpose. 1700 Fast and Accurate DRAM Simulation: Can we Further Accelerate it? Speaker: Matthias Jung, Fraunhofer IESE, DE Authors: Johannes Feldmann¹, Matthias Jung², Kira Kraft¹, Lukas Steiner¹ and Norbert Wehn¹ ¹TU Kaiserslautern, DE; ²Fraunhofer IESE, DE 1730 Accurate and Efficient Continuous Time and Discrete Events Simulation in SystemC Speaker: Breytner Fernandez-Mesa, TIMA Laboratory, University Grenoble Alpes, FR Authors: Breytner Fernandez-Mesa, Liliana Andrade and Frédéric Pétrot, TIMA Lab, Université Grenoble Alpes, FR 1800 Modeling and Verifying Uncertainty-Aware TimingBehaviors using Parametric Logical Time Constraint Speaker: Fei Gao, East China Normal University, CN Authors: Fei Gao¹, Mallet Frederic², Min Zhang¹ and Mingsong Chen³ ¹East China Normal University, CN; ²Universite Cote d'Azur, CNRS, Inria, I3S, Nice, France, FR; ³East China Normal University, FR IPs IP2-3, IP2-4 4.3 EU Projects on Nanoelectronics with CMOS and alternative technologies Autrans 1700 - 1830 Chair:Dimitris Gizopoulos, UoA, GR Co-Chair:George Karakonstantis, Queen's University Belfast, GR This session presents the results of three European Projects in different stages of execution covering the development of a complete synthesis and optimization methodology for nano-crossbar arrays; the reliability, security, and associated EDA tools for nanoelectronic systems, and the exploitation of STT-MTJ technologies for heterogeneous function implementation. 1700 Nano-Crossbar based Computing: Lessons Learned and Future Directions Speaker: Mustafa Altun, Istanbul TU, TR Authors: Mustafa Altun¹, Ismail Cevik¹, Ahmet Erten¹, Osman Eksik¹, Mircea Stan² and Csaba Moritz³ ¹Istanbul TU, TR; ²University of Virginia, US; ³University of Massachusetts Amherst, US 1730 RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Speaker: Maksim Jenihhin, Tallinn University of Technology, EE Authors: Maksim Jenihhin¹, Said Hamdioui², Matteo Sonza Reorda³, Milos Krstic⁴, Peter Langendoerfer⁴, Christian Sauer⁵, Anton Klotz⁵, Michael Huebner⁶, Joerg Nolte⁶, H.T. Vierhaus⁶, Georgios Selimis⁷, Dan Alexandrescu⁸, Mottaqiallah Taouil², Geert-Jan Schrijen⁷, Luca Sterpone³, Giovanni Squillero³, Zoya Dyka⁴ and Jaan Raik¹ ¹Tallinn University of Technology, EE; ²TU Delft, NL; ³Politecnico di Torino, IT; ⁴Leibniz-Institut für innovative Mikroelektronik, DE; ⁵Cadence Design Systems, DE; ⁶BTU Cottbus-Senftenberg, DE; ⁷Intrinsic-ID, NL; ⁸IROC Technologies, FR 1800 A Universal Spintronic Technology based on Multifunctional Standardized Stack Speaker: Mehdi Tahoori, Karlsruhe Institute of Technology, DE Authors: Mehdi Tahoori¹, Sarath Mohanachandran Nair¹, Rajendra Bishnoi², Lionel Torres³, Guillaume Partigeon⁴, Gregory DiPendina⁵ and Guillaume Prenat⁵ ¹Karlsruhe Institute of Technology, DE; ²TU Delft, NL; ³Université de Montpellier, FR; ⁴LIRMM, FR; ⁵Spintec, FR 4.4 Some run it hot, others do not Stendhal 1700 - 1830 Chair:Pascal Vivet, CEA-Leti, FR Co-Chair:Daniele J. Pagliari, Politecnico di Torino, IT Temperature management is a must-have in modern computing systems. The session presents a set of techniques for smart cooling systems, both active and pro-active, and thermal control policies. The techniques presented are vertically applied to different components, such as computing and communication sub-systems, and use orthogonal modeling and optimization strategies, such as machine-learning. 1700 A Learning-Based Thermal Simulation Framework for Emerging Two-Phase Cooling Technologies Speaker: Ayse Coskun, Boston University, US Authors: Zihao Yuan¹, Geoffrey Vaartstra², Prachi Shukla¹, Zhengmao Lu², Evelyn Wang², Sherief Reda³ and Ayse Coskun¹ ¹Boston University, US; ²Massachusetts Institute of Technology, US; ³Brown University, US 1730 Lightweight Thermal Monitoring in Optical Networks-on-Chip via Router Reuse Speaker: Mengquan Li, Nanyang Technological University, SG Authors: Mengquan Li¹, Jun Zhou² and Weichen Liu² ¹Nanyang Technological University, CN; ²Nanyang Technological University, SG 1800 A Spectral Approach to Scalable Vectorless Thermal Integrity Verification Speaker: Zhuo Feng, Stevens Institute of Technology, US Authors: Zhiqiang Zhao¹ and Zhuo Feng² ¹Michigan Technological University, US; ²Stevens Institute of Technology, US 1815 Dynamic Thermal Management with Proactive Fan Speed Control Through Reinforcement Learning Speaker: Arman Iranfar, EPFL, CH Authors: Arman Iranfar¹, Federico Terraneo², Gabor Csordas¹, Marina Zapater¹, William Fornaciari² and David Atienza¹ ¹EPFL, CH; ²Politecnico di Milano, IT IPs IP2-5, IP2-6 4.5 Adaptation and optimization for real-time systems Bayard 1700 - 1830 Chair:Wanli Chang, University of york, GB Co-Chair:Emmanuel Grolleau, ENSMA, FR This session presents novel techniques for systems requiring adaptations. The papers in this session are including monitoring techniques to increase reactivity, considering weakly-hard constraints, extending previous cache persistence analyses from one core to several cores, and modeling data chains while latency bounds are ensured. 1700 Reliable and Energy-Aware Fixed-Priority (m,k)-Deadlines Enforcement with Standby-Sparing Speaker: Linwei Niu, West Virginia State University, US Authors: Linwei Niu¹ and Dakai Zhu² ¹West Virginia State University, US; ²University of Texas at San Antonio, US 1730 Period Adaptation for Continuous Security Monitoring in Multicore Real-Time Systems Speaker: Monowar Hasan, University of Illinois at Urbana-Champaign, US Authors: Monowar Hasan¹, Sibin Mohan², Rodolfo Pellizzoni³ and Rakesh Bobba⁴ ¹University of Illinois at Urbana-Champaign, US; ²University of Illinois at Urbana-Champaign (UIUC), US; ³University of Waterloo, CA; ⁴Oregon State University, US 1800 Efficient Latency Bound Analysis for Data Chains of Real-Time Tasks in Multiprocessor Systems Speaker: Jiankang Ren, Dalian University of Technology, CN Authors: Jiankang Ren¹, Xin He¹, Junlong Zhou², Hongwei Ge¹, Guowei Wu¹ and Guozhen Tan¹ ¹Dalian University of Technology, CN; ²Nanjing University of Science and Technology, CN 1815 Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems Speaker: Syed Aftab Rashid, Polytechnic Institute of Porto, PT Authors: Syed Aftab Rashid, Geoffrey Nelissen and Eduardo Tovar, Polytechnic Institute of Porto, PT IPs IP2-7 4.6 Artificial Intelligence and Secure Systems Lesdiguières 1700 - 1830 Chair:Annelie Heuser, Univ Rennes, Inria, CNRS, France, FR Co-Chair:Ilia Polian, University of Stuttgart, DE In this session we will cover artificial intelligence algorithms in the context of secure systems. The presented papers cover an extension of a trusted execution environment to securely run machine learning algorithms, novel attacking strategies against logic-locking countermeasures, and an investigation of aging effects on the success rate of machine learning modelling attacks. 1700 A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking In The Absence of Scan Access Speaker: Rajit Karmakar, IIT KHARAGPUR, IN Authors: RAJIT KARMAKAR and Santanu Chattopadhyay, IIT Kharagpur, IN 1730 Effect of Aging on PUF Modeling Attacks based on Power Side-Channel Observations Speaker: Trevor Kroeger, University of Maryland Baltimore County, US Authors: Trevor Kroeger¹, Wei Cheng², Jean Luc Danger³, Sylvain Guilley⁴ and Naghmeh Karimi⁵ ¹University of Maryland Baltimore County, US; ²Telecom ParisTech, FR; ³Télécom ParisTech, FR; ⁴Secure-IC, FR; ⁵University of Maryland, Baltimore County, US 1800 Offline Model Guard: Secure and Private ML on Mobile Devices Speaker: Emmanuel Stapf, TU Darmstadt, DE Authors: Sebastian P. Bayerl¹, Tommaso Frassetto², Patrick Jauernig², Korbinian Riedhammer¹, Ahmad-Reza Sadeghi², Thomas Schneider², Emmanuel Stapf² and Christian Weinert² ¹TH Nürnberg, DE; ²TU Darmstadt, DE 4.7 Future computing fabrics: security and design integration Berlioz 1700 - 1830 Chair:Elena Gnani, Università di Bologna, IT Co-Chair:Gage Hills, Massachusetts Institute of Technology, US Emerging technologies always promise to achieve computational and resource-efficiency. This session addresses various aspects of efficiency in the context of security and future computing fabrics: a unique challenge at the intersection of hardware security and machine learning, fully front-end compatible CAD frameworks to enable access to floating-gate memristive devices, and current recycling in superconducting circuits. 1700 Security Enhancement for RRAM Computing System through Obfuscating Crossbar Row Connections Speaker: Minhui Zou, Nanjing University of Science and Technology, CN Authors: Minhui Zou¹, Zhenhua Zhu², Yi Cai², Junlong Zhou¹, Chengliang Wang³ and Yu Wang² ¹Nanjing University of Science and Technology, CN; ²Tsinghua University, CN; ³Chongqing University, CN 1730 Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing Speaker: Loai Danial, Technion, IL Authors: Loai Danial¹, Vasu Gupta², Evgeny Pikhay³, Yakov Roizin³ and Shahar Kvatinsky¹ ¹Technion, IL; ²Technion, IN; ³TowerJazz, IL 1800 Ground plane partitioning for current recycling of superconducting circuits Speaker: Naveen Katam, University of Southern California, US Authors: Naveen Kumar Katam, Bo Zhang and Massoud Pedram, University of Southern California, US 1815 Silicon Photonic Microring Resonators: Design Optimization Under Fabrication Non-Uniformity Speaker: Mahdi Nikdast, Colorado State University, US Authors: Asif Mirza, Febin Sunny, Sudeep Pasricha and Mahdi Nikdast, Colorado State University, US IPs IP2-8, IP2-9 5.1 Special Day on "Embedded AI": Tutorial Overviews Amphithéâtre Jean Prouve 0830 - 1000 Chair:Dmitri Strukov, University of California, Santa Barbara, US Co-Chair:Bernabe Linares-Barranco, CSIC, ES This session aims to provide a more tutorial overview of hardware AI case studies and some proposed solutions, problems, and challenges. 0830 Neural Networks circuits based on resistive memories Author: Carlo Reita, CEA, FR 0915 Exploiting activation sparsity in DRAM-based scalable CNN and RNN accelerators Author: Tobi Delbrück, ETH Zurich, CH 5.2 Machine Learning Approaches to Analog Design Chamrousse 0830 - 1000 Chair:Marie-Minerve Louerat, Sorbonne University Lip6, FR Co-Chair:Sebastien Cliquennois, STMicroelectronics, FR This session presents recent advances in machine learning approaches to support the design of analog and mixed-signal circuits. Techniques such as reinforced learning and convolutional networks are employed to address circuit and layout optimization. The presented techniques have a great potential for seeding innovative solutions to face current and future challenges in this field. 0830 AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs Speaker: Keertana Settaluri, University of California, Berkeley, US Authors: Keertana Settaluri, Ameer Haj-Ali, Qijing Huang, Kourosh Hakhamaneshi and Borivoje Nikolic, University of California, Berkeley, US 0900 Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning Speaker: David Pan, University of Texas at Austin, US Authors: Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun and David Z. Pan, University of Texas at Austin, US 0930 Design of Multi-Output Switched-Capacitor Voltage Regulator via Machine Learning Speaker: Zhiyuan Zhou, Washington State University, US Authors: Zhiyuan Zhou¹, Syrine Belakaria², Aryan Deshwal², Wookpyo Hong¹, Jana Doppa², Partha Pratim Pande¹ and Deukhyoun Heo¹ ¹Washington State University, US; ²‎Washington State University, US IPs IP2-10, IP2-11 5.3 Special Session: Secure Composition of Hardware Systems Autrans 0830 - 1000 Chair:Ilia Polian, Stuttgart University, DE Co-Chair:Francesco Regazzoni, ALARI, CH Today's electronic systems consist of mixtures of programmable, reconfigurable, and application- specific hardware components, tied together by tremendously complex software. At the same time, systems are increasingly integrated such that a sub-system that was traditionally regarded "harm- less" (car's entertainment system) finds itself tightly coupled with safety-critical sub-systems (driving assistance) and security-sensitive sub-systems such as online payment and others. Moreover, a system's hardware components are now often directly accessible to the end users and thus vulnerable to physical attacks. The goal of this hot-topic session is to establish a common understanding of principles and techniques that can facilitate composition and integration of hardware systems and achieve security guarantees. Theoretical foundations of secure composition are currently limited to software systems, and unique security challenges arise when a real system, composed of a range of hardware components with different owners and trust assumptions is put together. Physical and side-channel attacks add another level of complexity to the problem of secure composition. Moreover, practical hardware systems include software stacks of tremendous size and complexity, and hardware- software interaction can create new security challenges. This hot-topic session will consider secure composition both from a purely hardware-centric and from a hardware-software perspective in a more complex system. It will also target composition of countermeasures against hardware-centric attacks and against software-driven attacks on hardware. It brings together researchers and industry practitioners who deal with secure composition: security- oriented electronic design automation; secure architectures of automotive hardware-software systems; and advanced attack scenarios against complexed hardware systems. 0830 Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA Speaker: Johann Knechtel, New York University Abu Dhabi, AE Authors: Johann Knechtel¹, Elif Bilge Kavun², Francesco Regazzoni³, Annelie Heuser⁴, Anupam Chattopadhyay⁵, Debdeep Mukhopadhyay⁶, Dey Soumyajit⁶, Yunsi Fei⁷, Yaacov Belenky⁸, Itamar Levi⁹, Tim Güneysu¹⁰, Patrick Schaumont¹¹ and Ilia Polian¹² ¹New York University Abu Dhabi, AE; ²University of Sheffield, GB; ³ALaRI, CH; ⁴Université de Rennes / Inria / CNRS / IRISA, FR; ⁵Nanyang Technological University, SG; ⁶IIT Kharagpur, IN; ⁷Northeastern University, US; ⁸Intel, IL; ⁹Bar-Ilan University, IL; ¹⁰Ruhr-University Bochum, DE; ¹¹Worcester Polytechnic Institute, US; ¹²University of Stuttgart, DE 0855 Attacker Modeling on Composed Systems Speaker: Pierre Schnarz, Continental AG, DE Authors: Tobias Basic, Jan Müller, Pierre Schnarz and Marc Stoettinger, Continental AG, DE 0915 Pitfalls in Machine Learning-based Adversary Modeling for Hardware Systems Speaker: Fatemeh Ganji, University of Florida, US Authors: Fatemeh Ganji¹, Sarah Amir¹, Shahin Tajik¹, Jean-Pierre Seifert² and Domenic Forte¹ ¹University of Florida, US; ²TU Berlin, DE 0935 Using Universal Composition to Design and Analyze Secure Complex Hardware Systems Speaker: Marten van Dijk, University of Connecticut, US Authors: Ran Canetti¹, Marten van Dijk², Hoda Maleki³, Ulrich Rührmair⁴ and Patrick Schaumont⁵ ¹Boston University, US; ²University of Connecticut, US; ³University of Augusta, US; ⁴TU Munich, DE; ⁵Worcester Polytechnic Institute, US 5.4 New Frontiers in Formal Verification for Hardware Stendhal 0830 - 1000 Chair:Alessandro Cimatti, Fondazione Bruno Kessler, IT Co-Chair:Heinz Riener, EPFL, CH The session presents several new techniques in hardware verification. The technical papers propose methods for the formal verification of industrial arithmetic circuits and processors, and show how reinforcement learning can be used for verification of shared memory protocols. Two interactive presentations describe how to use high-level synthesis to supply security guarantees and to generate certificates when verifying multipliers. 0830 Gap-free Processor Verification by S²QED and Property Generation Speaker: Keerthikumara Devarajegowda, Infineon Technologies, DE Authors: Keerthikumara Devarajegowda¹, Mohammad Rahmani Fadiheh², Eshan Singh³, Clark Barrett³, Subhasish Mitra³, Wolfgang Ecker¹, Dominik Stoffel² and Wolfgang Kunz² ¹Infineon Technologies, DE; ²TU Kaiserslautern, DE; ³Stanford University, US 0900 SPEAR: Hardware-based Implicit Rewriting for Square-root Verification Speaker: Maciej Ciesielski, University of Massachusetts Amherst, US Authors: Atif Yasin¹, Tiankai Su¹, Sebastien Pillement² and Maciej Ciesielski¹ ¹University of Massachusetts Amherst, US; ²University of Nantes France, FR 0930 A Reinforcement Learning Approach to Directed Test Generation for Shared Memory Verification Speaker: Nícolas Pfeifer, Federal University of Santa Catarina, BR Authors: Nicolas Pfeifer, Bruno V. Zimpel, Gabriel A. G. Andrade and Luiz C. V. dos Santos, Federal University of Santa Catarina, BR 0945 Towards Formal Verification of Optimized and Industrial Multipliers Speaker: Alireza Mahzoon, University of Bremen, DE Authors: Alireza Mahzoon¹, Daniel Grosse², Christoph Scholl³ and Rolf Drechsler² ¹University of Bremen, DE; ²University of Bremen / DFKI, DE; ³University of Freiburg, DE IPs IP2-12, IP2-13 5.5 Model-Based Analysis and Security Bayard 0830 - 1000 Chair:Ylies Falcone, University Grenoble Alpes and Inria, FR Co-Chair:Todd Austin, University of Michigan, US The session explores the use of state-of-the-art model-based analysis and verification techniques to secure and improve the performance of embedded systems. More specifically, it presents the use of satisfiability modulo theory, runtime monitoring, fuzzing, and model-checking to evaluate how secure is a system, prevent, and detect attacks. 0830 Is Register Transfer Level Locking Secure? Speaker: Chandan Karfa, IIT Guwahati, IN Authors: Chandan Karfa¹, Ramanuj Chouksey¹, Christian Pilato², Siddharth Garg³ and Ramesh Karri³ ¹IIT Guwahati, IN; ²Politecnico di Milano, IT; ³New York University, US 0900 Design Space Exploration for Model-based Communication Systems Speaker: Valentina Richthammer, University of Ulm, DE Authors: Valentina Richthammer, Marcel Rieß, Julian Bestler, Frank Slomka and Michael Glaß, University of Ulm, DE 0930 Statistical Time-based Intrusion Detection in Embedded Systems Speaker: Nadir Carreon Rascon, University of Arizona, US Authors: Nadir Carreon Rascon, Allison Gilbreath and Roman Lysecky, University of Arizona, US IPs IP2-14, IP2-15 5.6 Logic synthesis towards fast, compact, and secure designs Lesdiguières 0830 - 1000 Chair:Valeria Bertacco, University of Michigan, US Co-Chair:Lukas Sekanina, Brno University of Technology, CZ The logic synthesis family is growing. While traditional optimization goals such as area and delay are still very important in todays design automation, new applications require improvement of aspects such as security or power consumption. This session showcases various algorithms addressing both emerging and traditional optimization goals. An algorithm is proposed for cryptographic applications which reduces the multiplicative complexity thereby making designs less vulnerable to attacks. A synthesis method converts flip-flops to latches in a clever way and saves power in this way. Approximation and bi-decomposition techniques are used in an area optimization strategy. Finally, a methodology for design minimization in advanced technology nodes is presented that takes both wire congestion and coupling effects into account. 0830 A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks Speaker: Eleonora Testa, EPFL, CH Authors: Eleonora Testa¹, Mathias Soeken¹, Heinz Riener¹, Luca Amaru² and Giovanni De Micheli¹ ¹EPFL, CH; ²Synopsys, US 0900 Saving Power by Converting Flip-Flop to 3-Phase Latch-Based Designs Speaker: Peter Beerel, University of Southern California, US Authors: Huimei Cheng, Xi Li, Yichen Gu and Peter Beerel, University of Southern California, US 0930 Computing the full quotient in bi-decomposition by approximation Speaker: Valentina Ciriani, University of Milan, IT Authors: Anna Bernasconi¹, Valentina Ciriani², Jordi Cortadella³ and Tiziano Villa⁴ ¹Università di Pisa, IT; ²Universita' degli Studi di Milano, IT; ³UPC, ES; ⁴Università di Verona, IT 0945 MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes Speaker: Xinghai Zhang, Fuzhou University, CN Authors: Xinghai Zhang¹, Zhen Zhuang¹, Genggeng Liu¹, Xing Huang², Wen-Hao Liu³, Wenzhong Guo¹ and Ting-Chi Wang² ¹Fuzhou University, CN; ²National Tsing Hua University, TW; ³Cadence Design Systems, US IPs IP2-16, IP2-17 5.7 Stochastic Computing Berlioz 0830 - 1000 Chair:Robert Wille, Johannes Kepler University Linz, AT Co-Chair:Shigeru Yamashita, Ritsumeikan, JP Stochastic computing uses random bitstreams to reduce computational and area costs of a general class of Boolean operations, including arithmetic addition and multiplication. This session considers stochastic computing from a model-, accuracy-, and applications-perspective, by presenting papers that span from models of pseudo-random number generators, to accuracy analysis of stochastic circuits, to novel applications for signal processing tasks. 0830 The Hypergeometric Distribution as a More Accurate Model for Stochastic Computing Speaker: Timothy Baker, University of Michigan, US Authors: Timothy Baker and John Hayes, University of Michigan, US 0900 Accuracy Analysis for Stochastic Circuits with D-Flip Flop Insertion Speaker: Kuncai Zhong, University of Michigan-Shanghai Jiao Tong University Joint Institute, CN Authors: Kuncai Zhong and Weikang Qian, Shanghai Jiao Tong University, CN 0930 Dynamic Stochastic Computing for Digital Signal Processing Applications Speaker: Jie Han, University of Alberta, CA Authors: Siting Liu and Jie Han, University of Alberta, CA IPs IP2-18, IP2-19, IP2-20 5.8 Special Session: HLS for AI HW Exhibition Theatre 0830 - 1000 Chair:Massimo Cecchetti, Mentor, A Siemens Business, US Co-Chair:Astrid Ernst, Mentor, A Siemens Business, US One of the fastest growing areas of hardware and software design is artificial intelligence (AI)/machine learning (ML), fueled by the demand for more autonomous systems like self-driving vehicles and voice recognition for personal assistants. Many of these algorithms rely on convolutional neural networks (CNNs) to implement deep learning systems. While the concept of convolution is relatively straightforward, the application of CNNs to the ML domain has yielded dozens of different neural network approaches. These networks can be executed in software on CPUs/GPUs, the power requirements for these solutions make them impractical for most inferencing applications, the majority of which involve portable, low-power devices. To improve the power/performance, hardware teams are forming to create ML hardware acceleration blocks. However, the process of taking any one of these compute-intensive networks into hardware, especially energy-efficient hardware, is a time consuming process if the team employs a traditional RTL design flow. Consider all of these interdependent activities using a traditional flow: •Expressing the algorithm correctly in RTL. •Choosing the optimal bit-widths for kernel weights and local storage to meet the memory budget. •Designing the microarchitecture to have a low enough latency to be practical for the target application, while determining how the accelerator communicates across the system bus without killing the latency the team just fought for. •Verifying the algorithm early on and throughout the implementation process, especially in the context of the entire system. •Optimizing for power for mobile devices. •Getting the product to market on time. This domain is in desperate need of a productivity-boosting methodology shift away from an RTL flow. 0830 Introduction to HLS concepts open-source IP and References Designs enabling building AI Acceleration Hardware Author: Mike Fingeroff, Mentor, A Siemens Business, US 0900 Early SOC Performance Verification Using SystemC with NVIDIA MatchLib and HLS Author: Stuart Swan, Mentor, A Siemens Business, US 0930 Customer Case Studies of using HLS for ultra-low power AI Hardware acceleration Author: Ellie Burns, Mentor, A Siemens Business, US IP2 Interactive Presentations Poster Area 1000 - 1030 Interactive Presentations run simultaneously during a 30-minute slot. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session IP2-1 Sampling from Discrete Distributions in Combinational Hardware with Application to Post-Quantum Cryptography Speaker: Michael Lyons, George Mason University, US Authors: Michael Lyons and Kris Gaj, George Mason University, US IP2-2 On the performance of Non-Profiled Differential Deep Learning Attacks against an AES encryption algorithm protected using a Correlated Noise hiding countermeasure Speaker: Amir Alipour, Grenoble INP Esisar, FR Authors: Amir Alipour¹, Athanasios Papadimitriou², Vincent Beroulle³, Ehsan Aerabi³ and David Hely³ ¹University Grenoble Alpes, Grenoble INP ESISAR, LCIS Laboratory, FR; ²University Grenoble Alpes, Grenoble INP ESISAR, ESYNOV, FR; ³University Grenoble Alpes, Grenoble INP ESISAR, LSIC Laboratory, FR IP2-3 Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes Speaker: Vladimir Herdt, University of Bremen, DE Authors: Vladimir Herdt¹, Daniel Grosse² and Rolf Drechsler² ¹University of Bremen, DE; ²University of Bremen / DFKI, DE IP2-4 Automated Generation of LTL Specifications For Smart Home IoT Using Natural Language Speaker: Shiyu Zhang, Nanjing University, CN Authors: Shiyu Zhang¹, Juan Zhai¹, Lei Bu¹, Mingsong Chen², Linzhang Wang¹ and Xuandong Li¹ ¹Nanjing University, CN; ²East China Normal University, CN IP2-5 A Heat-Recirculation-Aware VM Placement Strategy for Data Centers Authors: Hao Feng¹, Yuhui Deng² and Yi Zhou³ ¹Jinan University, CN; ²Chinese Academy of Sciences; Jinan University, CN; ³Columbus State University, US IP2-6 Energy Optimization in NCFET-based Processors Authors: Sami Salamin¹, Martin Rapp¹, Hussam Amrouch¹, Andreas Gerstlauer² and Joerg Henkel¹ ¹Karlsruhe Institute of Technology, DE; ²University of Texas at Austin, US IP2-7 Towards a Model-based Multi-Objective Optimization Approach For Safety-Critical Real-Time Systems Speaker: Emmanuel Grolleau, LIAS / ISAE-ENSMA, FR Authors: Soulimane Kamni¹, Yassine OUHAMMOU², Antoine Bertout³ and Emmanuel Grolleau⁴ ¹LIAS/ENSMA, FR; ²LIAS / ISAE-ENSMA, FR; ³LIAS, Université de Poitiers, ISAE-ENSMA, FR; ⁴LIAS, ISAE-ENSMA, Universite de Poitiers, FR IP2-8 Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture Speaker: Shengqi Yu, Newcastle University, GB Authors: Shengqi Yu¹, Ahmed Soltan², Rishad Shafik¹, Thanasin Bunnam¹, Domenico Balsamo¹, Fei Xia¹ and Alex Yakovlev¹ ¹Newcastle University, GB; ²Nile University, EG IP2-9 n-bit Data Parallel Spin Wave Logic Gate Speaker: Abdulqader Mahmoud, TU Delft, NL Authors: Abdulqader Mahmoud¹, Frederic Vanderveken², Florin Ciubotaru², Christoph Adelmann², Sorin Cotofana¹ and Said Hamdioui¹ ¹TU Delft, NL; ²IMEC, BE IP2-10 High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors Speaker: Tom Kazmierski, University of Southampton, GB Authors: Gines Domenech-Asensi¹ and Tom J Kazmierski² ¹Universidad Politecnica de Cartagena, ES; ²University of Southampton, GB IP2-11 A 100KHz-1GHz Termination-dependent Human Body Communication Channel Measurement using Miniaturized Wearable Devices Speaker: Shreyas Sen, Purdue University, US Authors: Shitij Avlani, Mayukh Nath, Shovan Maity and Shreyas Sen, Purdue University, US IP2-12 From DRUP to PAC and Back Speaker: Daniela Kaufmann, Johannes Kepler University Linz, AT Authors: Daniela Kaufmann, Armin Biere and Manuel Kauers, Johannes Kepler University Linz, AT IP2-13 Verifiable Security Templates for Hardware Speaker: Bill Harrison, Oak Ridge National Laboratory, US Authors: William Harrison¹ and Gerard Allwein² ¹Oak Ridge National Laboratory, US; ²Naval Research Laboratory, US IP2-14 IFFSET: In-Field Fuzzing of Industrial Control Systems using System Emulation Speaker: Dimitrios Tychalas, New York University, US Authors: Dimitrios Tychalas¹ and Michail Maniatakos² ¹New York University, US; ²New York University Abu Dhabi, AE IP2-15 FANNet: Formal Analysis of Noise Tolerance, Training Bias and Input Sensitivity in Neural Networks Speaker: Mahum Naseer, TU Wien, AT Authors: Mahum Naseer¹, Mishal Fatima Minhas², Faiq Khalid¹, Muhammad Abdullah Hanif¹, Osman Hasan² and Muhammad Shafique¹ ¹TU Wien, AT; ²National University of Sciences and Technology, PK IP2-16 A Scalable Mixed Synthesis Framework for Heterogeneous Networks Speaker: Max Austin, University of Utah, US Authors: Max Austin¹, Scott Temple¹, Walter Lau Neto¹, Luca Amaru², Xifan Tang¹ and Pierre-Emmanuel Gaillardon¹ ¹University of Utah, US; ²Synopsys, US IP2-17 DiSCERN: Distilling Standard Cells for Emerging Reconfigurable Nanotechnologies Speaker: Shubham Rai, TU Dresden, DE Authors: Shubham Rai¹, Michael Raitza², Siva Satyendra Sahoo¹ and Akash Kumar¹ ¹TU Dresden, DE; ²TU Dresden and CfAED, DE IP2-18 A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length Speaker: Hyunjoon Kim, Nanyang Technological University, SG Authors: Qian Chen, Yuqi Su, Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim and Bongjin Kim, Nanyang Technological University, SG IP2-19 Towards Exploring the Potential of Alternative Quantum Computing Architectures Speaker: Arighna Deb, Kalinga Institute of Industrial Technology, IN Authors: Arighna Deb¹, Gerhard W. Dueck² and Robert Wille³ ¹Kalinga Institute of Industrial Technology, IN; ²University of New Brunswick, CA; ³Johannes Kepler University Linz, AT IP2-20 Accelerating Quantum Approximate Optimization Algorithm using Machine Learning Speaker: Swaroop Ghosh, Pennsylvania State University, US Authors: Mahabubul Alam, Abdullah Ash- Saki and Swaroop Ghosh, Pennsylvania State University, US 6.1 Special Day on "Embedded AI": Emerging Devices, Circuits and Systems Amphithéâtre Jean Prouve 1100 - 1230 Chair:Carlo Reita, CEA, FR Co-Chair:Bernabe Linares-Barranco, CSIC, ES This session focuses on the advantages and use of novel emerging nanotechnology devices and their use in designing circuits and systems for embedded AI hardware solutions. 1100 In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications Speaker: Damien Querlioz, University Paris-Saclay, FR Authors: Bogdan Penkovsky¹, Marc Bocquet², Tifenn Hirtzlin¹, Jacques-Olivier Klein¹, Etienne Nowak³, Elisa Vianello³, Jean-Michel Portal² and Damien Querlioz⁴ ¹Université Paris-Saclay, FR; ²Aix-Marseille University, FR; ³CEA-Leti, FR; ⁴Université Paris-Sud, FR 1122 Mixed-signal vector-by-matrix multiplier circuits based on 3D-NAND memories for neuromorphic computing Speaker: Dmitri Strukow, University of California, Santa Barbara, US Authors: Mohammad Bavandpour, Shubham Sahay, Mohammad Mahmoodi and Dmitri Strukov, University of California, Santa Barbara, US 1144 Modular RRAM based in-memory computing design for embedded AI Authors: Xinxin Wang, Qiwen Wang, Mohammed A. Zidan, Fan-Hsuan Meng, John Moon and Wei Lu, University of Michigan, US 1206 Neuromorphic computing: toward dynamical data processing Author: Fabian Alibart, CNRS, Lille, FR 6.2 Secure and fast memory and storage Chamrousse 1100 - 1230 Chair:Hao Yu, SUSTech, CN Co-Chair:Chengmo Yang, University of Delaware, US As memories become persistent, the design of traditional data structures such as trees and hash tables as well as filesystems should be revisited to cope with the challenges brought by new memory devices. In this context, the main focus of this session is on how to improve performance, security, and energy-efficiency of memory and storage. The specific techniques range from the designs of integrity trees and hash tables, the management of superpages in filesystems, data prefetch in solid state drives (SSDs), as well as energy-efficient carbon-nanotube cache design. 1100 An Efficient Persistency and Recovery Mechanism for SGX-style Integrity Tree in Secure NVM Speaker: Mengya Lei, Huazhong University of Science & Technology, CN Authors: Mengya Lei, Fang Wang, Dan Feng, Fan Li and Jie Xu, Huazhong University of Science & Technology, CN 1130 Revisiting Persistent Hash Table Design for Commercial Non-Volatile Memory Speaker: Kaixin Huang, Shanghai Jiao Tong University, CN Authors: Kaixin Huang, Yan Yan and Linpeng Huang, Shanghai Jiao Tong University, CN 1200 Optimizing Performance of Persistent Memory File Systems using Virtual Superpages Speaker: Chaoshu Yang, Chongqing University, CN Authors: Chaoshu Yang¹, Duo Liu¹, Runyu Zhang¹, Xianzhang Chen¹, Shun Nie¹, Qingfeng Zhuge¹ and Edwin H.-M Sha² ¹Chongqing University, CN; ²East China Normal University, CN 1215 Frequent Access Pattern-based Prefetching Inside of Solid-State Drives Speaker: Jianwei Liao, Southwest University of China, CN Authors: Xiaofei Xu¹, Zhigang Cai², Jianwei Liao² and Yutaka Ishikawa³ ¹Southwest University, CN; ²Southwest University of China, CN; ³RIKEN, Japan, JP IPs IP3-1 6.3 Special Session: Modern Logic Reasoning Methods for Functional ECO Autrans 1100 - 1230 Chair:Patrick Vuillod, Synopsys, US Co-Chair:Christoph Scholl, Albert-Ludwigs-University Freiburg, DE Functional Engineering Change Order (ECO) is the problem of incrementally updating an existing logic network after a (possibly late) change in the design specification. The problem requires (i) to identify a small portion of the network's logic to be changed and (ii) to automatically synthesize a patch to replace this portion and rectify the network's functional behavior. ECOs can be solved using the logical framework of quantified Boolean formulæ (QBF), where a logic query asks for the existence of a set of nodes and values at those nodes to rectify the logic network's output functions. The global nature of the problem, however, challenges scalability. Any internal node in the logic network is a potential location for rectification and any node in the logic network may be used to simplify the synthesized patch. Furthermore, off-the-self QBF algorithms do not allow a formulation of resource costs for reusing existing logic. 1100 Engineering Change Order for Combinational and Sequential Design Rectification Speaker: Jie-Hong Roland Jiang, National Taiwan University, TW Authors: Jie-Hong Roland Jiang¹, Victor Kravets² and NIAN-ZE LEE¹ ¹National Taiwan University, TW; ²IBM, US 1120 Exact DAG-Aware Rewriting Speaker: Heinz Riener, EPFL, CH Authors: Heinz Riener¹, Alan Mishchenko² and Mathias Soeken¹ ¹EPFL, CH; ²University of California, Berkeley, US 1140 Learning to Automate the Design Updates from Observed Engineering Changes in the Chip Development Cycle Speaker: Victor Kravets, IBM, US Authors: Victor Kravets¹, Jie-Hong Roland Jiang² and Heinz Riener³ ¹IBM, US; ²National Taiwan University, TW; ³EPFL, CH 1205 Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations Speaker: Masahiro Fujita, University of Tokyo, JP Authors: Masahiro Fujita, Yusuke Kimura, Xingming Le, Yukio Miyasaka and Amir Masoud Gharehbaghi, University of Tokyo, JP 6.4 Microarchitecture to the rescue of memory Stendhal 1100 - 1230 Chair:Olivier Sentieys, INRIA, FR Co-Chair:Jeronimo Castrillon, TU Dresden, DE This session discusses micro-architectural innovations across three different memory technologies, namely, caches, 3D-stacked DRAM and non-volatile. This includes exploiting several aspects of redundancy to maximize cache utilization through compression, as well as multicast in 3D-stacked high-speed memories for graph analytics, and a microarchitecture solution to unify persistency and encryption in non-volatile memories. 1100 Efficient Hardware-Assisted Crash Consistency in Encrypted Persistent Memory Speaker: Zhan Zhang, Huazhong University of Science & Technology, CN Authors: Zhan Zhang¹, Jianhui Yue², Xiaofei Liao¹ and Hai Jin¹ ¹Huazhong University of Science & Technology, CN; ²Michigan Technological University, US 1130 2DCC: Cache Compression in Two Dimensions Speaker: Amin Ghasemazar, University of British Columbia, CA Authors: Amin Ghasemazar¹, Mohammad Ewais², Prashant Nair¹ and Mieszko Lis¹ ¹University of British Columbia, CA; ²UofT, CA 1200 GraphVine: Exploiting Multicast for Scalable Graph Analytics Speaker: Leul Belayneh, University of Michigan, US Authors: Leul Belayneh and Valeria Bertacco, University of Michigan, US IPs IP3-2 6.5 Efficient Data Representations in Neural Networks Bayard 1100 - 1230 Chair:Brandon Reagen, Facebook and New York University, US Co-Chair:Sebastian Steinhorst, TU Munich, DE The large processing requirements of ML models strains the capabilities of low-power embedded systems. Addressing this challenge, the first presentation proposes a robust co-design to leverage stochastic computing for highly accurate and efficient inference. Next, a structural optimization is proposed to counter faults at low voltage levels. Then, authors present a method for sharing results in binarized CNNs to reduce computation. The session will conclude with a talk implementing binary networks on mobile GPUs. 1100 ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing Speaker: Puneet Gupta, University of California, Los Angeles, US Authors: Wojciech Romaszkan, Tianmu Li, Tristan Melton, Sudhakar Pamarti and Puneet Gupta, University of California, Los Angeles, US 1130 Accuracy Tolerant Neural Networks Under Aggressive Power Optimization Speaker: Yi-Wen Hung, National Tsing Hua University, TW Authors: Xiang-Xiu Wu¹, Yi-Wen Hung¹, Yung-Chih Chen² and Shih-Chieh Chang¹ ¹National Tsing Hua University, TW; ²Yuan Ze University, Taoyuan, Taiwan, TW 1200 A Convolutional Result Sharing Approach for Binarized Neural Network Inference Speaker: Chia-Chun Lin, National Tsing Hua University, TW Authors: Ya-Chun Chang¹, Chia-Chun Lin¹, Yi-Ting Lin¹, Yung-Chih Chen² and Chun-Yao Wang¹ ¹National Tsing Hua University, TW; ²Yuan Ze University, TW 1215 PhoneBit: Efficient GPU-Accelerated Binary Neural Network Inference Engine for Mobile Phones Speaker: Gang Chen, Sun Yat-sen University, CN Authors: Gang Chen¹, Shengyu He², Haitao Meng² and Kai Huang¹ ¹Sun Yat-sen University, CN; ²Northeastern University, CN IPs IP3-3, IP3-4, IP3-5 6.6 From DFT to Yield Optimization Lesdiguières 1100 - 1230 Chair:Maria Micheal, University of Cyprus, CY Co-Chair:Sanchez Ernesto, Politecnico di Torino, IT The session presents a variety of semiconductor test techniques, including a new design-for-testability scheme for FinFET SRAMs, a method to increase yield based on error-metric-independent signature analysis, and a synthesis method for fault-tolerant reconfigurable scan networks. 1100 A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs Speaker: Guilherme Cardoso Medeiros, TU Delft, NL Authors: Guilherme Cardoso Medeiros¹, Cemil Cem Gürsoy², Moritz Fieback¹, Lizhou Wu¹, Maksim Jenihhin², Mottaqiallah Taouil¹ and Said Hamdioui¹ ¹TU Delft, NL; ²Tallinn University of Technology, EE 1130 Synthesis of Fault-Tolerant Reconfigurable Scan Networks Speaker: Sebastian Brandhofer, University of Stuttgart, DE Authors: Sebastian Brandhofer, Michael Kochte and Hans-Joachim Wunderlich, University of Stuttgart, DE 1200 Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction Speaker: Chang Liu, Altran Deutschland, DE Authors: Chang Liu, Eric Schneider and Hans-Joachim Wunderlich, University of Stuttgart, DE 1215 Maximizing Yield for Approximate Integrated Circuits Speaker: Marcello Traiola, Université de Montpellier, FR Authors: Marcello Traiola¹, Arnaud Virazel¹, Patrick Girard², Mario Barbareschi³ and Alberto Bosio⁴ ¹LIRMM, FR; ²LIRMM / CNRS, FR; ³Università di Napoli Federico II, IT; ⁴Lyon Institute of Nanotechnology, FR IPs IP3-6 6.7 Safety and efficiency for smart automotive and energy systems Berlioz 1100 - 1230 Chair:Selma Saidi, TU Dortmund, DE Co-Chair:Donghwa Shin, Soongsil University, KR This session presents four papers dealing with various aspects of smart automotive and energy systems, including safety and efficiency of photovoltaic panels, deterministic execution behavior of adaptive automotive applications, efficient implementation of fail-operational automated vehicles, and efficient resource usage in networked automotive systems. 1100 A Diode-Aware Model of PV Modules from Datasheet Specifications Speaker: Sara Vinco, Politecnico di Torino, IT Authors: Sara Vinco, Yukai Chen, Enrico Macii and Massimo Poncino, Politecnico di Torino, IT 1130 Achieving Determinism in Adaptive AUTOSAR Speaker: Christian Menard, TU Dresden, DE Authors: Christian Menard¹, Andres Goens¹, Marten Lohstroh² and Jeronimo Castrillon¹ ¹TU Dresden, DE; ²University of California, Berkeley, US 1200 A Fail-safe Architecture for Automated Driving Speaker: Sebastian vom Dorff, DENSO Automotive Deutschland GmbH, DE Authors: Sebastian vom Dorff¹, Bert Böddeker², Maximilian Kneissl¹ and Martin Fränzle³ ¹DENSO Automotive Deutschland GmbH, DE; ²Autonomous Intelligent Driving GmbH, DE; ³Carl von Ossietzky University Oldenburg, DE 1215 Priority-Preserving Optimization of Status Quo ID-Assignments in Controller Area Network Speaker: Lea Schoenberger, TU Dortmund University, DE Authors: Sebastian Schwitalla¹, Lea Schönberger¹ and Jian-Jia Chen² ¹TU Dortmund University, DE; ²TU Dortmund, DE IPs IP3-7, IP3-8 7.0 LUNCHTIME KEYNOTE SESSION Amphitéâtre Jean Prouvé 1345 - 1420 Chair:Bernabe Linares-Barranco, CSIC, ES Co-Chair:Dmitri Strukov, University of California, Santa Barbara, US 1345 CEDA LUNCHEON ANNOUNCEMENT Author: David Atienza, EPFL, CH 1350 Leveraging Embedded Intelligence in Industry: Challenges and Opportunities Author: Jim Tung, MathWorks Fellow, US 7.1 Special Day on "Embedded AI": Industry AI chips Amphithéâtre Jean Prouve 1430 - 1600 Chair:Tobi Delbrück, ETH Zurich, CH Co-Chair:Bernabe Linares-Barranco, CSIC, ES This session on Industry AI chips will present examples of companies developing actual products for AI hardware solutions, a highly competitive and full of new challenges market. 1430 Opportunities for Analog Acceleration of Deep Learning with Phase Change Memory Authors: Pritish Narayanan, Geoffrey W. Burr, Stefano Ambrogio, Hsinyu Tsai, Charles Mackin, Katherine Spoon, An Chen, Alexander Friz and Andrea Fasoli, IBM Research, US 1452 Event-based AI for Automotive and IoT Speaker: Etienne Pero, Prophesee, FR Author: Etienne Perot, Prophesee, FR 1514 NeuronFlow: a neuromorphic processor architecture for Live AI applications Speaker: Orlando Moreira, GrAI Matter Labs, NL Authors: Orlando Moreira, Amirreza Yousefzadeh, Gokturk Cinserin, Rik-Jan Zwartenkot, Ajay Kapoor, Fabian Chersi, Peng Qiao, Peter Kievits, Mina Khoei, Louis Rouillard, Ashoka Visweswara and Jonathan Tapson, GrAI Matter Labs, NL 1536 Speck - sub-mW smart vision sensor for mobile IoT applications Author: Ning Qiao, aiCTX, CH 7.2 Reconfigurable Systems and Architectures Chamrousse 1430 - 1600 Chair:Christian Pilato, Politecnico di Milano, IT Co-Chair:Philippe Coussy, University Bretagne Sud / Lab-STICC, FR Reconfigurable technologies are evolving at the device, architecture, and system levels, from embedded computation to server-based accelerator integration. In this session we explore ideas at these levels, discussing architectural features for power optimisation of CGRAs, a framework for integrating FPGA accelerators in serverless environments, and placement strategies on alternative FPGA device technologies. 1430 A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs Speaker: Ankita Nayak, Stanford University, US Authors: Ankita Nayak, Keyi Zhang, Raj Setaluri, Alex Carsello, Makai Mann, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz and Priyanka Raina, Stanford University, US 1500 BlastFunction: an FPGA-as-a-Service system for Accelerated Serverless Computing Speaker: Rolando Brondolin, Politecnico di Milano, IT Authors: Marco Bacis, Rolando Brondolin and Marco D. Santambrogio, Politecnico di Milano, IT 1530 Energy-aware Placement for SRAM-NVM Hybrid FPGAs Speaker: Seongsik Park, Seoul National University, KR Authors: Seongsik Park, Jongwan Kim and Sungroh Yoon, Seoul National University, KR 7.3 Special Session: Realizing Quantum Algorithms on Real Quantum Computing Devices Autrans 1430 - 1600 Chair:Eduard Alarcon, UPC BarcelonaTech, ES Co-Chair:Swaroop Ghosh, Pennsylvania State University, US Quantum computing is currently moving from an academic idea to a practical reality. Quantum computing in the cloud is already available and allows users from all over the world to develop and execute real quantum algorithms. However, companies which are heavily investing in this new technology such as Google, IBM, Rigetti, and Intel follow different technological approaches. This led to a situation where we have substantially different quantum computing devices available thus far. Because of that, various methods for realizing the intended quantum functionality to a respectively given quantum computing device are available. This special session provides an introduction and overview into this domain and comprehensively describes corresponding methods (also referred to as compilers, mappers, synthesizers, or routers). By this, attendees will be provided with a detailed understanding on how to use quantum computers in general and dedicated quantum computing devices in particular. The special session will include speakers from both, academia and industry, and will cover the most relevant quantum computing devices such as provided by IBM, Intel, etc. 1430 Running Quantum Algorithms on Resource-Constrained Quantum Devices Author: Carmen G. Almudever, TU Delft, NL 1500 Realizing Quantum Circuits on IBM Q Devices Author: Robert Wille, Johannes Kepler University Linz, AT 1530 Every Device is (almost) Equal Before the Compiler Author: Gian Giacomo Guerreschi, Intel Corporation, US 7.4 Simulation and verification: where real issues meet scientific innovation Stendhal 1430 - 1600 Chair:Avi Ziv, IBM, IL Co-Chair:Graziano Pravadelli, Università di Verona, IT This session presents recent concerns and innovative solutions in verification and simulation, covering topics ranging from partial verification to lazy event prediction, till signal name disambiguation.They tackle these challenges by reducing complexity, exploiting GPUs, and using similarity-learning techniques. 1430 Verification Runtime Analysis: Get the Most Out of Partial Verification Authors: Martin Ring¹, Fritjof Bornbebusch¹, Christoph Lüth², Robert Wille³ and Rolf Drechsler² ¹DFKI, DE; ²University of Bremen / DFKI, DE; ³Johannes Kepler University Linz, AT 1500 GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling Speaker: Eric Schneider, University of Stuttgart, DE Authors: Eric Schneider and Hans-Joachim Wunderlich, University of Stuttgart, DE 1530 Lazy Event Prediction using Deﬁning Trees and Schedule Bypass for Out-of-Order PDES Speaker: Rainer Doemer, University of California, Irvine, US Authors: Daniel Mendoza, Zhongqi Cheng, Emad Arasteh and Rainer Doemer, University of California, Irvine, US 1545 Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification Speaker: Yi-An Chen, National Chiao Tung University, TW Authors: Yi-An Chen¹, Gung-Yu Pan², Che-Hua Shih², Yen-Chin Liao¹, Chia-Chih Yen² and Hsie-Chia Chang¹ ¹National Chiao Tung University, TW; ²Synopsys, TW IPs IP3-9, IP3-10 7.5 Runtime support for multi/many cores Bayard 1430 - 1600 Chair:Sara Vinco, Politecnico di Torino, IT Co-Chair:Jeronimo Castrillon, TU Dresden, DE In the era of heterogenous embedded systems, the diverse nature of computing elements pushes more than ever the need for smart runtime systems to be able to deal with resource management, multi-application mapping, task parallelism, and non-functional constraints. This session tackles these issues with solutions that span from resource-aware software architectures to novel runtime systems optimizing memory and energy consumption. 1430 Resource-Aware MapReduce Runtime for Multi/Many-core Architectures Speaker: Konstantinos Iliakis, MicroLab, ECE, NTUA, GR Authors: Konstantinos Iliakis¹, Sotirios Xydis¹ and Dimitrios Soudris² ¹National TU Athens, GR; ²National Technical University of Athens, GR 1500 Towards a Qualifiable OpenMP Framework for Embedded Systems Speaker: Adrian Munera Sanchez, BSC, ES Authors: Adrián Munera Sánchez, Sara Royuela and Eduardo Quiñones, BSC, ES 1530 Energy-efficient Runtime Resource Management for Adaptable Multi-application Mapping Speaker: Robert Khasanov, TU Dresden, DE Authors: Robert Khasanov and Jeronimo Castrillon, TU Dresden, DE IPs IP3-11 7.6 Attacks on Hardware Architectures Lesdiguières 1430 - 1600 Chair:Johanna Sepúlveda, Airbus Defence and Space, DE Co-Chair:Jean-Luc Danger, Télécom ParisTech, FR Hardware architectures are under the continuous threat of all types of attacks. This session covers attacks based on side-channel leakage and the exploitation of vulnerabilities at the micro-architectural and circuit level. 1430 Sweeping for Leakage in Masked Circuit Layouts Speaker: Danilo Šijačić, IMEC / KU Leuven, BE Authors: Danilo Šijačić, Josep Balasch and Ingrid Verbauwhede, KU Leuven, BE 1500 Increased reproducibility and comparability of data leak evaluations using ExOT Speaker: Philipp Miedl, ETH Zürich, CH Authors: Philipp Miedl¹, Bruno Klopott² and Lothar Thiele¹ ¹ETH Zurich, CH; ²ETH Zürich, CH 1515 GhostBusters: Mitigating Spectre Attacks on a DBT-Based Processor Speaker and Author: Simon Rokicki, Irisa, FR 1530 Dynamic Faults based Hardware Trojan Design in STT-MRAM Speaker: Sarath Mohanachandran Nair, Karlsruhe Institute of Technology, DE Authors: Sarath Mohanachandran Nair¹, Rajendra Bishnoi², Arunkumar Vijayan¹ and Mehdi Tahoori¹ ¹Karlsruhe Institute of Technology, DE; ²TU Delft, NL 1545 Oracle-based Logic Locking Attacks: Protect the Oracle Not Only the Netlist Speaker: Emmanouil Kalligeros, University of the Aegean, GR Authors: Emmanouil Kalligeros, Nikolaos Karousos and Irene Karybali, University of the Aegean, GR IPs IP3-12 7.7 Self-Adaptive and Learning Systems Berlioz 1430 - 1600 Chair:Gilles Sassatelli, Université de Montpellier, FR Co-Chair:Rishad Shafik, University of Newcastle, GB Recent advances in machine learning have pushed the boundaries of what is possible in self-adaptive and learning systems. This session pushes the state of art in runtime power and performance trade-offs for deep neural networks and self-optimizing embedded systems. 1430 AnytimeNet: Controlling Time-Quality Tradeoffs in Deep Neural Network Architectures Speaker: Jung-Eun Kim, Yale University, US Authors: Jung-Eun Kim¹, Richard Bradford² and Zhong Shao¹ ¹Yale University, US; ²Collins Aerospace, US 1500 AntiDote: Attention-based Dynamic Optimization for Neural Network Runtime Efficiency Speaker: Xiang Chen, George Mason University, US Authors: Fuxun Yu¹, Chenchen Liu², Di Wang³, Yanzhi Wang¹ and Xiang Chen¹ ¹George Mason University, US; ²University of Maryland, Baltimore County, US; ³Microsoft, US 1530 Using Learning Classifier Systems for the DSE of Adaptive Embedded Systems Speaker: Fedor Smirnov, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE Authors: Fedor Smirnov, Behnaz Pourmohseni and Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE IPs IP3-13, IP3-14 IP3 Interactive Presentations Poster Area 1600 - 1630 Interactive Presentations run simultaneously during a 30-minute slot. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session IP3-1 CNT-Cache: an Energy-efficient Carbon Nanotube Cache with Adaptive Encoding Speaker: Kexin Chu, School of Electronic Science & Applied Physics Hefei University of Technology Anhui,China, CN Authors: Dawen Xu¹, Kexin Chu¹, Cheng Liu², Ying Wang², Lei Zhang² and Huawei Li² ¹School of Electronic Science & Applied Physics Hefei University of Technology Anhui, CN; ²Chinese Academy of Sciences, CN IP3-2 Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading Speaker: Antonio Scheneider Beck, Universidade Federal do Rio Grande do Sul, BR Authors: Jeckson Dellagostin Souza¹, Madhavan Manivannan², Miquel Pericas² and Antonio Carlos Schneider Beck¹ ¹Universidade Federal do Rio Grande do Sul, BR; ²Chalmers, SE IP3-3 Hardware Acceleration of CNN with One-Hot Quantization of Weights and Activations Speaker: Gang Li, Chinese Academy of Sciences, CN Authors: Gang Li, Peisong Wang, Zejian Liu, Cong Leng and Jian Cheng, Chinese Academy of Sciences, CN IP3-4 BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems Speaker: Luca Stornaiuolo, Politecnico di Milano, IT Authors: Giorgia Fiscaletti, Marco Speziali, Luca Stornaiuolo, Marco D. Santambrogio and Donatella Sciuto, Politecnico di Milano, IT IP3-5 L2L: A Highly Accurate Log_2_Lead Quantization of Pre-trained Neural Networks Speaker: Salim Ullah, TU Dresden, DE Authors: Salim Ullah¹, Siddharth Gupta², Kapil Ahuja², Aruna Tiwari² and Akash Kumar¹ ¹TU Dresden, DE; ²IIT Indore, IN IP3-6 Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA Speaker: Ryutaro Doi, Osaka University, JP Authors: Ryutaro DOI¹, Xu Bai², Toshitsugu Sakamoto² and Masanori Hashimoto¹ ¹Osaka University, JP; ²NEC Corporation, JP IP3-7 Applying Reservation-based Scheduling to a µC-based Hypervisor: An industrial case study Speaker: Dirk Ziegenbein, Robert Bosch GmbH, DE Authors: Dakshina Dasari¹, Paul Austin², Michael Pressler¹, Arne Hamann¹ and Dirk Ziegenbein¹ ¹Robert Bosch GmbH, DE; ²ETAS GmbH, GB IP3-8 Real-Time Energy Monitoring in IoT-enabled Mobile Devices Speaker: Nitin Shivaraman, TUMCREATE, SG Authors: Nitin Shivaraman¹, Seima Suriyasekaran¹, Zhiwei Liu², Saravanan Ramanathan¹, Arvind Easwaran² and Sebastian Steinhorst³ ¹TUMCREATE, SG; ²Nanyang Technological University, SG; ³TU Munich, DE IP3-9 Towards Specification and Testing of RISC-V ISA Compliance Speaker: Vladimir Herdt, University of Bremen, DE Authors: Vladimir Herdt¹, Daniel Grosse² and Rolf Drechsler² ¹University of Bremen, DE; ²University of Bremen / DFKI, DE IP3-10 Post-Silicon Validation of the IBM POWER9 Processor Speaker: Hillel Mendelson, IBM, IL Authors: Tom Kolan¹, Hillel Mendelson¹, Vitali Sokhin¹, Kevin Reick², Elena Tsanko² and Gregory Wetli² ¹IBM Research, IL; ²IBM Systems, US IP3-11 On the Task Mapping and Scheduling for DAG-based Embedded Vision Applications on Heterogeneous Multi/Many-core Architectures Speaker: Nicola Bombieri, Università di Verona, IT Authors: Stefano Aldegheri¹, Nicola Bombieri¹ and Hiren Patel² ¹Università di Verona, IT; ²University of Waterloo, CA IP3-12 Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks? Speaker: Ognjen Glamocanin, EPFL, CH Authors: Ognjen Glamocanin¹, Louis Coulon¹, Francesco Regazzoni² and Mirjana Stojilovic¹ ¹EPFL, CH; ²ALaRI, CH IP3-13 Efficient Training on Edge Devices Using Online Quantization Speaker: Michael Ostertag, University of California, San Diego, US Authors: Michael Ostertag¹, Sarah Al-Doweesh² and Tajana Rosing¹ ¹University of California, San Diego, US; ²King Abdulaziz City of Science and Technology, SA IP3-14 Multi-Agent Actor-Critic Method for Joint Duty-Cycle and Transmission Power Control Speaker: Sota Sawaguchi, CEA-Leti, FR Authors: Sota Sawaguchi¹, Jean-Frédéric Christmann², Anca Molnos², Carolynn Bernier² and Suzanne Lesecq² ¹CEA, FR; ²CEA-Leti, FR 8.1 Special Day on "Embedded AI": Neuromorphic chips and systems Amphithéâtre Jean Prouve 1700 - 1830 Chair:Wei Lu, University of Michigan, US Co-Chair:Bernabe Linares-Barranco, CSIC, ES Within the global field of AI, there is a subfield that focuses on exploiting neuroscience knowledge for artificial intelligent hardware systems. This is the neuromorphic engineering field. This session presents some examples of AI research focusing on this AI subfield. 1700 SpiNNaker2 : A Platform for Bio-Inspired Artificial Intelligence and Brain Simulation Authors: Bernhard Vogginger, Christian Mayr, Sebastian Höppner, Johannes Partzsch and Steve Furber, TU Dresden, DE 1730 An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays Authors: Shruti R. Kulkarni, Shihui Yin, Jae-sun Seo and Bipin Rajendran, New Jersey Institute of Technology, US 1800 Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories Speaker: Shimeng Yu, Georgia Tech, US Authors: Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang and Shimeng Yu, Georgia Tech, US 8.2 We are all hackers: design and detection of security attacks Chamrousse 1700 - 1830 Chair:Regazzoni Francesco, ALaRI, CH Co-Chair:Daniel Grosse, University of Bremen, DE This session deals with hardware trojans and vulnerabilities, proposing detection techniques and design paradigms to model attacks. It describes attacks by leveraging the exclusive characteristics of microfluidic devices and malicious usage of energy management. As for defenses, an automated test generation approach for hardware trojan detection using delay-based side-channel analysis is also presented. 1700 Automated Test Generation for Trojan Detection using Delay-based Side Channel Analysis Speaker: Prabhat Mishra, University of Florida, US Authors: Yangdi Lyu and Prabhat Mishra, University of Florida, US 1730 Microfluidic Trojan Design in Flow-based Biochips Speaker: Shayan Mohammed, New York University, US Authors: Shayan Mohammed¹, Sukanta Bhattacharjee², Yong-Ak Song², Krishnendu Chakrabarty³ and Ramesh Karri¹ ¹New York University, US; ²New York University Abu Dhabi, AE; ³Duke University, US 1800 Towards Malicious Exploitation of Energy Management Mechanisms Speaker: Safouane Noubir, École Polytechnique de l'Université de Nantes, FR Authors: Safouane Noubir, Maria Mendez Real and Sebastien Pillement, École Polytechnique de l'Université de Nantes, FR IPs IP4-1, IP4-2 8.3 Optimizing System-Level Design for Machine Learning Autrans 1700 - 1830 Chair:Luciano Lavagno, Politecnico di Torino, IT Co-Chair:Yuko Hara-Azumi, Tokyo Institute of Technology, JP In the last years, the use of ML techniques, as deep neural networks, have become a trend in system-level design, either to help the flow finding promising solutions or to deploy ML-based applications. This session presents various approaches to optimize several aspects of system-level design, like the mapping of applications on heterogeneous platforms, the inference of CNNs or the file-system usage. 1700 ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning Speaker: Davide Giri, Columbia University, US Authors: Davide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani and Luca Carloni, Columbia University, US 1730 Probabilistic Sequential Multi-Objective Optimization of Convolutional Neural Networks Speaker: Zixuan Yin, McGill University, CA Authors: Zixuan Yin, Warren Gross and Brett Meyer, McGill University, CA 1800 ARS: Reducing F2FS Fragmentation for Smartphones using Decision Trees Speaker: Lihua Yang, Huazhong University of Science & Technology, CN Authors: Lihua Yang, Fang Wang, Zhipeng Tan, Dan Feng, Jiaxing Qian and Shiyun Tu, Huazhong University of Science & Technology, CN IPs IP4-3, IP4-4 8.4 Architectural and Circuit Techniques toward Energy-efficient Computing Stendhal 1700 - 1830 Chair:Sara Vinco, Politecnico di Torino, IT Co-Chair:Davide Rossi, Università di Bologna, IT The session discusses low-power design techniques at the architectural as well as the circuit level. The presented works span from new solutions for conventional computing, such as ultra-low power tunable precision architectures and speculative SRAM arrays, to emerging paradigms, like spiking neural networks and stochastic computing. 1700 TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE Speaker: Rohit Prasad, Lab-SICC, UBS, France & DEI, UniBo, Italy, FR Authors: Rohit Prasad¹, Satyajit Das², Kevin Martin³, Giuseppe Tagliavini⁴, Philippe Coussy⁵, Luca Benini⁶ and Davide Rossi⁴ ¹Université Bretagne Sud, FR; ²IIT Palakkad, IN; ³University Bretagne Sud, FR; ⁴Università di Bologna, IT; ⁵Université Bretagne Sud / Lab-STICC, FR; ⁶Università di Bologna and ETH Zurich, IT 1730 Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM Speaker: Shan Shen, Southeast University, CN Authors: Shan Shen, Tianxiang Shao, Ming Ling, Jun Yang and Longxing Shi, Southeast University, CN 1800 Solving Constraint Satisfaction Problems Using the Loihi Spiking Neuromorphic Processor Speaker: Chris Yakopcic, University of Dayton, US Authors: Chris Yakopcic¹, Nayim Rahman¹, Tanvir Atahary¹, Tarek M. Taha¹ and Scott Douglass² ¹University of Dayton, US; ²Air Force Research Laboratory, US 1815 Accurate Power Density Map Estimation for Commercial Multi-Core Microprocessors Speaker: Sheldon Tan, University of California, Riverside, US Authors: Jinwei Zhang, Sheriff Sadiqbatcha, Wentian Jin and Sheldon Tan, University of California, Riverside, US IPs IP4-5, IP4-6 8.5 CNN Dataflow Optimizations Bayard 1700 - 1830 Chair:Mario Casu, Politecnico di Torino, IT Co-Chair:Wanli Chang, University of York, GB This session focuses on efficient dataflow approaches for reducing CNN runtime on embedded hardware platforms. The papers to be presented demonstrate techniques for enhancing parallelism to improve performance of CNNs, leverage output prediction to reduce the runtime for time-critical embedded applications during inference, and presents a Keras-based DNN framework for real-time cyber physical systems. 1700 Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling Speaker: Yesung Kang, Pohang University of Science and Technology, KR Authors: Yesung Kang¹, Yoonho Park¹, Sunghoon Kim¹, Eunji Kwon¹, Taeho Lim², Mingyu Woo³, Sangyun Oh⁴ and Seokhyeong Kang¹ ¹Pohang University of Science and Technology, KR; ²SK Hynix, KR; ³University of California, San Diego, US; ⁴UNIST, KR 1730 DCCNN: Computational Flow Redefinition for Efficient CNN Inference through Model Structural Decoupling Speaker: Xiang Chen, George Mason University, US Authors: Fuxun Yu¹, Zhuwei Qin¹, Di Wang², Ping Xu¹, Chenchen Liu³, Zhi Tian¹ and Xiang Chen¹ ¹George Mason University, US; ²Microsoft, US; ³University of Maryland, Baltimore County, US 1800 ABC: Abstract prediction Before Concreteness Speaker: Jung-Eun Kim, Yale University, US Authors: Jung-Eun Kim¹, Richard Bradford², Man-Ki Yoon¹ and Zhong Shao¹ ¹Yale University, US; ²Collins Aerospace, US 1815 A compositional approach using Keras for neural networks in real-time systems Speaker: Xin Yang, University of Auckland, NZ Authors: Xin Yang, Partha Roop, Hammond Pearce and Jin Woo Ro, University of Auckland, NZ IPs IP4-7, IP4-8 8.6 Microarchitecture-level reliability analysis and protection Lesdiguières 1700 - 1830 Chair:Michail Maniatakos, New York University Abu Dhabi, UA Co-Chair:Alessandro Savino, Politecnico di Torino, IT Reliability analysis and protection at the microarchitecture level is of paramount importance to speed-up the design face of any computing system. On the analysis side, this session starts presenting a reverse-order ACE (Architecturally Correct Execution) analysis that is more accurate than original ACE proposals, then moving to an instruction level analysis based on a genetic-algorithm able to improve program resiliency to errors. Finally, on the protection side, the session presents a low-cost ECC plus approximation mechanism for GPU register files. 1700 rACE: Reverse-Order Processor Reliability Analysis Authors: Athanasios Chatzidimitriou and Dimitris Gizopoulos, University of Athens, GR 1730 DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search Speaker: Ioannis Tsiokanos, Queen's University Belfast, GB Authors: Ioannis Tsiokanos¹, Lev Mukhanov¹, Giorgis Georgakoudis², Dimitrios S. Nikolopoulos³ and Georgios Karakonstantis¹ ¹Queen's University Belfast, GB; ²Lawrence Livermore National Laboratory, US; ³Virginia Tech, US 1800 LAD-ECC: Energy-Efficient ECC Mechanism for GPGPUs Register File Speaker: Hengshan Yue, Jilin University, CN Authors: Xiaohui Wei, Hengshan Yue and Jingweijia Tan, Jilin University, CN IPs IP4-9 8.7 Physical Design and Analysis Berlioz 1700 - 1830 Chair:Vasilis Pavlidis, The University of Manchester, GB Co-Chair:L. Miguel Silveira, INESC ID / IST, U Lisboa, PT This session deals with problems in extraction, DRC hotspots, IR drop, routing and other relevant issues in physical design and analysis. The common trend between all papers is efficiency improvement while maintaining accuracy. Floating random walk extraction is performed to handle non-stratified dielectrics with on-the-fly computations. Also, serial equivalence can be guaranteed in FPGA routing by exploring parallelism. A legalization flow is proposed for double-patterning aware feature alignment. Finally, machine-learning based DRC hotspot prediction is enhanced with explainability. 1700 Floating Random Walk Based Capacitance Solver for VLSI Structures with Non-Stratified Dielectrics Speaker: Ming Yang, Tsinghua University, CN Authors: Mingye Song, Ming Yang and Wenjian Yu, Tsinghua University, CN 1730 Towards Serial-Equivalent Multi-Core Parallel Routing for FPGAs Speaker: Minghua Shen, Sun Yat-sen University, CN Authors: Minghua Shen and Nong Xiao, Sun Yat-sen University, CN 1800 Self-Aligned Double-Patterning Aware Legalization Speaker: Hua Xiang, IBM Research, US Authors: Hua Xiang¹, Gi-Joon Nam¹, Gustavo Tellez², Shyam Ramji² and Xiaoqing Xu³ ¹IBM Research, US; ²IBM Thomas J. Watson Research Center, US; ³University of Texas at Austin, US 1815 Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree Explainer Speaker: Wei Zeng, University of Wisconsin-Madison, US Authors: Wei Zeng¹, Azadeh Davoodi¹ and Rasit Onur Topaloglu² ¹University of Wisconsin - Madison, US; ²IBM, US IPs IP4-10, IP4-11 9.1 Special Day on "Silicon Photonics": Advancements on Silicon Photonics Amphithéâtre Jean Prouve 0830 - 1000 Chair:Gabriela Nicolescu, Polytechnique Montréal, CA Co-Chair:Luca Ramini, Hewlett Packard Labs, US 0830 System Study of Silicon Photohotonicnics Modulator in Short Reach Gridless Coherent Networks Speaker: Sadok Aouini, Ciena Corporation, CA Authors: Sadok Aouini¹, Ahmad Abdo¹, Xueyang Li², Md Samiul Alam², Mahdi Parvizi¹, Claude D'Amours³ and David V. Plant² ¹Ciena Corporation, CA; ²McGill University, CA; ³University of Ottawa, CA 0900 Fully Integrated Photonic Circuits on Silicon by means of III-V/Silicon Bonding Author: Florian Denis-le Coarer, SCINTIL Photonics, US 0930 III-V/Silicon hybrid lasers integration on CMOS-compatible 200mm and 300mm platforms Speaker: Karim Hassan, CEA-Leti, FR Authors: Karim Hassan¹, Szelag Bertrand¹, Laetitia Adelmini¹, Cecilia Dupre¹, Elodie Ghegin², Philippe Rodriguez¹, Fabrice Nemouchi¹, Pierre Brianceau¹, Antoine Schembri¹, David Carrara³, Pierrick Cavalie³, Florent Franchin³, Marie-Christine Roure¹, Loic Sanchez¹, Christophe Jany¹ and Ségolène Olivier¹ ¹CEA-Leti, FR; ²STMicroelectronics, FR; ³Almae Technologies, FR 9.2 Autonomous Systems Design Initiative: Architectures and Frameworks for Autonomous Systems Chamrousse 0830 - 1000 Chair:Selma Saidi, TU Dortmund, DE Co-Chair:Rolf Ernst, TU Braunschweig, DE 0830 DeepRacing: A framework for Agile Autonomy Speaker: Trent Weiss, University of Virginia, US Authors: Trent Weiss and Madhur Behl, University of Virginia, US 0900 Fail-Operational Automotive Software Design Using Agent-Based Graceful Degradation Speaker: Philipp Weiss, TU Munich, DE Authors: Philipp Weiss¹, Andreas Weichslgartner², Felix Reimann² and Sebastian Steinhorst¹ ¹TU Munich, DE; ²Audi Electronics Venture GmbH, DE 0930 A Distributed Safety Mechanism using Middleware and Hypervisors for Autonomous Vehicles Speaker: Pieter van der Perk, NXP Semiconductors, NL Authors: Tjerk Bijlsma¹, Andrii Buriachevskyi², Alessandro Frigerio³, Yuting Fu², Kees Goossens⁴, Ali Osman Örs², Pieter J. van der Perk², Andrei Terechko² and Bart Vermeulen² ¹TNO, NL; ²NXP Semiconductors, NL; ³Eindhoven University of Technology, NL; ⁴Eindhoven university of technology, NL 9.3 Special Session: In memory computing for edge AI Autrans 0830 - 1000 Chair:Maha Kooli, CEA-Leti, FR Co-Chair:Alexandre Levisse, EPFL, CH In-Memory Computing (IMC) represents new computing paradigm where computation happens at data location. Within the landscape of IMC approaches, non-von Neumann architectures seek to minimize data movement associated with computing. Artificial intelligence applications are one of the most promising use case of IMC since they are both compute- and memory-intensive. Running such applications on edge devices offers significant save of energy consumption and high-speed acceleration. This special session proposes to take the attendees along a journey through IMC solutions for Edge AI. This session will cover four different viewpoints of IMC for Edge AI with four talks: (i) Enabling flexible electronics very-Edge AI with IMC, (ii) design automation methodology for computational SRAM for energy efficient SIMD operations, (iii) circuit/architecture/application multiscale design and optimization methodologies for IMC architectures, and (iv) device circuit and architecture optimizations to enable PCM-based deep learning accelerators. The speakers come from three different continents (Asia, Europe, America) and four different countries (Singapore, France, USA, Switzerland). Two speakers are affiliated to academic institutes; one to industry; and one to an institute of technological research center. We strongly believe that the topic and especially selected talks are extremely hot topics in the community and will attract various people from different countries and affiliations, from both academia and industry. Furthermore, thanks to its cross layer nature, we believe that this session is tailored to touch a wide range of experts from device and circuit community up to system and application design community. We also believe that highlighting and discussing such design methodologies is a key point for high quality and high impact research. Following up previous occurrences and success of IMC-oriented sessions and panels in DAC2019 as well as in ISLPED2019, we believe that this topic is extremely hot in the community and will trigger fruitful interactions and, we hope, collaboration among the community. We thereby expect more than 60 attendees for this session. This session will be the object of two scientific papers that will be integrated with DATE proceedings in case of acceptance. 0830 Fledge: Flexible edge platforms enabled by in-memory computing Speaker: Kamalika Datta, Nanyang Technological University, SG Authors: Kamalika Datta¹, Umesh Chand², Arko Dutt¹, Devendra Singh², Aaron Thean² and Mohamed M. Sabry¹ ¹Nanyang Technological University, SG; ²National University of Singapore, SG 0850 Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing Speaker: Maha Kooli, CEA-Leti, FR Authors: Jean-Philippe Noel¹, Valentin Egloff¹, Maha Kooli¹, Roman Gauchi¹, Jean-Michel Portal², Henri-Pierre Charles¹, Pascal Vivet¹ and Bastien Giraud¹ ¹CEA-Leti, FR; ²Aix-Marseille University, FR 0910 Demonstrating in-Cache Computing Thanks to Cross-Layer Design Optimizations Authors: Marco Rios, William Simon, Alexandre Levisse, Marina Zapater and David Atienza, EPFL, CH 0935 Device, circuit and software innovations to make deep learning with analog memory a reality Authors: Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Katie Spoon and Geoffrey W. Burr, IBM Research, US 9.4 Efficient DNN design with Approximate Computing. Stendhal 0830 - 1000 Chair:Daniel Menard, INSA Rennes, FR Co-Chair:Seokhyeong Kang, Pohang University of Science and Technology, KR Deep Neural Networks (DNN) are widely used in numerous domains. Cross-layer DNN approximation requires efficient simulation framework. The GPU-accelerated simulation framework, ProxSim, supports DNN inference and retraining for approximate hardware. A significant amount of energy is consumed during the training process due to excessive memory accesses. The precision-controlled memory systems, dedicated for GPUs, allow flexible management of approximation. New generation of networks, like Capsule Networks, provide better learning capabilities but at the expense of high complexity. ReD-CaNe methodology analyzes resilience through an error injection and approximates them. 0830 ProxSim: Simulation Framework for Cross-Layer Approximate DNN Optimization Speaker: Cecilia Eugenia De la Parra Aparicio, Robert Bosch GmbH, DE Authors: Cecilia De la Parra¹, Andre Guntoro¹ and Akash Kumar² ¹Robert Bosch GmbH, DE; ²TU Dresden, DE 0900 PCM: Precision-Controlled Memory System for Energy Efficient Deep Neural Network Training Speaker: Boyeal Kim, Seoul National University, KR Authors: Boyeal Kim¹, SangHyun Lee¹, Hyun Kim², Duy-Thanh Nguyen³, Minh-Son Le³, Ik Joon Chang³, Dohun Kwon⁴, Jin Hyeok Yoo⁵, Jun Won Choi⁴ and Hyuk-Jae Lee¹ ¹Seoul National University, KR; ²Seoul National University of Science and Technology, KR; ³Kyung Hee University, KR; ⁴Hanyang University, KR; ⁵Hanyang university, KR 0930 ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under Approximations Speaker: Alberto Marchisio, TU Wien (TU Wien), AT Authors: Alberto Marchisio¹, Vojtech Mrazek², Muhammad Abdullah Hanif³ and Muhammad Shafique³ ¹TU Wien (TU Wien), AT; ²Brno University of Technology, CZ; ³TU Wien, AT IPs IP4-12, IP4-13 9.5 Emerging memory devices Bayard 0830 - 1000 Chair:Alexandere Levisse, EPFL, CH Co-Chair:Marco Vacca, Politecnico di Torino, IT The development of future memories is driven by new devices, studied to overcome the limitations of traditional memories. Among these devices STT magnetic RAMs play a fundamental role, due to their excellent performance coupled with long endurance and non-volatility. What are the issues that these memories face? How can we solve them and make them ready for a successfull commercial development? And if, by changing perspective, emerging devices are used to improve existing memories like SRAM? These are some of the questions that this section aim to answer. 0830 Impact of Magnetic Coupling and Density on STT-MRAM Performance Speaker: Lizhou Wu, TU Delft, NL Authors: Lizhou Wu¹, Siddharth Rao², Mottaqiallah Taouil¹, Erik Jan Marinissen², Gouri Sankar Kar² and Said Hamdioui¹ ¹TU Delft, NL; ²IMEC, BE 0900 High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques Speaker: Wang Kang, Beihang University, CN Authors: Haotian Wang¹, Wang Kang¹, Liuyang Zhang¹, He Zhang¹, Brajesh Kumar Kaushik² and Weisheng Zhao¹ ¹Beihang University, CN; ²IIT Roorkee, IN 0930 Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay Devices Speaker: Hongtao Zhong, Tsinghua University, CN Authors: Hongtao Zhong, Mingyang Gu, Juejian Wu, Huazhong Yang and Xueqing Li, Tsinghua University, CN IPs IP4-14, IP4-15 9.6 Intelligent Dependable Systems Lesdiguières 0830 - 1000 Chair:Rishad Shafik, Newcastle University, GB This session spans from dependability approaches for multicore systems realized as SoCs for intelligent reliability management and on-line software-based self-test, to error resilient AI systems where the AI system is re-designed to tolerate critical faults or is used for error detection purposes. 0830 Thermal-Cycling-aware Dynamic Reliability Management in Many-Core System-on-Chip Speaker: Mohammad-Hashem Haghbayan, University of Turku, FI Authors: Mohammad-Hashem Haghbayan¹, Antonio Miele², Zhuo Zou³, Hannu Tenhunen¹ and Juha Plosila¹ ¹University of Turku, FI; ²Politecnico di Milano, IT; ³Nanjing University of Science and Technology, CN 0900 Deterministic Cache-based Execution of On-line Self-Test Routines in Multi-core Automotive System-on-Chips Speaker: Andrea Floridia, Politecnico di Torino, IT Authors: Andrea Floridia¹, Tzamn Melendez Carmona¹, Davide Piumatti¹, Annachiara Ruospo¹, Ernesto Sanchez¹, Sergio De Luca², Rosario Martorana² and Mose Alessandro Pernice² ¹Politecnico di Torino, IT; ²STMicroelectronics, IT 0930 FT-ClipAct: Resilience Analysis of Deep Neural Networks and Improving their Fault Tolerance using Clipped Activation Authors: Le-Ha Hoang¹, Muhammad Abdullah Hanif² and Muhammad Shafique² ¹TU Wien (TU Wien), AT; ²TU Wien, AT IPs IP4-16 9.7 Diverse Applications of Emerging Technologies Berlioz 0830 - 1000 Chair:Pavlidis Vasilis, The University of Manchester, GB Co-Chair:Bing Li, TU Munich, DE This session examines a diverse set of applications for emerging technologies. Papers consider the use of Q-learning to perform more efficient backups in non-volatile processors, the use of emerging technologies to mitigate hardware side-channels, time-sequence-based classification that rise from ultrasonic patters due to hand movements for gesture recognition, and processing-in-memory-based solutions to accelerate DNA alignment searches. 0830 Q-learning Based Backup for Energy Harvesting Powered Embedded Systems Speaker: Wei Fan, Shandong University, CN Authors: Wei Fan, Yujie Zhang, Weining Song, Mengying Zhao, Zhaoyan Shen and Zhiping Jia, Shandong University, CN 0900 A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks Speaker: Michael Niemier, University of Notre Dame, US Authors: Mohammad Mehdi Sharifi¹, Ramin Rajaei¹, Patsy Cadareanu², Pierre-Emmanuel Gaillardon², Yier Jin³, Michael Niemier¹ and X. Sharon Hu¹ ¹University of Notre Dame, US; ²University of Utah, US; ³University of Florida, US 0930 Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCN Speaker: Emad A. Ibrahim, Eindhoven University of Technology, NL Authors: Emad A. Ibrahim¹, Marc Geilen¹, Jos Huisken¹, Min Li² and Jose Pineda de Gyvez² ¹Eindhoven University of Technology, NL; ²NXP Semiconductors, NL 0945 PIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence Alignment Speaker: Deliang Fan, Arizona State University, US Authors: Shaahin Angizi¹, Jiao Sun¹, Wei Zhang¹ and Deliang Fan² ¹University of Central Florida, US; ²Arizona State University, US IPs IP4-17 9.8 Special Session: Panel: Variation-aware analyzes of Mega-MOSFET Memories, Challenges and Solutions Exhibition Theatre 0830 - 1000 Moderators:Firas MOHAMED, Silvaco, FR Jean-Baptiste DULUC, Silvaco, FR Designing large memories under manufacturing variability requires statistical approaches that rely on SPICE simulations at different Process, Voltage, Temperature operating points to verify that yield requirements will be met. Variation-aware simulations of full memories that consist of millions of transistors is a challenging task for both SPICE simulators and statistical methodology to achieve accurate results. The ideal solution for variation-aware verifications of full memories would be to run Monte Carlo simulations through SPICE simulators to assess that all the addressable elements enable successful write and read operations. However, this classical approach suffers from practical issues and prevent it to be used. Indeed, for large memory arrays (e.g. MB and more) the number of SPICE simulations to perform would be intractable to achieve a descent statistical precision. Moreover, the SPICE simulation of a single sample of the full-memory netlist that involve millions or billions of MOSFETs and parasitic elements might be very long or impossible because of the netlist size. Unfortunately, Fast-SPICE simulations are not a palatable solution for final verification because the loss of accuracy compared to pure SPICE simulations is difficult to evaluate for such netlists. So far, most of the variation-aware methodologies to analyze and validate Mega-MOSFETs memories rely on the assumption that the sub-blocks of the system (e.g. control unit, IOs, row decoders, column circuitries, memory cells) might be assessed independently. Doing so memory designers apply dedicated statistical approaches for each individual sub-block to reduce the overall simulation time to achieve variation-aware closure. When considering that each element of the memory is independent of its neighborhood, the simulation of the memory is drastically reduced to few MOSFETs on the critical paths (longest paths for read or write memory operation), the other sub-blocks being idealized and estimations being derived under Gaussian assumption. Using such an approach, memory designers avoid the usual statistical simulations of the full memory that is, most of the time, unpractical in terms of duration and load. Although the aforementioned approach has been widely used by memory designers, these methods reach their limits when designing memory for low-power and advanced-node technologies where non idealities arise. The consequence of less reliable results is that the memory designers compensate by increasing security margins at the expense of performances to achieve satisfactory yield. In this context sub-blocks can no longer be considered individually and Gaussianity no longer prevails, other practical simulation flows are required to verify full memories with satisfying performances. New statistical approaches and simulation flows must handle memory slices or critical paths with all relevant sub-blocks in order to consider element interactions to be more realistic. Additionally, these approaches must handle the hierarchy of the memory to respect variation ranges of each sub-block, from low sigma for control units and IOs to high sigma for highly replicated blocks. Using a virtual reconstruction of the full memory the yield can be asserted without relying on the assumptions of individual sub-block analyzes. With accurate estimation over the full memory, no more security margins are required, and better performances will be reached." Panelists: Yves Laplanche, ARM, FR Lorenzo Ciampolini, CEA, FR Pierre Faubet, SILVACO FRANCE, FR IP4 Interactive Presentations Poster Area 1000 - 1030 Interactive Presentations run simultaneously during a 30-minute slot. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session IP4-1 HIT: a hidden instruction Trojan model for processors Speaker: Jiaqi Zhang, Tongji University, CN Authors: Jiaqi Zhang¹, Ying Zhang¹, Huawei Li² and Jianhui Jiang³ ¹Tongji University, CN; ²Chinese Academy of Sciences, CN; ³School of Software Engineering, Tongji University, CN IP4-2 Bitstream Modification Attack on SNOW 3G Speaker: Michail Moraitis, Royal Institute of Technology KTH, SE Authors: Michail Moraitis and Elena Dubrova, Royal Institute of Technology - KTH, SE IP4-3 A Machine Learning Based Write Policy for SSD Cache in Cloud Block Storage Speaker: Yu Zhang, Huazhong University of Science & Technology, CN Authors: Yu Zhang¹, Ke Zhou¹, Ping Huang², Hua Wang¹, Jianying Hu³, Yangtao Wang¹, Yongguang Ji³ and Bin Cheng³ ¹Huazhong University of Science & Technology, CN; ²Temple University, US; ³Tencent Technology (Shenzhen) Co., Ltd., CN IP4-4 You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-design Speaker: Weiwei Chen, Chinese Academy of Sciences, CN Authors: Weiwei Chen, Ying Wang, Shuang Yang, Cheng Liu and Lei Zhang, Chinese Academy of Sciences, CN IP4-5 When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing Speaker: Yawen Zhang, Peking University, CN Authors: Yawen Zhang¹, Sheng Lin², Runsheng Wang¹, Yanzhi Wang², Yuan Wang¹, Weikang Qian³ and Ru Huang¹ ¹Peking University, CN; ²Northeastern University, US; ³Shanghai Jiao Tong University, CN IP4-6 WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation Speaker: Yehuda Kra, Bar-Ilan University, IL Authors: Yehuda Kra, Adam Teman and Tzachi Noy, Bar-Ilan University, IL IP4-7 DeepNVM: A Framework for Modeling and Analysis of Non-Volatile Memory Technologies for Deep Learning Applications Speaker: Ahmet Inci, Carnegie Mellon University, US Authors: Ahmet Inci, Mehmet M Isgenc and Diana Marculescu, Carnegie Mellon University, US IP4-8 Efficient Embedded Machine Learning applications using Echo State Networks Speaker: Rolando Brondolin, Politecnico di Milano, IT Authors: Luca Cerina¹, Giuseppe Franco², Claudio Gallicchio³, Alessio Micheli³ and Marco D. Santambrogio⁴ ¹politecnico di milano, IT; ²Scuola Superiore Sant'Anna / Università di Pisa, IT; ³Università di Pisa, IT; ⁴Politecnico di Milano, IT IP4-9 ExplFrame: Exploiting Page Frame Cache for Fault Analysis of Block Ciphers Speaker: Anirban Chakraborty, IIT Kharagpur, IN Authors: Anirban Chakraborty¹, Sarani Bhattacharya², Sayandeep Saha¹ and Debdeep Mukhopadhyay¹ ¹IIT Kharagpur, IN; ²KU Leuven, BE IP4-10 XGBIR: An XGBoost-based IR Drop Predictor for Power Delivery Network Speaker: An-Yu Su, National Chiao Tung University, TW Authors: Chi-Hsien Pao, Yu-Min Lee and An-Yu Su, National Chiao Tung University, TW IP4-11 On Pre-Assignment Route Prototyping for Irregular Bumps on BGA Packages Speaker: Hung-Ming Chen, National Chiao Tung University, TW Authors: Jyun-Ru Jiang¹, Yun-Chih Kuo², Simon Chen³ and Hung-Ming Chen¹ ¹National Chiao Tung University, TW; ²National Taiwan University, TW; ³MediaTek.inc, TW IP4-12 Towards best-effort approximation: Applying NAS to Approximate Computing Speaker: Weiwei Chen, Chinese Academy of Sciences, CN Authors: Weiwei Chen, Ying Wang, Shuang Yang, Cheng Liu and Lei Zhang, Chinese Academy of Sciences, CN IP4-13 On the Automatic Exploration of Weight Sharing for Deep Neural Network Compression Speaker: Etienne Dupuis, École Centrale de Lyon, FR Authors: Etienne Dupuis¹, David Novo², Ian O'Connor¹ and Alberto Bosio¹ ¹Lyon Institute of Nanotechnology, FR; ²Université de Montpellier, FR IP4-14 Robust and High-Performance12-T Interlocked SRAM for In-Memory Computing Speaker: Joycee Mekie, IIT Gandhinagar, IN Authors: Neelam Surana, Mili Lavania, Abhishek Barma and Joycee Mekie, IIT Gandhinagar, IN IP4-15 High Density STT-MRAM compiler design, validation and characterization methodology in 28nm FDSOI technology Speaker: Piyush Jain, ARM Embedded Technologies Pvt Ltd., IN Authors: Piyush Jain¹, Akshay Kumar¹, Nicolaas Van Winkelhoff², Didier Gayraud², Surya Gupta³, Abdelali El Amraoui², Giorgio Palma², Alexandra Gourio², Laurentz Vachez², Luc Palau², Jean-Christophe Buy² and Cyrille Dray² ¹ARM Embedded Technologies Pvt Ltd., IN; ²ARM France, FR; ³ARM Embedded technologies Pvt Ltd., IN IP4-16 An Approximation-based Fault Detection Scheme for Image Processing Applications Speaker: Antonio Miele, Politecnico di Milano, IT Authors: Matteo Biasielli, Luca Cassano and Antonio Miele, Politecnico di Milano, IT IP4-17 Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays Speaker: Gautam Choudhary, Adobe Research, India, IN Authors: Gautam Choudhary¹, Sandeep Pal¹, Debraj Kundu¹, Sukanta Bhattacharjee², Shigeru Yamashita³, Bing Li⁴, Ulf Schlichtmann⁴ and Sudip Roy¹ ¹IIT Roorkee, IN; ²Indian Statistical Institute, IN; ³Ritsumeikan University, JP; ⁴TU Munich, DE 10.1 Special Day on "Silicon Photonics": High-Speed Silicon Photonics Interconnects for Data Center and HPC Amphithéâtre Jean Prouve 1100 - 1230 Chair:Ian O’Connor, Ecole Centrale de Lyon, FR Co-Chair:Luca Ramini, Hewlett Packard Labs, US 1100 The need and challenges of Co-packaging and Optical Integration in Data Centers Author: Liron Gantz, Mellanox, US 1130 Power and Cost Estimate of Scalable All-to-All Topologies with Silicon Photonics Links Author: Luca Ramini, Hewlett Packard Labs, US 1200 The next frontier in silicon photonic design: experimentally validated statistical models Authors: Geoff Duggan¹, James Pond¹, Xu Wang¹, Ellen Schelew¹, Federico Gomez¹, Milad Mahpeykar¹, Ray Chung¹, Zequin Lu¹, Parya Samadian¹, Jens Niegemann¹, Adam Reid¹, Roberto Armenta¹, Dylan McGuire¹, Peng Sun², Jared Hulme², Mudit Jan² and Ashkan Seyedi² ¹Lumerical, US; ²Hewlett Packard Labs, US 10.2 Autonomous Systems Design Initiative: Uncertainty Handling in Safe Autonomous Systems (UHSAS) Chamrousse 1100 - 1230 Chair:Philipp Mundhenk, Autonomous Intelligent Driving GmbH, DE Co-Chair:Ahmad Adee, Bosch Corporate Research, DE 1100 Making the Relationship between Uncertainty Estimation and Safety Less Uncertain Speaker: Peter Schlicht, Volkswagen, DE Authors: Peter Schlicht¹, Vincent Aravantinos² and Fabian Hüger¹ ¹Volkswagen, DE; ²AID, DE 1130 System Theoretic View on Uncertainties Speaker: Roman Gansch, Robert Bosch GmbH, DE Authors: Roman Gansch and Ahmad Adee, Robert Bosch GmbH, DE 1200 Detection of False Negative and False Positive Samples in Semantic Segmentation Speaker: Matthias Rottmann, School of Mathematics & Science and ICMD, DE Authors: Hanno Gottschalk¹, Matthias Rottmann¹, Kira Maag¹, Robin Chan¹, Fabian Hüger² and Peter Schlicht² ¹School of Mathematics & Science and ICMD, DE; ²Volkswagen, DE 10.3 Special Session: Next Generation Arithmetic for Edge Computing Autrans 1100 - 1230 Chair:Farhad Merchant, RWTH Aachen University, DE Co-Chair:Akash Kumar, TU Dresden, DE Arithmetic is ubiquitous in today's digital world, ranging from embedded to high- performance computing systems. With machine learning at fore in a wide range of application domains from wearables, automotive, avionics to weather prediction, sufficiently accurate yet low-cost arithmetic is the need for the day. Recently, there have been several advances in the domain of computer arithmetic like high-precision anchored numbers from ARM, posit arithmetic by John Gustafson, and bfloat16, etc. as an alternative to IEEE 754-2008 compliant arithmetic. Optimizations on fixed-point and integer arithmetic are also pursued actively for low-power computing architectures. Furthermore, approximate computing and transprecision/mixed-precision computing have been exciting areas for research forever. While academic research in the domain of computer arithmetic has a long history, industrial adoption of some of these new data-types and techniques is in its early stages and expected to increase in future. bfloat16 is an excellent example of that. In this special session, we bring academia and industry together to discuss latest results and future directions for research in the domain of next-generation computer arithmetic. 1100 Paradigm on Approximate Compute for Complex Perception-Based Neural Networks Authors: Andre Guntoro and Cecilia De la Parra, Robert Bosch GmbH, DE 1122 Next Generation FPGA Arithmetic for AI Author: Martin Langhammer, Intel, GB 1144 Application-Specific Arithmetic Design Author: Florent de Dinechin, INSA Lyon, FR 1206 A Comparison of Posit and IEEE 754 Floating-Point Arithmetic that Accounts for Exception Handling Author: John Gustafson, National University of Singapore, SG 10.4 Design Methodologies for Hardware Approximation Stendhal 1100 - 1230 Chair:Lukas Sekanina, Brno University of Technology, CZ Co-Chair:David Novo, CNRS & University of Montpellier, FR New methods for the design and evaluation of approximate hardware are key to its success. This section shows that these approximation methods are applicable across different levels of hardware description including an RTL design of an approximate multiplier, approximate circuits modelled using binary decision diagrams and a behavioural description used in the context of high level synthesis of hardware accelerators. The papers of this section also show how to address another challenge - an efficient error evaluation - by means of new statistical and formal verification methods. 1100 REALM: Reduced-Error Approximate Log-based Integer Multiplier Speaker: Hassaan Saadat, University of New South Wales, AU Authors: Hassaan Saadat¹, Haris Javaid², Aleksandar Ignjatovic¹ and Sri Parameswaran¹ ¹University of New South Wales, AU; ²Xilinx, SG 1130 A fast BDD Minimization Framework for Approximate Computing Speaker: Oliver Keszocze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE Authors: Andreas Wendler and Oliver Keszocze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE 1200 On the Design of High Performance HW Accelerator through High-level Synthesis Scheduling Approximations Speaker: Benjamin Carrion Schaefer, University of Texas at Dallas, US Authors: Siyuan Xu and Benjamin Carrion Schaefer, University of Texas at Dallas, US 1215 Fast Kriging-based Error Evaluation for Approximate Computing Systems Speaker: Daniel Menard, INSA Rennes, FR Authors: Justine Bonnot¹, Karol Desnos¹ and Daniel Menard² ¹Université de Rennes / Inria / IRISA, FR; ²INSA Rennes, FR IPs IP5-1, IP5-2 10.5 Emerging Machine Learning Applications and Models Bayard 1100 - 1230 Chair:Mladen Berekovic, TU Braunschweig, DE Co-Chair:Sophie Quinton, INRIA, FR This session presents new application domains and new models for neural networks, discussing two novel video applications: multi-view and surveillance, and discusessing a Bayesian model approach for neural networks. 1100 Communication-efficient View-Pooling for Distributed Inference with Multi-View Neural Networks Speaker: Manik Singhal, School of Electrical and Computer Engineering, Purdue University, US Authors: Manik Singhal, Anand Raghunathan and Vijay Raghunathan, Purdue University, US 1130 An Anomaly Comprehension Neural Network for Surveillance Videos on Terminal Devices Speaker: Yuan Cheng, Shanghai Jiao Tong University, CN Authors: Yuan Cheng¹, Guangtai Huang², Peining Zhen¹, Bin Liu², Hai-Bao Chen¹, Ngai Wong³ and Hao Yu² ¹Shanghai Jiao Tong University, CN; ²Southern University of Science and Technology, CN; ³University of Hong Kong, HK 1200 BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA Speaker: Hiromitsu Awano, Osaka University, JP Authors: Hiromitsu Awano and Masanori Hashimoto, Osaka University, JP 10.6 Secure Processor Architecture Lesdiguières 1100 - 1230 Chair:Emanule Regnath, TU Munich, DE Co-Chair:Erkay Savas, Sabanci University, TR This session proposes an overview of new mechanisms to protect processor architectures, boot sequences, caches, and energy management. The solutions strive to address and mitigate a wide range of attack methodologies, with a special focus on new emerging attacks. 1100 Capturing and Obscuring Ping-Pong Patterns to Mitigate Continuous Attacks Speaker: Kai Wang, Harbin Institute of Technology, CN Authors: Kai Wang¹, Fengkai Yuan², Rui Hou², Zhenzhou Ji¹ and Dan Meng² ¹Harbin Institute of Technology, CN; ²Chinese Academy of Sciences, CN 1130 Mitigating Cache-Based Side-Channel Attacks through Randomization: A Comprehensive System and Architecture Level Analysis Speaker: Houman Homayoun, University of California, Davis, US Authors: Han Wang¹, Hossein Sayadi¹, Avesta Sasan¹, Setareh Rafatirad¹, Houman Homayoun¹, Liang Zhao¹ and Tinoosh Mohsenin² ¹George Mason University, US; ²University of Maryland, Baltimore County, US 1200 Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LAC Speaker: Tim Fritzmann, TU Munich, DE Authors: Tim Fritzmann¹, Georg Sigl² and Johanna Sepúlveda³ ¹TU Munich, DE; ²TU Munich/Fraunhofer AISEC, DE; ³Airbus Defence and Space, DE IPs IP5-3 10.7 Accelerators for Neuromorphic Computing Berlioz 1100 - 1230 Chair:Alexandre Levisse, EPFL, CH Co-Chair:Deliang Fan, Arizona State University, US In this session, special hardware accelerators based on different technologies for neuromorphic computing will be presented. These accelerators (i) improve the computing efficiency by using pulse widths to deliver information across memristor crossbars, (ii) enhance the robustness of neuromorphic computing with unary coding and priority mapping, and (iii) explore the modulation of light in transferring information so to push the performance of computing systems to new limits. 1100 A Pulse Width Neuron with Continuous Activation for Processing-In-Memory Engines Speaker: Shuhang Zhang, TU Munich, DE Authors: Shuhang Zhang¹, Bing Li¹, Hai (Helen) Li² and Ulf Schlichtmann¹ ¹TU Munich, DE; ²Duke University, US / TU Munich, US 1130 Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic Computing Speaker: Li Jiang, Shanghai Jiao Tong University, CN Authors: Chang Ma, Yanan Sun, Weikang Qian, Ziqi Meng, Rui Yang and Li Jiang, Shanghai Jiao Tong University, CN 1200 LightBulb: A Photonic-Nonvolatile-Memory-based Accelerator for Binarized Convolutional Neural Networks Authors: Farzaneh Zokaee¹, Qian Lou¹, Nathan Youngblood², Weichen Liu³, Yiyuan Xie⁴ and Lei Jiang¹ ¹Indiana University Bloomington, US; ²University of Pittsburh, US; ³Nanyang Technological University, SG; ⁴Southwest University, CN IPs IP5-4, IP5-5 11.0 LUNCHTIME KEYNOTE SESSION Amphitéâtre Jean Prouvé 1320 - 1350 Chair:Gabriela Nicolescu, Polytechnique Montréal, CA Co-Chair:Luca Ramini, Hewlett Packard Labs, US 1320 Memory Driven Computing to Revolutionize the Medical Sciences Author: Joachim Schultze, Director Platform for Single Cell Genomics and Epigenomics German Center for Neurodegenerative Diseases, DE 11.1 Special Day on "Silicon Photonics": Advanced Applications Amphithéâtre Jean Prouve 1400 - 1530 Chair:Olivier Sentieys, University of Rennes, IRISA, INRIA, FR Co-Chair:Gabriela Nicolescu, Polytechnique Montréal, CA 1400 System-level evaluation of chip-scale silicon photonic networks for emerging data- intensive applications Speaker: Ayse Coskun, Boston University, US Authors: Aditya Narayan¹, Yvain Thonnart², Pascal Vivet², Ajay Joshi¹ and Ayse Coskun¹ ¹Boston University, US; ²CEA-Leti, FR 1430 OSCAR: an Optical Stochastic Computing AcceleRator for Polynomial Functions Speaker: Sébastien Le Beux, Concordia University, CA Authors: Hassnaa El-Derhalli, Sébastien Le Beux and Sofiène Tahar, Concordia University, CA 1500 POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems Speaker: Yvain Thonnart, CEA-Leti, FR Authors: Yvain Thonnart¹, Stéphane Bernabe¹, Jean Charbonnier¹, César Fuget Totolero¹, Pierre Tissier¹, Benoit Charbonnier¹, Stephane Malhouitre¹, Damien Saint-Patrice¹, Myriam Assous¹, Aditya Narayan², Ayse Coskun², Denis Dutoit¹ and Pascal Vivet¹ ¹CEA-Leti, FR; ²Boston University, US 11.2 Autonomous Systems Design Initiative: Autonomous Cyber-Physical Systems: Modeling and Verification Chamrousse 1400 - 1530 Chair:Nikos Aréchiga, Toyota Research Institute, US Co-Chair:Jyotirmoy V. Deshmukh, University of Southern California, US 1400 Trustworthy Autonomy: Behavior Prediction and Validation Author: Katherine Driggs-Campbell, University of Illinois Urbana Champaign, US 1430 On Infusing Logical Reasoning into Robot Learning Author: Marco Pavone, Stanford University, US 1500 Formally-Specifiable Agent Behavior Models for Autonomous Vehicle Test Generation Author: Jonathan DeCastro, Toyota Research Institute, US 11.3 Special Session: Emerging Neural Algorithms and Their Impact on Hardware Autrans 1400 - 1530 Chair:Ian O’Connor, Ecole Centrale de Lyon, FR Co-Chair:Michael Niemier, University of Notre Dame, US 1400 Analog Resistive Crossbar Arrays for Neural Network Acceleration Author: Martin Frank, IBM, US 1430 In-Memory Computing for Memory Augmented Neural Networks Authors: X. Sharon Hu¹ and Anand Raghunathan² ¹University of Notre Dame, US; ²Purdue University, US 1500 Hardware Challenges for Neural Recommendation Systems Author: Udit Gupta, Harvard University, US 11.4 Reliable in-memory computing Stendhal 1400 - 1530 Chair:Jean-Philippe Noel, CEA-Leti, FR Co-Chair:Kvatinsky Shahar, Technion, IL This session deals with work on the reliability of computing in memories. This includes new design techniques to improve CNN computing in ReRAM going through the co-optimization between device and algorithm to improve the reliability of ReRAM-based Graph Processing. Moreover, this session also deals with work on the improvment of reliability of well-established STT-MRAM and PCM. Finally, early works presenting stochastic computing and disruptive image processing techniques based on memristor are also discussed. 1400 ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM Speaker: Yitu Wang, Fudan University, CN Authors: Yitu Wang¹, Fan Chen², Linghao Song², C.-J. Richard Shi³, Hai (Helen) Li⁴ and Yiran Chen² ¹Fudan University, CN; ²Duke University, US; ³University of Washington, US; ⁴Duke University, US / TU Munich, US 1430 GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing Speaker: Chin-Fu Nien, Academia Sinica, TW Authors: Chin-Fu Nien¹, Yi-Jou Hsiao², Hsiang-Yun Cheng¹, Cheng-Yu Wen³, Ya-Cheng Ko³ and Che-Ching Lin³ ¹Academia Sinica, TW; ²National Chiao Tung University, TW; ³National Taiwan University, TW 1500 STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation Speaker: Hossein Asadi, Sharif University of Technology, IR Authors: Mostafa Hadizadeh, Elham Cheshmikhani and Hossein Asadi, Sharif University of Technology, IR 1515 Effective Write Disturbance Mitigation Encoding Scheme for High-density PCM Speaker: Muhammad Imran, Sungkyunkwan University, KR Authors: Muhammad Imran, Taehyun Kwon and Joon-Sung Yang, Sungkyunkwan University, KR IPs IP5-6, IP5-7 11.5 Compile time and virtualization support for embedded system design Bayard 1400 - 1530 Chair:Nicola Bombieri, Università di Verona, IT Co-Chair:Rodolfo Pellizzoni, University of Waterloo, CA The session leverages compiler support and novel architectural features, such as virtualization extensions and emerging memory structures, to optimize the design flow of modern embedded systems. 1400 Unified Thread- and Data-Mapping for Multi-Threaded Multi-Phase Applications on SPM Many-Cores Speaker: Anuj Pathania, National University of Singapore, SG Authors: Vanchinathan Venkataramani, Anuj Pathania and Tulika Mitra, National University of Singapore, SG 1430 Generalized Data Placement Strategies for Racetrack Memories Speaker: Asif Ali Khan, TU Dresden, DE Authors: Asif Ali Khan, Andres Goens, Fazal Hameed and Jeronimo Castrillon, TU Dresden, DE 1500 ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms Speaker: Lukas Jünger, RWTH Aachen University, DE Authors: Lukas Jünger¹, Jan Luca Malte Bölke², Stephan Tobies², Rainer Leupers¹ and Andreas Hoffmann² ¹RWTH Aachen University, DE; ²Synopsys GmbH, DE IPs IP5-8, IP5-9 11.6 Aging: estimation and mitigation Lesdiguières 1400 - 1530 Chair:Arnaud Virazel, Université de Montpellier / LIRMM, FR Co-Chair:Lorena Anghel, University Grenoble-Alpes, FR This session shares improvements in aging calculations of emerging technologies and how to take these reliability aspects into account during power grid design and floorplanning of FPGAs. 1400 Impact of NBTI Aging on Self-Heating in Nanowire FET Speaker: Hussam Amrouch, Karlsruhe Institute of Technology, DE Authors: Om Prakash¹, Hussam Amrouch¹, Sanjeev Kumar Manhas² and Joerg Henkel¹ ¹Karlsruhe Institute of Technology, DE; ²IIT Roorkee, IN 1430 PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning Speaker: Sukanta Dey, IIT Guwahati, IN Authors: Sukanta Dey, Sukumar Nandi and Gaurav Trivedi, IIT Guwahati, IN 1500 An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs Speaker: Carl Sechen, University of Texas at Dallas, US Authors: Bo Hu, Mustafa Shihab, Yiorgos Makris, Benjamin Carrion Schaefer and Carl Sechen, University of Texas at Dallas, US IPs IP5-10, IP5-11 11.7 System Level Security Berlioz 1400 - 1530 Chair:Pascal Benoit, Université de Montpellier, FR Co-Chair:David Hely, Unviversity Grenoble Alpes, FR The session focuses on topics of system-level security, especially related to authentication. The papers span topics of memory authentication and group-of-users authentication, with a focus on IoT applications. 1400 AMSA: Adaptive Merkle Signature Architecture Speaker: Emanuel Regnath, TU Munich, DE Authors: Emanuel Regnath and Sebastian Steinhorst, TU Munich, DE 1430 DISSECT: Dynamic Skew-and-Split Tree for Memory Authentication Speaker: Lam Siew-Kei, Nanyang Technological University, SG Authors: Saru Vig¹, Rohan Juneja² and Siew Kei Lam¹ ¹Nanyang Technological University, SG; ²Qualcomm, IN 1500 Design-flow Methodology for Secure Group Anonymous Authentication Speaker: Rashmi Agrawal, Boston University, US Authors: Rashmi Agrawal¹, Lake Bu², Eliakin del Rosario¹ and Michel Kinsy¹ ¹Boston University, US; ²Draper Lab, US IPs IP5-12 11.8 Special Session: Self-aware, biologically-inspired adaptive hardware systems for ultimate dependability and longevity Exhibition Theatre 1400 - 1530 Chair:Martin A. Trefzer, University of York, GB Co-Chair:Andy M. Tyrrell, University of York, GB State-of-the-art electronic design allows the integration of complex electronic systems comprising thousands of high-level functions on a single chip. This has become possible and feasible because of the combination of atomic-scale semiconductor technology allowing VLSI of billions of transistors, and EDA tools that can handle their useful application and integration by following strictly hierarchical design methodology. This results in many layers of abstraction within a system that makes it implementable, verifiable and, ultimately, explainable. However, while many layers of abstraction maximise the likelihood of a system to function correctly, this can prevent a design from making full use of the capabilities of current technology. Making systems brittle at a time where NoC- and SoC-based implementations are the only way to increase compute capabilities as clock speed limits are reached, devices are affected by variability and ageing, and heat-dissipation limits impose "dark silicon" constraints. Design challenges of electronic systems are no longer driven by making designs smaller but by creating systems that are ultra-low power, resilient and autonomous in their adaptation to anomalies including faults, timing violations and performance degradation. This gives rise to the idea of self-aware hardware, capable of adaptive behaviours or features taking inspiration from, e.g., biological systems, learning algorithms, factory processes. The challenge is to adopt and implement these concepts while achieving a "next- generation" kind of electronic system which is considered at least as useful and trustworthy as its "classical" counterpart—plus additional essential features for future system design and operation. The goal of this Special Session is to present research from world-leading experts addressing state-of-the-art techniques and devices demonstrating the efficacy of concepts of self-awareness, adaptivity and bio-inspiration in the context of real-world hardware systems and applications with a focus on autonomous resource management at runtime, robustness and performance, and new computing architecture in embedded hardware systems." 1400 Embedded Social Insect-Inspired Intelligence Networks for System-level Runtime Management Speaker: Matthew R. P. Rowlings, University of York, GB Authors: Matthew Rowlings, Andy Tyrrell and Martin Albrecht Trefzer, University of York, GB 1420 Optimising Resource Management for Embedded Machine Learning Authors: Lei Xun, Long Tran-Thanh, Bashir Al-Hashimi and Geoff Merrett, University of Southampton, GB 1440 Emergent Control of MPSoC Operation by a Hierarchical Supervisor / Reinforcement Learning Approach Speaker: Florian Maurer, TU Munich, DE Authors: Florian Maurer¹, Andreas Herkersdorf¹, Bryan Donyanavard², Amir M. Rahmani² and Nikil Dutt² ¹TU Munich, DE; ²University of California, Irvine, US 1500 AstroByte: A multi-FPGA Architecture for Accelerated Simulations of Spiking Astrocyte Neural Networks Speaker: Shvan Karim, Ulster University, GB Authors: Shvan Haji Karim, Jim Harkin, McDaid Liam, Gardiner Bryan and Junxiu Liu, Ulster University, GB IP5 Interactive Presentations Poster Area 1530 - 1600 Interactive Presentations run simultaneously during a 30-minute slot. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session IP5-1 Statistical Model Checking of Approximate Circuits: Challenges and Opportunities Speaker and Author: Josef Strnadel, Brno University of Technology, CZ IP5-2 Runtime Accuracy-Configurable Approximate Hardware Synthesis Using Logic Gating and Relaxation Speaker: Tanfer Alan, Karlsruhe Institute of Technology, DE Authors: Tanfer Alan¹, Andreas Gerstlauer² and Joerg Henkel¹ ¹Karlsruhe Institute of Technology, DE; ²University of Texas at Austin, US IP5-3 Post-Quantum Secure Boot Speaker: Vinay B. Y. Kumar, Nanyang Technological University, SG Authors: Vinay B. Y. Kumar¹, Naina Gupta², Anupam Chattopadhyay¹, Michael Kasper³, Christoph Krauss⁴ and Ruben Niederhagen⁴ ¹Nanyang Technological University, SG; ²Indraprastha Institute of Information Technology, IN; ³Fraunhofer Singapore, SG; ⁴Fraunhofer SIT, DE IP5-4 ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit Controls Speaker: Jiaqi Gu, University of Texas at Austin, US Authors: Jiaqi Gu¹, Zheng Zhao¹, Chenghao Feng¹, Hanqing Zhu², Ray T. Chen¹ and David Z. Pan¹ ¹University of Texas at Austin, US; ²Shanghai Jiao Tong University, CN IP5-5 Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise Speaker: Ying Zhu, TU Munich, DE Authors: Ying Zhu¹, Grace Li Zhang¹, Tianchen Wang², Bing Li¹, Yiyu Shi², Tsung-Yi Ho³ and Ulf Schlichtmann¹ ¹TU Munich, DE; ²University of Notre Dame, US; ³National Tsing Hua University, TW IP5-6 Computational Restructuring: Rethinking Image Processing using Memristor Crossbar Arrays Speaker: Rickard Ewetz, University of Central Florida, US Authors: Baogang Zhang, Necati Uysal and Rickard Ewetz, University of Central Florida, US IP5-7 SCRIMP: A General Stochastic Computing Acceleration Architecture using ReRAM in-Memory Processing Speaker: Saransh Gupta, University of California, San Diego, US Authors: Saransh Gupta¹, Mohsen Imani¹, Joonseop Sim¹, Andrew Huang¹, Fan Wu¹, M. Hassan Najafi² and Tajana Rosing¹ ¹University of California, San Diego, US; ²University of Louisiana, US IP5-8 TDO-CIM: Transparent Detection and Offloading for Computation In-memory Speaker: Lorenzo Chelini, Eindhoven University of Technology, NL Authors: Kanishkan Vadivel¹, Lorenzo Chelini², Ali BanaGozar¹, Gagandeep Singh², Stefano Corda², Roel Jordans¹ and Henk Corporaal¹ ¹Eindhoven University of Technology, NL; ²IBM Research, CH IP5-9 BackFlow: Backward Edge Control Flow Enforcement for Low End ARM Microcontrollers Speaker: Cyril Bresch, LCIS, FR Authors: Cyril Bresch¹, David Hély² and Roman Lysecky³ ¹LCIS, FR; ²LCIS - Grenoble INP, FR; ³University of Arizona, US IP5-10 Delay Sensitivity Polynomials Based Design-Dependent Performance Monitors for Wide Operating Ranges Speaker: Ruikai Shi, Chinese Academy of Sciences, CN Authors: Ruikai Shi¹, Liang Yang² and Hao Wang² ¹Chinese Academy of Sciences / University of Chinese Academy of Sciences, CN; ²Loongson Technology Corporation Ltd., CN IP5-11 Mitigation of Sense Amplifier Degradation Using Skewed Design Speaker: Daniel Kraak, TU Delft, NL Authors: Daniel Kraak¹, Mottaqiallah Taouil¹, Said Hamdioui¹, Pieter Weckx², Stefan Cosemans² and Francky Catthoor² ¹TU Delft, NL; ²IMEC, BE IP5-12 Blockchain Technology Enabled Pay Per Use Licensing Approach for Hardware IPs Speaker: Krishnendu Guha, University of Calcutta, IN Authors: Krishnendu Guha, Debasri Saha and Amlan Chakrabarti, University of Calcutta, IN 12.1 Special Day on "Silicon Photonics": Design Automation for Photonics Amphithéâtre Jean Prouve 1600 - 1730 Chair:Dave Penkler, SCINTIL Photonics, US Co-Chair:Luca Ramini, Hewlett Packard Labs, US 1600 Opportunities for Cross-Layer Design in High-Performance Computing Systems with Integrated Silicon Photonic Networks Speaker: Mahdi Nikdast, Colorado State University, US Authors: Asif Mirza, Shadi Manafi Avari, Ebadollah Taheri, Sudeep Pasricha and Mahdi Nikdast, Colorado State University, US 1630 Design and validation of photonic IP macros based on foundry PDKs Authors: Ruping Cao, François Chabert and Pieter Dumon, Luceda Photonics, BE 1700 Efficient Optical Power Delivery System for Hybrid Electronic-Photonic Manycore Processors Speaker: Jiang Xu, Hong Kong University of Science and Technology, HK Authors: Shixi Chen, Jiang Xu, Xuanqi Chen, Zhifei Wang, Jun Feng, Jiaxu Zhang, Zhongyuan Tian and Xiao Li, Hong Kong University of Science and Technology, HK 12.2 Autonomous Systems Design Initiative: Emerging Approaches to Autonomous Systems Design Chamrousse 1600 - 1730 Chair:Dirk Ziegenbein, Robert Bosch GmbH, DE Co-Chair:Sebastian Steinhorst, TU Munich, DE 1600 A Preliminary View on Automotive Cyber Security Management Systems Speaker: Christoph Schmittner, Austrian Institute of Technology, AT Authors: Christoph Schmittner¹, Jürgen Dobaj², Georg Macher³ and Eugen Brenner² ¹Austrian Institute of Technology, AT; ²TU Graz, DE; ³TU Graz, AT 1630 Towards Safety Verification of Direct Perception Neural Networks Speaker: Chih-Hong Cheng, DENSO Automotive Deutschland GmbH, DE Authors: Chih-Hong Cheng¹, Chung-Hao Huang², Thomas Brunner² and Vahid Hashemi³ ¹DENSO Automotive Deutschland GmbH, DE; ²Fortiss, DE; ³Audi AG, DE 1700 Minimizing Execution Duration in the Presence of Learning-Enabled Components Speaker: Sanjoy Baruah, Washington University in St. Louis, US Authors: Kunal Agrawal¹, Sanjoy Baruah², Alan Burns³ and Abhishek Singh² ¹Washington University in Saint Louis, US; ²Washington University in St. Louis, US; ³University of York, GB 12.3 Reconfigurable Systems for Machine Learning Autrans 1600 - 1730 Chair:Bogdan Pasca, Intel, FR Co-Chair:Smail Niar, Université Polytechnique Hauts-de-France, FR Machine learning continues to attract significant research attention and reconfigurable systems offer ample flexibility for exploring new approaches to accelerating these workloads. In this session we explore how FPGAs can be used for a variety of machine learning workloads. We discuss memory optimisations for 3D convolutional neural networks (CNNs), design and implementation of binarised neural networks, and an approach for cascading hybrid precision datapaths to improve CNN classification latency. 1600 Exploration of Memory Access Optimization for FPGA-based 3D CNN Accelerator Speaker: Teng Tian, University of Science and Technology of China, CN Authors: Teng Tian, Xi Jin, Letian Zhao, Xiaotian Wang, Jie Wang and Wei Wu, University of Science and Technology of China, CN 1630 A Throughput-Latency Co-Optimised Cascade of Convolutional Neural Network Classifiers Speaker: Alexandros Kouris, Imperial College London, GB Authors: Alexandros Kouris¹, Stylianos Venieris² and Christos Bouganis¹ ¹Imperial College London, GB; ²Samsung AI, GB 1700 OrthrusPE: Runtime Reconfigurable Processing Elements for Binary Neural Networks Speaker: Nael Fasfous, TU Munich, DE Authors: Nael Fasfous¹, Manoj-Rohit Vemparala², Alexander Frickenstein² and Walter Stechele¹ ¹TU Munich, DE; ²BMW Group, DE 12.4 Approximate Computing Works! Applications & Case Studies Stendhal 1600 - 1730 Chair:Oliver Keszocze, Friedrich-Alexander-University Erlangen-Nuremberg (FAU), DE Co-Chair:Benjamin Carrion Schaefer, University of Texas at Dallas, US Approximate computing leverages the fact that many applications are tolerant of incorrect results. This session highlights that by presenting methods and applications that optimize the trade-off between area, power and output error. At the same time it is important to ensure that the approximation approaches are scalable because complex problems are addressed. While some of these approaches completely work at the application level, others are oriented towards optimizing key subcircuits. 1600 Towards Generic and Scalable Word-Length Optimization Speaker: Van-Phu Ha, Université de Rennes / Inria / IRISA, FR Authors: Van-Phu Ha¹, Tomofumi Yuki² and Olivier Sentieys² ¹Université de Rennes / Inria / IRISA, FR; ²INRIA, FR 1630 Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator Speaker: Paul Detterer, Eindhoven University of Technology, NL Authors: Paul Detterer¹, Cumhur Erdin¹, Jos Huisken¹, Hailong Jiao¹, Majid Nabi¹, Twan Basten¹ and Jose Pineda de Gyvez² ¹Eindhoven University of Technology, NL; ²NXP Semiconductors, US 1700 Approximation Trade Offs in an Image-Based Control System Speaker: Sayandip De, Eindhoven University of Technology, NL Authors: Sayandip De, Sajid Mohamed, Konstantinos Bimpisidis, Dip Goswami, Twan Basten and Henk Corporaal, Eindhoven University of Technology, NL 12.5 Cyber-Physical Systems for Manufacturing and Transportation Bayard 1600 - 1730 Chair:Ulrike Thomas, Chemnitz University of Technology, DE Co-Chair:Robert De Simone, INRIA, FR Modeling and design of transportation and manufacturing systems from a cyber-physical system (CPS) perspective have lately attracted extensive attention and the session covers various aspects, from modelling of traffic intersections and control of traffic signals, to implementations of iterative learning controllers for control blocks. Other contributions deal with the selection of network architectures for manufacturing plants and the Digital Twin of production processes for validation. 1600 CPS-oriented Modeling and Control of Traffic Signals Using Adaptive Back Pressure Speaker: Wanli Chang, University of York, GB Authors: Wanli Chang¹, Debayan Roy², Shuai Zhao¹, Anuradha Annaswamy³ and Samarjit Chakraborty² ¹University of York, GB; ²TU Munich, DE; ³Massachusetts Institute of Technology, US 1630 Network Synthesis for Industry 4.0 Speaker: Enrico Fraccaroli, Università di Verona, IT Authors: Enrico Fraccaroli, Alan Michael Padovani, Davide Quaglia and Franco Fummi, Università di Verona, IT 1700 Production Recipe Validation through Formalization and Digital Twin Generation Speaker: Stefano Spellini, Università di Verona, IT Authors: Stefano Spellini¹, Roberta Chirico¹, Marco Panato¹, Michele Lora² and Franco Fummi¹ ¹Università di Verona, IT; ²Singapore University of Technology and Design, SG 1715 Parallel Implementation of Iterative Learning Controllers on Multi-core Platforms Speaker: Mojtaba Haghi, Eindhoven University of Technology, NL Authors: Mojtaba Haghi¹, Yusheng Yao², Dip Goswami¹ and Kees Goossens² ¹Eindhoven University of Technology, NL; ²Eindhoven university of technology, NL 12.6 Industrial Experience: From Wafer-Level Up to IoT Security Lesdiguières 1600 - 1730 Chair:Enrico Macii, Politecnico di Torino, IT Co-Chair:Norbert Wehn, TU Kaiserslautern, DE This session addresses recent industrial experiences covering all Design Levels from Technology up to System Level 1600 Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis Authors: Andrew Yi-Ann Huang¹, Katherine Shu-Min Li², Ken Chau-Cheung Cheng³, Ji-Wei Li¹, Leon Li-Yang Chen⁴, Nova Cheng-Yen Tsai¹, Sying-Jyan Wang⁵, Chen-Shiun Lee¹, Leon Chou¹, Peter Yi-Yu Liao¹, Hsing-Chung Liang⁶ and Jwu E Chen⁷ ¹NXP Semiconductors Taiwan Ltd., TW; ²National Sun Yat-sen University, TW; ³NXP Semiconductors Taiwan Ltd, TW; ⁴National Sun Yat-Sen University, TW; ⁵National Chung-Hsing University, TW; ⁶Chung Yuan Christian University, TW; ⁷National Central University, TW 1615 A Method of Via Variation Induced Delay Computation Authors: Moonsu Kim¹, Yun Heo¹, Seungjae Jung¹, Kelvin Le², Jongpil Lee¹, Youngmin Shin¹, Nathaniel Conos² and Hanif Fatemi² ¹Samsung, KR; ²Synopsys, US 1630 Fully Automated Analog Sub-Circuit Clustering with Graph Convolutional Neural Networks Speaker: Keertana Settaluri, University of California, Berkeley, US Authors: Keertana Settaluri¹ and Elias Fallon² ¹University of California, Berkeley, US; ²Cadence Design Systems, US 1645 EVPS: An Automotive Video Acquisition and Processing Platform Speaker: Christophe Flouzat, CEA LIST, FR Authors: Christophe Flouzat¹, Erwan Piriou², Mickael Guibert¹, Bojan Jovanovic¹ and Mohamad Oussayran¹ ¹CEA LIST, FR; ²CEA List, FR 1700 An On-board Algorithm Implementation on an Embedded GPU: A Space Case Study Speaker: Ivan Rodriguez, UPC / BSC, ES Authors: Ivan Rodriguez¹, Leonidas Kosmidis², Olivier Notebaert³, Francisco J Cazorla² and David Steenari⁴ ¹UPC / BSC, ES; ²BSC, ES; ³Airbus Defence and Space, FR; ⁴European Space Agency, NL 1715 TLS-Level Security for Low Power Industrial IoT Network Infrastructures Authors: Jochen Mades¹, Gerd Ebelt¹, Boris Janjic¹, Frederik Lauer², Carl Rheinländer² and Norbert Wehn² ¹KSB SE & Co. KGaA, DE; ²TU Kaiserslautern, DE 12.7 Power-efficient multi-core embedded architectures Berlioz 1600 - 1730 Chair:Andreas Burg, EPFL, CH Co-Chair:Semeen Rehman, TU Wien, AT This session has papers that provide power-efficiency solutions for multi-core embedded architectures. Techniques discussed in the session are related to the architectural measures as well as effectively controlling voltage-frequency settings using machine learning based on user experiences. 1600 Tuning the ISA for increased heterogeneous computation in MPSoCs Authors: Pedro Henrique Exenberger Becker, Jeckson Dellagostin Souza and Antonio Carlos Schneider Beck, Universidade Federal do Rio Grande do Sul, BR 1630 User Interaction Aware Reinforcement Learning for Power and Thermal Efficiency of CPU-GPU Mobile MPSoCs Speaker: Somdip Dey, University of Essex, GB Authors: Somdip Dey¹, Amit Kumar Singh¹, Xiaohang Wang² and Klaus McDonald-Maier¹ ¹University of Essex, GB; ²South China University of Technology, CN 1700 Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster Speaker: Jie Chen, Università di Bologna, CN Authors: Jie Chen¹, Igor Loi², Luca Benini³ and Davide Rossi³ ¹Università di Bologna, FR; ²GreenWaves Technologies, FR; ³Università di Bologna, IT 12.8 Special Session: EDA Challenges in Monolithic 3D Integration: From Circuits to Systems Exhibition Theatre 1600 - 1730 Chair:Pascal Vivet, CEA-Leti, FR Co-Chair:Mehdi Tahoori, Karlsruhe Institute of Technology, DE Monolithic-3D integration (M3D) has the potential to improve the performance and energy efficiency of 3D ICs over conventional TSV-based counterparts. By using significantly smaller inter-layer vias (ILVs), M3D offers the "true" benefits of utilizing the vertical dimension for system integration: M3D provides ILVs that are 100x smaller than a TSV and have similar dimensions as normal vias in planar technology. This allows M3D to enable high-performance and energy-efficient systems through higher integration density, flexible partitioning of logic blocks across multiple layers, and significantly lower total wire-length. From a system design perspective, M3D is a breakthrough technology to achieve "More Moore and More Than Moore," and opens up the possibility of creating manycore chips with multi-tier cores and network routers by utilizing ILVs. Importantly, this allows us to create scalable manycore systems that can address the communication and computation needs of big data, graph analytics, and other data-intensive parallel applications. In addition, the dramatic reduction in via size and the resulting increase in density opens up numerous opportunities for design optimizations in the manycore domain. 1600 M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy-Efficient 3D IC Authors: Sebastien Thuries, Olivier Billoint, Sylvain Choisent, Didier Lattard, Romain Lemaire and Perrine Batude, CEA-Leti, FR 1630 Design of a Reliable Power Delivery Network for Monolithic 3D ICs Speaker: Krishnendu Chakrabarty, Duke University, US Authors: Shao-Chun Hung and Krishnendu Chakrabarty, Duke University, US 1700 Power-Performance-Thermal Trade-offs in M3D-Enabled Manycore Chips Speaker: Partha Pande, Washington State University, US Authors: Shouvik Musavvir¹, Anwesha Chatterjee¹, Ryan Kim², Daehyun Kim¹, Janardhan Rao Doppa¹ and Partha Pratim Pande¹ ¹Washington State University, US; ²Colorado State University, US