M02 OpenCL design flows for Intel and Xilinx FPGAs - common optimization strategies, design patterns and vendor-specific differences

Agenda

Time	Label	Session
13:30	M02.1	Tutorial and Conference Registration
14:00	M02.2	Tutorials start
14:00	M02.3	OpenCL and FPGA design: common constructs and patterns Speaker: Tobias Kenter, Paderborn Center for Parallel Computing, DE
14:40	M02.4	Key differences between Intel FPGA and Xilinx tools: outer loop pipelining, local memory ports and replication Speaker: Tobias Kenter, Paderborn Center for Parallel Computing, DE
15:30	M02.5	Coffee Break for Tutorials
16:00	M02.6	Simple, yet efficient matrix multiplication designs with OpenCL Chair: Tobias Kenter, Paderborn Center for Parallel Computing, DE Design example with Xilinx SDAccel Design example with Intel FPGA SDK for OpenCL Discussion of the used abstraction levels: what do we want the compile to infer, what do we want to express explicitly?
17:10	M02.8	OpenCL FPGA success stories, complex design examples, libraries Speaker: Tobias Kenter, Paderborn Center for Parallel Computing, DE
18:00	M02.7	Tutorials end
18:00	M02.9	Welcome Reception & PhD Forum