M01 Applications of Machine Learning in Semiconductor Manufacturing and Test Room 4 1400 - 1800 Organisers:Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR Yiorgos Makris, University of Texas at Dallas, US Throughout the lifetime of an integrated circuit, a wealth of data is collected for ensuring its robust and reliable operation. Ranging from design-time simulations to process characterization monitors, and from high-volume specification tests to diagnostic measurements on customer returns, the information inherent in this data is invaluable. Mining this information using machine learning methods has seen intense interest and numerous breakthroughs in recent years. This tutorial seeks to elucidate the utility of machine learning in semiconductor manufacturing and test. Relevant concepts from machine learning will be introduced, agglomerated with current practice, and showcased using industrial data. Recommendations for practitioners will also be given. M01.1 Tutorial and Conference Registration 13:30 - 17:51 M01.2 Tutorials start 14:00 - 17:51 M01.3 Introduction and Motivation 14:00 - 14:20 Speakers:Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR Yiorgos Makris, The University of Texas at Dallas, US Part I will motivate the need, the challenges, and the benefits of using machine learning and will discuss its utility on actual test- and yield-related industrial problems. We will give an abstract representation of problems that can be tackled using machine learning. We will also illustrate the link between machine learning and semiconductor manufacturing and test. M01.4 Overview of Machine Learning Applications in Semiconductor Manufacturing and Test 14:20 - 15:30 Speaker:Yiorgos Makris, The University of Texas at Dallas, US Part II will provide a concise and comprehensive overview of applications of machine learning in semiconductor manufacturing and test. For each application, we will define the problem, we will explain how machine learning can come to the rescue, and we will show a case study on industrial datasets. Applications include: alternate test for analog/mixed-signal/RF ICs, test compaction, fault diagnosis, yield learning, post-manufacturing tuning, outlier detection, adaptive test, wafer-level spatial & lot-level spatiotemporal correlation modeling, analog test metrics estimation, neuromorphic on-chip testers, hotspot detection, board-level fault diagnosis, trimming, die inking, pre-silicon verification and post-silicon validation, yield estimation in fab-to-fab migration, yield estimation when transitioning from one design generation to the next. M01.5 Coffee Break for Tutorials 15:30 - 16:00 M01.6 Recommendations for Practitioners 16:00 - 16:45 Speaker:Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR Part III will illustrate the main practical issues when applying machine learning techniques. It will provide several recommendations based on the presenters' own experience in developing several applications in the past. Practical issues that will be discussed include: types of learning machines, feature extraction, feature selection, training and validation processes, dataset preparation, limited and unbalanced datasets, non-stationary datasets, metrics for generalization error, mitigating the generalization error, explainable artificial intelligence. M01.7 Selected Applications in Depth 16:45 - 17:45 Speakers:Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR Yiorgos Makris, The University of Texas at Dallas, US Part IV will describe in more detail selected applications of machine learning in semiconductor manufacturing and test. We will delve into the following four mainstream applications: alternate test for analog/mixed-signal/RF ICs, adaptive test, yield learning, and hotspot detection. For each application we will discuss the collection of training data, the choice of learning models, the training procedures, etc., and we will provide several cases studies on actual industrial data. M01.8 Emerging Applications 17:45 - 18:00 Speaker:Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR Part V will discuss emerging applications. In particular, we will discuss whether deep learning methods open new opportunities for solving efficiently test and semiconductor manufacturing problems. We will also discuss the "inverse" problem of testing machine learning hardware. In particular, we will discuss to what extent testing machine learning hardware is any different from testing any regular integrated circuit. We will also discuss fault tolerance methods that gain interest thanks to the integration of machine learning hardware in autonomous vehicles and systems. M01.9 Tutorials end 18:00 - 17:51 M01.10 Welcome Reception & PhD Forum 18:00 - 21:00 M02 OpenCL design flows for Intel and Xilinx FPGAs - common optimization strategies, design patterns and vendor-specific differences Room 9 1400 - 1800 Organiser:Tobias Kenter, University of Paderborn, DE An increasing fraction of new results in the reconfigurable computing domain are obtained with the help of high level synthesis tools. Among the more popular tools are the OpenCL based Xilinx SDAccel and Intel FPGA SDK for OpenCL. Since they are building upon the same programming model and source language, one would hope for portability between different OpenCL based FPGA designs. However, the vast majority of published research is only optimized for one vendor tool and FPGA family. In their dissemination and training activities, both vendors focus on promoting effective design patterns with their respective tools and for their respective hardware. In this tutorial, we want to broaden that scope and provide training for both tool chains. During two years of PostDoc research, the workshop organizer has gained extensive experience and insights into these tools. This tutorial will contain step by step optimization examples with performance models based on analysis of generated reports and complemented with measurements and profiling data. We will present design patterns that work well for both tools and thus can promote portability of OpenCL based FPGA designs, but also shed light on differences. Based on examples, we will illustrate the central difference in pipelining of nested loops, which has implications on local memory ports, replication and predictability of design space exploration. M02.1 Tutorial and Conference Registration 13:30 - 17:51 M02.2 Tutorials start 14:00 - 17:51 M02.3 OpenCL and FPGA design: common constructs and patterns 14:00 - 14:40 Speaker:Tobias Kenter, Paderborn Center for Parallel Computing, DE M02.4 Key differences between Intel FPGA and Xilinx tools: outer loop pipelining, local memory ports and replication 14:40 - 15:30 Speaker:Tobias Kenter, Paderborn Center for Parallel Computing, DE M02.5 Coffee Break for Tutorials 15:30 - 16:00 M02.6 Simple, yet efficient matrix multiplication designs with OpenCL 16:00 - 17:10 Chair:Tobias Kenter, Paderborn Center for Parallel Computing, DE Design example with Xilinx SDAccel Design example with Intel FPGA SDK for OpenCL Discussion of the used abstraction levels: what do we want the compile to infer, what do we want to express explicitly? M02.8 OpenCL FPGA success stories, complex design examples, libraries 17:10 - 18:00 Speaker:Tobias Kenter, Paderborn Center for Parallel Computing, DE M02.7 Tutorials end 18:00 - 17:51 M02.9 Welcome Reception & PhD Forum 18:00 - 21:00 M03 A Comprehensive Analysis of Approximate Computing Techniques: From Component- to Application-Level Room 5 1400 - 1800 Organisers:Daniel Menard, INSA Rennes/IETR, FR Alberto Bosio, INL, FR Olivier Sentieys, INRIA, FR A new design paradigm, Approximate Computing (AxC), has been established to investigate how computing systems can be more energy efficient, faster, and less complex. Intuitively, instead of performing exact computation and, consequently, requiring a high amount of resources, AxC aims to selectively relax the specifications, trading accuracy off for efficiency. It has been demonstrated in the literature the effectiveness of imprecise computation for both software and hardware components implementing inexact algorithms, showing an inherent resiliency to errors. This tutorial introduces basic and advanced topics on AxC. We intend to follow a bottom-up approach: from component, up to application-level. More in detail, we will first present existing approximate computing techniques according to three levels: hardware, data and computation. At hardware level, functional approximation through inexact operators and voltage over-scaling will be detailed. At data level, approximation can be carried-out by using efficient arithmetic, precision scaling, less data or less-up-to-date data. We will present some compile-time results in terms of energy-efficiency, area, performance versus accuracy of computations when using customized arithmetic (fixed-point, floating-point) and also, we will try to derive some conclusions by comparing the different paradigms. At computation level, algorithmic transformations are used to reduce complexity by skipping or approximating parts of the processing. The concepts of loop perforation, early termination, memoïzation, and computation approximation will be detailed. The second part of the tutorial is dedicated to methods and tools to exploit efficiently approximate computing. First of all, the different approaches to analyze approximation effects on application quality will be described. Then the complex problem of word-length optimization for fixed-point and floating-point is considered. Finally, the different frameworks for design space exploration will be detailed. The last part of the tutorial is devoted to present how AxC paradigm can be exploited in the context of safety-critical applications. More in particular, the tutorial will show how design efficient and low-cost fault tolerance mechanisms. The outline of the presentation is as follows General introduction Motivations Techniques for approximate computing Data level approximation Hardware level approximation Computation level approximation Methods and tools for approximate computing Analysis of approximation effect on application quality Word-length optimization for fixed-point and floating-point Design space explorationGeneral introduction Motivations Approximate Computing for Safety-Critical Applications Analysis of approximation effect on application quality Word-length optimization for fixed-point and floating-point Design space explorationGeneral introduction Motivations M03.1 Tutorial and Conference Registration 13:30 - 17:51 M03.2 Tutorials start 14:00 - 17:51 M03.3 Coffee Break for Tutorials 15:30 - 16:00 M03.4 Tutorials end 18:00 - 17:51 M03.5 Welcome Reception & PhD Forum 18:00 - 21:00 M04 Hardware-based Security Solutions for the Internet of Things Room 6 1400 - 1800 Organiser:Basel Halak, University of Southampton, GBChair:Basel Halak, University of Southampton, GBCo-Chair:Maire O'Neill, Queen's University Belfast, GBSpeakers:Basel Halak, University of Southampton, GB Maire O'Neill, Queen's University Belfast, GB Yier Jin, The University of Central Florida, US Gang Qu, University of Maryland, College Park, US M04.1 Tutorial and Conference Registration 13:30 - 17:51 M04.2 Chair Introduction 14:00 - 14:05 Chair:Basel Halak, University of Southampton, GB The security of the internet of things is one of the major challenges facing both engineers and researcher alike. This technology has led to billions of low power devices to become entrenched in our lives. Reports state that currently 15 billion IoT devices are currently deployed, and deployment is expected to reach 50 billion by the year 2020. This massive deployment of devices has led to significant security concerns. Various attacks have shown weaknesses in IoT infrastructure, with a swarm of light bulbs potentially leaving a city in darkness, rogue devices attacking infrastructure to attacks in critical infrastructure. This tutorial a combined effort of four leading international universities in the field of hardware-based IoT security, it aims to disseminate the latest research results and state-pf the art-techniques in this field DATE community. The tutorial will be highly beneficial for both experienced researchers and students considering delving into this topic. The tutorial has the following objectives; To describe the security challenges of internet of things devices To explain the basics of attestation techniques for IoT devices To explain the principles of lightweight authentications techniques To explain the design principles of Physically Unclonable Functions To Describe open research problems in the area of designing hardware-security schemes for IoT applications. M04.3 Hardware based Lightweight Authentication for IoT Application 14:05 - 14:45 Speaker:Gang Qu, Univ. of Maryland, College Park, US In many embedded systems and the Internet of Things (IoT) applications, resources like CPU, memory, and battery power are limited that they cannot afford the classic cryptographic security solutions. Meanwhile, the security requirement on these systems/devices is not as high as the traditional secure systems. In this talk, we use authentication as an example to demonstrate how hardware and physical characteristics can help to build lightweight security primitives such as authentication protocols. More specifically, we will report our recent work that utilizes the traditional CMOS, the emerging RRAM technologies, and voltage over scaling (VoS) technique for user and device authentication as well as GPS spoofing detection. These practical approaches are promising alternatives for the classical crypto-based authentication protocols for the embedded and IoT devices in the smart world. M04.4 Device Attestation for IoT and Resources-Constrained Systems 14:45 - 15:30 Speaker:Yier Jin, The University of Central Florida, US In recent years we have seen a rise in popularity of networked devices. As a consequence, a need to ensure secure and reliable operation of these devices has also risen. Device attestation is a promising solution to the operational demands of embedded devices, especially those widely used in Internet of Things (IoT) and Cyber-Physical System (CPS). In this tutorial, we summarize the basics of device attestation. We then present a summary of attestation approaches by classifying them based on their functionality and reliability guarantees they provide to networked devices. Lastly, we discuss the limitations and potential issues current mechanisms exhibit and propose new research directions. M04.5 Coffee Break for Tutorials 15:30 - 16:00 M04.6 Securing IoT Devices using Physically Unclonable Functions 16:00 - 16:45 Speaker:Basel Halak, University of Southampton, GB Physically Unclonable Functions (PUFs) exploit the intrinsic manufacturing process variations to generate a unique signature for each silicon chip; this technology allows building lightweight cryptographic primitive suitable for resource-constrained IoT devices. The first part of this tutorial provides a comprehensive overview on the design principles of physically unclonable functions and their main evaluation metrics. The second part explains why we need the PUF technology and how to use it to build robust defense mechanisms against emerging security threats facing IoT technologies, in this context, we give specific examples that includes; secure cryptographic keys generation/storage, authentication protocols, and low cost secure sensors. The final part of this tutorial outlines the outstanding security challenges facing PUF technology and their potential countermeasures, including mathematical modelling attacks using machine-learning algorithms, side channel attacks and physical cloning attacks. The tutorial concludes with a summary of learned lessons and directions for the future M04.7 Practical Design Guidelines PUF using FPGA 16:45 - 17:30 Speaker:Maire O'Neill, Queen's University Belfast, GB A Physical unclonable function (PUF) is a security primitive which enables the extraction of a digital identifier from electronic devices, based on the inherent silicon variation between devices which occurs during the manufacturing process. Many PUF implementations for ASICs and FPGAs have been proposed to date. However, on FPGA they often offer insufficient uniqueness and reliability, and consume excessive FPGA resources. This talk will focus on how to design efficient, lightweight and scalable PUF identification (ID) generator circuits specifically for FPGAs that offer compact designs, high uniqueness and good reliability. It will also discuss the challenges in designing challenge-response PUF circuits on FPGAs, including their vulnerability to machine-learning attacks. This talk will focus on how to design efficient, lightweight and scalable PUF identification (ID) generator circuits specifically for FPGAs that offer compact designs, high uniqueness and good reliability. It will also discuss the challenges in designing challenge-response PUF circuits on FPGAs, including their vulnerability to machine-learning attacks.M05 Safety and Security in Automotive 2.0 Era Room 8 1400 - 1800 Organiser:Srivaths Ravi, Texas Instruments, INSpeakers:Prasanth Viswanathan Pillai, Texas Instruments, IN Srivaths Ravi, Texas Instruments, IN The increasing semiconductor consumption has been spurred by a revolution witnessed in the automotive industry. The integration of electronics and networking into conventional automobile driven by infotainment and ADAS a few years back is accelerated by megatrends of EV/HEV, autonomous driving and shared mobility. These trends, termed sometimes as "Automotive 2.0", drive various requirements into the semiconductors being sourced. Of these, safety and security requirements are becoming paramount due to their impact and liability. This tutorial leverages the authors' experiences in driving safety and security as a part of semiconductor development cycles. By breaking down complex system requirements into foundational ones at semiconductor level, the tutorial is intended to provide an accessible treatment of the subject for any semiconductor developer. M05.1 Tutorial and Conference Registration 13:30 - 17:51 M05.2 Tutorials start 14:00 - 17:51 M05.3 Introduction 14:00 - 17:51 PART A: Introduction starts with a brief overview of the top level trends in automotive and semiconductor industries that are driving various design requirements, including the emerging concerns of safety and security. M05.4 Automotive Functional Safety I 14:20 - 17:51 PART B: Automotive Functional Safety I is the first of a two part module on automotive functional safety for a semiconductor developer. Using the presenters' experience in leading functional safety compliant chip development and certification, the module examines various aspects of the automotive functional safety standard ISO 26262 and its parent industrial safety standard IEC61508. We start with the foundations of functional safety including key terminology and metrics, safety compliant development process for HW/SW, component and system level safety mechanisms, and qualitative safety analysis. M05.5 Coffee Break for Tutorials 15:30 - 16:00 M05.6 Automotive Functional Safety II 16:00 - 17:51 PART C: Automotive Functional Safety II is the second of a two part module on automotive functional safety for a semiconductor developer. This module first covers the various techniques that are used in the quantitative safety analysis phase that follows qualitative safety analysis. We then survey the readiness of safety EDA ecosystem today from the eyes of a semiconductor developer. We conclude with emerging functional safety topics of interest and review the key changes in the 2nd edition of ISO26262. M05.7 Automotive Security: Moving from Ad-hoc to Standards 16:50 - 17:51 PART D: Automotive Security: Moving from Ad-hoc to Standards is a module crafted to share the latest knowhow from a rapidly evolving domain - automotive security. The module starts with a detailed look at attack surface of an automobile and the various threat "opportunities". Then, we survey the foundational HW/SW mechanisms necessary to secure automotive electronics and also review emerging standards for secure automotive semiconductor development. Finally, we examine the curious relationship of security and safety that designers need to grapple with. M05.8 Tutorials end 18:00 - 17:51 M05.9 Welcome Reception & PhD Forum 18:00 - 21:00 M07 Quantum Computing, intro to IBM Q and Qiskit Room 7 1400 - 1800 Organisers:Leon Stok, IBM, US SheshaShayee Raghunathan, IBM, INSpeakers:Leon Stok, IBM, US SheshaShayee Raghunathan, IBM, IN Robert Perricone, IBM, US Though early in its development, quantum computing is now available on real hardware via the cloud through IBM Q. This radically new kind of computing holds open the possibility of solving some problems that are now and perhaps always will be intractable for "classical" computers. In this talk we'll discuss the motivation for quantum computing and the types of problems to which it might be applied. We'll describe the basics of the technology and show where we are in the timeline toward reaching quantum advantage: the point where quantum computing shows demonstrable and significant advantage over classical computers and algorithms. We'll continue by describing the no-charge IBM Q Experience where more than 90,000 people have used IBM's offerings to to learn and experiment with quantum computing. We will give an hands-on introduction to Qiskit and show how to run several quantum programs on IBM Q and simulator systems. Feel free to look at: https://qiskit.org beforehand. Please bring your own laptop for the hands-on Qiskit experience. Requirements Please make sure you bring your laptop along. Please create an account with IBM Q Experience if you have not done so already. Visit: https://quantumexperience.ng.bluemix.net/qx If you don't have an account, create an account using "Sign Up". The account is free. Generate an API token in IBM Q Experience Visit: https://quantumexperience.ng.bluemix.net/qx Login using your ID After successfully logging in, click on person icon at top right corner Select "My Account" from the dropdown list Click on "Advanced" tab "API Token" section should now be visible Click on "Generate" button This will populate the field above the "Generate" button. This string is your API token. The API token is needed when we want to run our program in quantum hardware. We will talk about how to set it up in our tutorial. Optional setup While we plan to use web-based deployment model in our session (and therefore we don't require you to install anything), we however recommend installing Qiskit locally in your respective laptops. This is for couple of reasons: Having a local copy and install enables you to take the learnings from the tutorial to start doing development after the session Should there be any issues, we can help you out; if we can't resolve it during the event, we will take note of the issue and will put you in touch with appropriate expert. Install Qiskit locally Please follow the installation process described in the following link: https://github.com/Qiskit/qiskit-tutorials/blob/master/INSTALL.md. References Qiskit https://qiskit.org/ https://github.com/qiskit https://www.youtube.com/channel/UClBNq7mCMf5xm8baE_VMl3A https://www.research.ibm.com/ibm-q/ Python https://www.python.org/ https://www.oreilly.com/ideas/10-top-python-resources-on-oreillys-online-learning-platform https://courses.cognitiveclass.ai/login?next=/courses/course-v1%3ACognitiveclass%2BPY0101EN%2Bv2/info Jupyter notebook https://www.datacamp.com/community/tutorials/tutorial-jupyter-notebook https://jupyter-notebook-beginner-guide.readthedocs.io/en/latest/ https://jupyter.readthedocs.io/en/latest/ https://www.codecademy.com/articles/how-to-use-jupyter-notebooks Git and Github https://guides.github.com/ https://www.youtube.com/githubguides https://www.tutorialspoint.com/git/ Contacts SheshaShayee Raghunathan (shesha.raghunathan@in.ibm.com) Leon Stok (leonstok@us.ibm.com) M07.1 Tutorial and Conference Registration 13:30 - 17:51 M07.2 Tutorials start 14:00 - 17:51 M07.3 Coffee Break for Tutorials 15:30 - 16:00 M07.4 Tutorials end 18:00 - 17:51 M07.5 Welcome Reception & PhD Forum 18:00 - 21:00