W01 The 5th International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS) Room 3 0830 - 1700 General Co-Chairs:Jiang Xu, Hong Kong University of Science and Technology, HK Mahdi Nikdast, Colorado State University, US Gabriela Nicolescu, Ecole Polytechnique de Montréal, CAProgramme Committee Chair:Sébastien Le Beux, Lyon Institute of Nanotechnology, FRProgramme Committee Members:Alan Mickelson, University of Colorado Boulder, US Ayse Coskun, Boston University, US Nikos Hardavellas, Northwestern University, US Olivier Sentieys, INRIA, FR Tohru Ishihara, Kyoto University, JP Yaoyao Ye, Shanghai Jiao Tong University, CN José Abellán, Universidad Católica de Murcia (UCAM), ES Yoan Léger, CNRS – FOTON, FR Workshop Focus As Moore's Law is slowing down, an exploration of alternative technologies are developed to replace traditional CMOS-based architectures at the heart of data processing. Moreover, stringent application constraints on massive data transfers in data centers, artificial intelligence systems, and embedded high-performance computing (eHPC), requires new communication-centric systems with novel interconnect technologies. Silicon photonics is a prime candidate to achieve this thanks to its compatibility with CMOS fabrication process, scalability, and growing maturity. OPTICS aims at discussing the most recent advances in silicon photonics for computing systems, covering topics from the device fabrication all the way up to the system-level design through circuit optimization with Electronic-Photonic Design Automation (EPDA). The workshop is of interest to researchers working on silicon photonics, high-performance computing systems and EDA/EPDA. It is comprised of invited talks of the highest caliber from industry and academia addressing most recent outcomes. Ideas and new opportunities are discussed during a panel and a refereed poster presentations session highlights works-in progress. Topics to be discussed include but are not limited to: EPDA (Electronic-Photonic Design Automation): non-uniformity/thermal aware design, floor-planning, crosstalk-aware interconnects modeling and simulation, etc. Inter/Intra-chip Interconnects: hybrid optical-electronic interconnects, passive/active-based optical switched networks, communication protocols, I/O design etc. Applications: embedded high-performance computing, data center, reservoir computing, all-optical logic gates, etc. Silicon Photonics Devices and Circuits: circuit demonstrator, on-chip lasers, photodetectors, electro-optic modulators, optical switches, athermal devices, etc. General Chairs Jiang Xu, Hong Kong University of Science and TechnologyMahdi Nikdast, Colorado State University Gabriela Nicolescu, Polytechnique Montréal Program Chair Sébastien Le Beux, Lyon Institute of Nanotechnology W01.1 Registration Desk opens 07:30 - 08:30 W01.2 Workshops start 08:30 - 08:30 W01.3 Introduction to OPTICS 08:30 - 08:40 W01.4 From system level simulations to silicon photonic circuit fabrication 08:40 - 10:00 08:40 - 09:40 (Keynote) Vladimir Stojanovic, UC Berkeley (US)EPDA for EPSoC design: From co-simulation to photonic circuit generators 09:40 - 10:00 (invited) Jean Christophe Crebier, CMP (FR)MPW services for Photonics & ICs prototyping W01.5 Coffee break 1 10:00 - 10:30 W01.6 Silicon Photonics for on-chip interconnects, IO and computing 10:30 - 11:50 10:30-10:50 (invited) Timo Aalto, VTT (Finland)3 µm and 12 µm SOI platforms for optical interconnects and I/O coupling 10:50-11:10 (invited) Fabio Pavanello, IMEC (BE)Electronics-photonics integration in advanced CMOS platforms using a photonics module: a transceiver application in 65 nm bulk CMOS 11:10-11:30 (invited) Bert Offrein, IBM Zurich (CH)Advancing silicon photonics for traditional and novel computing paradigms 11:30-11:50 (invited) Jun Shiomi, Kyoto University (JP)Integrated Optical Neural Networks Exploiting Light Speed Approximate Parallel Multipliers W01.7 Poster Presentation (session 1) 11:50 - 12:00 Design Automation for Wavelength-Routed Optical NoCs Tsun-Ming Tseng, Ulf Schlichtmann, TUM (DE) High-Radix Nonblocking Integrated Optical Switching Fabric for Data Center Zhifei Wang, Jiang Xu, Peng Yang, et al., HKUST (CN) Integrated spiking nanolaser Maxime Delmulle, Sylvain Combrié, Fabrice Raineri and Alfredo De Rossi, Thales and Research Technology (FR) and C2N (FR) RSON: an Inter/Intra-Chip Silicon Photonic Network for Rack-Scale Computing Systems Peng Yang, Zhifei Wang, Zhehui Wang and Jiang Xu, HKUST (CN) Hardware Emulation Platform of Optical Network-on-Chip Lucien Del Bosque, Ian O'ConnoR, Sébastien Le Beux, ECL (FR) BOSIM: Holistic Optical Switch Models for Silicon Photonic Networks Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, et al., HKUST (CN) and Intel (US) Stochastic Computing with Integrated Optics Hassnaa El-Derhalli, Sébastien Le Beux, Sofiene Tahar, Concordia University (CA) W01.8 Lunch break 12:00 - 13:00 W01.9 New Devices for New Architectures 13:00 - 14:20 13:00-13:20 (invited) Laurent Vivien, C2N (FR) Recent advances in silicon photonics 13:20-13:40 (invited) Christophe Peucheret, Foton (FR) Mode division multiplexing for optical networks on chip - potential and limitations 13:40-14:00 (invited) Fabrice Raineri, Paris-Sud University (FR)III-V semiconductor on silicon nanodevices for high performance computing 14:00-14:20 (invited) Zheng Zhao, Zhoufeng Ying, Ray T. Chen, and David Z. Pan, The University of Texas at Austin (US) Hardware-software Co-design of Optical Neural Networks W01.10 Poster presentation (session 2) 14:20 - 14:30 FODON: Ultra-High-Radix Low-Loss Optical Switching Fabric Zhifei Wang, Zhehui Wang, Jiang Xu, et al., HKUST (CN) All-optical sampling with hybrid III-V on Silicon nano-resonators for photonic computing Léa Constans, Sylvain Combrié, Fabrice Raineri and Alfredo De Rossi, Thales and Research Technology (FR) and C2N (FR) MOCA: an Inter/Intra-Chip Optical Network for Memory Zhehui Wang, Jiang Xu, Zhifei Wang, et al., HKUST (CN) Enabling System-Level Design with Optical Nrworks-On-Chip Through Architecture Integration and Topology Synthesis Mahdi Tala, Maddalena Nonato, Oliver Schrape, et al., University of Ferrara (IT) and IHP Microelectronics (DE) Quantitative Analysis of Optical/Electrical Interconnects and Optical-Electrical Interfaces Zhehui Wang, Jiang Xu, Zhifei Wang, et al., HKUST (CN) Light Up your Many Core Clément Zrounba, Sébastien Le Beux, Ian O'Connor, ECL (FR) Crosstalk Noise Reduction through Adaptive Power Control in Inter/Intra-Chip Optical Networks Luan Huu Kinh Duong, Peng Yang, Zhifei Wang, etal., HKUST (CN) W01.11 Coffee break 2 14:30 - 15:00 W01.12 Toward large scale on-chip optical interconnects 15:00 - 16:20 15:00-15:20 (invited) Umar Khan, IMEC (BE) Designing large-scale photonic integrated circuits 15:20-15:40 (invited) Ulf Schlichtmann, TUM (DE)EDA for WRONoCs: From Topology to Physical Design, and Breaking Down Barriers 15:40-16:00 (invited) Aditya Narayan, Boston University (US) A System-Level Perspective on Silicon Photonic Network-on-Chips 16:00-16:20 (invited) Cédric Killian, IRISA/INRIA (FR) ONoCs: from offline optimization to run time adaptability W01.13 Panel: Bringing on-chip optical interconnects into the real world 16:20 - 17:20 Davide Bertozzi, University of Ferrara (IT), chairIan O'Connor, ECL (FR) Yvain Thonnart, CEA-Leti (FR) Laurent Vivien, C2N (FR) Vladimir Stojanovic, UC Berkeley (US)Panelists: W01.14 Concluding Remarks and Closing Session 17:20 - 17:30 W01.15 Workshops end 17:30 - 17:30 W02 Recent Trends in Memristor Science & Technology: the journey from single memristor device towards 100 trillion synapses of brain Room 2 0830 - 1700 Organisers:Kyeong-Sik Min, Kookmin University, KR Ronald Tetzlaff, Technische Universität Dresden, DE Fernando Corinto, Politecnico di Torino, IT AIM and FOCUS This workshop focuses on Recent Trends in Memristor Science & Technology: the journey from single memristor device towards 100 trillion synapses of brain. Memristors were predicted theoretically in 1971 and demonstrated experimentally in 2008. Since then, a lot of researches have been done to develop memristor technology for possible uses of non-volatile memories, analog circuits, computing logics, neuromorphic systems, etc. In this special workshop of memristor science and technology, we have some invited talks about the recent state-of-the-art techniques of memristor circuits & systems, integration, fabrication, etc. We also discuss how memristor-based neuromorphic systems can mimic human brain's neuronal architecture with ~1011 neurons and ~1014 synapses for realizing future neuromorphic systems. We hope that this workshop can be a premier forum, where we review the recent challenges of memristor technology and discuss future possibility of artificial-intelligence hardware which can be based on memristor science and technology. KEYNOTE and INVITED SPEAKERS Leon O. Chua, Berkeley, USA. He is widely known for his invention of the memristor and the Chua's Circuit. His research has been recognized internationally through numerous major awards, including 16 honorary doctorates from major universities in Europe and Japan, and 7 U.S. patents. He was elected as a foreign member of the European Academy of Sciences (Academia Europea) in 1997, a foreign member of the Hungarian Academy of Sciences in 2007, and an honorary fellow of the Institute of Advanced Study at the Technical University of Munich, Germany, in 2012. He was honored with many major prizes, including the Frederick Emmons Award in 1974, the IEEE Neural Networks Pioneer Award in 2000, the first IEEE Gustav Kirchhoff Award in 2005, the Guggenheim Fellow award in 2010, Leverhulme Professor Award (United Kingdom) during 2010-2011, and the EU Marie Curie Fellow award, 2013. Prof. Chua is a Recipient of the top 15 most cited authors Award in 2002 from all fields of engineering published during the 10-year period 1991 to 2001, from the Current Contents (ISI) database. Daniele Ielmini, Politecnico Milano, Italy. He received the Laurea (cum laude) and Ph.D. in Nuclear Engineering from Politecnico di Milano in 1995 e 2000, respectively. He is a Full Professor at the Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, after appointments as Assistant Professor in 2002 and Associate Professor in 2010. He held visiting positions at Intel Corporation (2006), Stanford University (2006) and the University of Illinois at Urbana-Champaign (2010). His research interests include the modeling and characterization of non-volatile memories, such as nanocrystal memory, charge trap memory, phase change memory (PCM), resistive switching memory (RRAM), and spin-transfer torque magnetic memory (STT-MRAM). In 2016, he coedited the book 'Resistive switching - from fundamental redox-processes to device applications' for Wiley-VCH. He authored/coauthored 8 book chapters, more than 250 papers published in international journals and presented at international conferences, and 6 patents. His works received more than 5300 citations, with an H-index of 41 (Scopus, October 2016). He has served in several Technical Subcommittees of international conferences, such as IEEE-IEDM (2008-2009), IEEE-IRPS (2006-2008), IEEE-SISC (2008-2010), INFOS (2011-2017), ISCAS (2016-2017) and DATE (2017). He is a Senior Member of the IEEE. He was recognized a Highly Cited Researcher by Thomson Reuters in 2015. He received the Intel Outstanding Researcher Award in 2013, the ERC Consolidator Grant in 2014, and the IEEE-EDS Paul Rappaport Award in 2015. Hyunsang Hwang received his Ph.D. in Materials Science from the University of Texas at Austin, USA in 1992. After five years at LG Semicon as a senior researcher, he became a Professor of Materials Science and Engineering at Gwangju Institute of Science and Technology (GIST), South Korea in 1997. Since 2012, he has been a Professor at Pohang University of Science and Technology (POSTECH), South Korea. He has published more than 360 journal papers and 32 IEDM/VLSI technology papers. His current research interests include neuromorphic device, ReRAM and selector devices. Wei Lu, Univ. of Michigan. His research interest includes high-density memory based on two-terminal resistive devices (RRAM), memristors and memristive systems, neuromorphic circuits, aggressively scaled nanowire transistors, and other emerging electrical devices. He received his B.S. (1996) and Ph.D (2003) in physics from Tsinghua University, Beijing, China, and Rice University, Houston, TX respectively. From 2003 to 2005, he was a postdoctoral research fellow at Harvard University, Cambridge, MA. He joined the faculty of the University of Michigan in 2005 and is currently a Professor and Director of the Lurie Nanofabrication Facility. He is an IEEE Fellow, Associate Editor for Nanoscale, a recipient of the NSF CAREER Award in 2009, EECS Outstanding Achievement Award in 2012, 2014-15 Rexford E. Hall Innovation Excellence Award, and the 2016-2017 David E. Liddle Research Excellent Award. To date he has published over 100 journal papers that have received over 20,000 citations with an h-factor of 61 ( Google Scholar ). Prof. Lu is currently advising 11 Ph.D. students and 3 Postdocs. He is also co-founder and Chief Scientist of Crossbar Inc, a Silicon Valley semiconductor company with over $100M VC funding to date to develop next generation non-volatile memories. Said Hamdioui, TU Delft, Netherlands. He received the MSEE and PhD degrees (both with honors) from the Delft University of Technology, Delft, The Netherlands. He is currently with the Delft University of Technology. He has more than eight years of experience in industry and academia as a consultant and/or as researcher and developer on test issues in general and memory testing in particular. He spent a couple of years with Intel Corporation in Santa Clara and Folsom, California, where he was responsible for developing new low-cost and efficient test solutions for advanced Intel single-port and multiport embedded cache designs in the new generations of microprocessors. In addition, he spent more than one and half years with Philips Semiconductors in France and The Netherlands, where he was responsible for driving advanced product debug and yield ramp activities and for developing systematic ways of reducing the time in yield improvement for advanced semiconductor memories. Dr. Hamdioui is the author of a book and about 40 conference and journal papers in the area of testing; many of them are the result of cooperation with industrial partners (e.g., Intel, ST, Infineon, etc). His research interests include VLSI test and reliability, deep-submicron CMOS IC design and test, systematic fault modeling, test generation and optimization for semiconductor memories, design for testability, BIST, yield enhancement, product engineering, etc. He was the recipient of the European Design Automation Association (EDAA) Award for 2001. He is a member of the IEEE. Abu Sebastian, IBM Zurich. He is a Principal Research Staff Member and Master Inventor at IBM Research - Zurich. He received a B. E. (Hons.) degree in Electrical and Electronics Engineering from BITS Pilani, India, in 1998 and M.S. and Ph.D. degrees in Electrical Engineering (minor in Mathematics) from Iowa State University in 1999 and 2004, respectively. He was a contributor to several key projects in the space of storage and memory technologies and currently leads the research effort on in-memory computing at IBM Zurich. Dr. Sebastian is a co-recipient of the 2009 IEEE Control Systems Technology Award and the 2009 IEEE Transactions on Control Systems Technology Outstanding Paper Award. In 2013 he received the IFAC Mechatronic Systems Young Researcher Award for his contributions to the field of mico-/nanoscale mechatronic systems. In 2015 he was awarded the European Research Council (ERC) consolidator grant. Dr. Sebastian served on the editorial board of the journal, Mechatronics from 2008 till 2015 and served on the memory technologies committee of the IEDM from 2015-2016. Mirko Prezioso, Mentium Technologies Inc., Santa Barbara, USA. He received the M.S. degree in theoretical condensed matter physics and the Ph.D. degree in advanced materials science and technology from the University of Parma, Parma, Italy, in 2004 and 2008, respectively. Since 2013, he has been a Research Assistant Professor with the University of California at Santa Barbara, Santa Barbara, CA, USA, where he has been working on memristors and neuromorphic hardware. Qiangfei Xia, University of Massachusetts, Amherst, USA. Dr. Qiangfei Xia is a professor of Electrical & Computer Engineering at UMass Amherst and head of the Nanodevices and Integrated Systems Lab . He received his Ph.D. in Electrical Engineering in 2007 from Princeton University, where he was a recipient of the Guggenheim Fellowship in Engineering (a graduate fellowship from Princeton). He then spent three years as a research associate in the Hewlett Packard Laboratories in Palo Alto, California. In October 2010, he joined the faculty of UMass Amherst as an assistant professor (tenure clock started in January 2011). He was promoted to an associate professor with tenure in January 2016 and then a full professor in September 2018. Dr. Xia's research interests include beyond-CMOS devices, integrated systems and enabling technologies, with applications in machine intelligence, reconfigurable RF systems and hardware security. He has received a DARPA Young Faculty Award (YFA), an NSF CAREER Award, and the Barbara H. and Joseph I. Goldstein Outstanding Junior Faculty Award. Dr. Xia teaches freshman to graduate level courses, including Introduction to Electrical and Computer Engineering (ENGIN 112), Semiconductor Devices (ECE 344), Microelectronic Fabrication (ECE571) and Nanostructure Engineering (ECE 597/697NS). He was nominated for the Distinguished Teaching Award (DTA), a campus-wide highest honor to recognize exemplary teaching at UMass. Dr. Xia serves as a technical committee member for the International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN) conference, and the IEEE International Symposium on Circuits and Systems (ISCAS), to name a few. He was the co-program chair for the 14th International Conference on Nanoimprint & Nanoprint Technology (NNT). He is also an active panelist for U.S. and international funding agencies, and a peer reviewer for tens of international archival journals and conferences. Within UMass, his most notable service is the building of a brand new clean room facility in the Marcus Hall. He is a senior member of IEEE and SPIE. Kyeong-Sik Min, Kookmin Univ., Seoul, Korea. He received the B.S. degree in electronics and computer engineering from Korea University, Seoul, South Korea, in 1991, and the M.S.E.E. and Ph. D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 1993 and 1997, respectively. In 1997, he joined Hynix Semiconductor, Inc., where he was engaged in the development of low-power and high-speed DRAM circuits. From 2001 to 2002, he was a Research Associate with the University of Tokyo, Tokyo, Japan, where he designed low-leakage memories and low-leakage logic circuits. In September 2002, he joined the Faculty of Kookmin University, Seoul, South Korea, where he is currently a Professor in the School of Electrical Engineering. He was a Visiting Professor with the University of California, Merced, Merced, CA, USA, from August 2008 to July 2009. His research interests include low-power VLSI, memory design, and power IC design. He is a member of the Institute of Electronics Engineers of Korea, and the Institute of Electronics, Information, and Communication Engineers in Japan. He was on various technical program committees, such as Asian Solid-State Circuits Conference, International SoC Design Conference, and Korean Conference on Semiconductors. He and his students were the recipient of the IDEC CAD & Design Methodology Award (2011), IDEC Chip Design Contest Award (2011), and IDEC Chip Design Contest Award (2012). Fernando Corinto, Politecnico di Torino, Italy. He received the Laurea degree in electronics and the Ph.D. degree in electronics and communications engineering in 2001 and 2005, respectively, and the European Doctorate in 2005, all from the Politecnico di Torino, Torino, Italy. In 2004, he won a Marie Curie Fellowship (within the 'Marie Curie Actions' under the Sixth Framework Programme). He is currently an Assistant Professor of Circuit Theory with the Dipartimento di Elettronica, Politecnico di Torino. His research activities are mainly in the areas of nonlinear dynamical circuits and systems and locally coupled nonlinear/nanoscale networks. He is coauthor of more than 90 international journal and conference papers. He has been reviewer of several papers for international journals and conferences and chair of sessions in international conferences. He is the principal investigator of several research projects. Since 2010, he is Senior Member of the IEEE, Member of the IEEE CAS Technical Committees on Cellular Nanoscale Networks and Array Computing and Nonlinear Circuit and Systems. He is also Visiting Professor at PPCU of Budapest, since 2007. Dr. Corinto was the Technical Program Chair for the 13th Workshop on Cellular Nanoscale Networks and their Applications and 3rd Symposium on Memristor. Ronald Tetzlaff, TU Dresden, Germany. He is a Full Professor of Fundamentals of Electrical Engineering at Technische Universität Dresden, Germany. His scientific interests lie in the theory of signals and systems, system modelling and identification, Volterra systems, cellular nonlinear networks, and memristors. From 1999 to 2003 he was Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: REGULAR PAPERS. Prof. Tetzlaff was "Distinguished Lecturer" of the IEEE CAS Society (2001-2002). He is a member of the ITG, of the German Society of Electrical Engineers, and of the German URSI Committee. Alon Ascoli received a Ph.D. Degree in Electronic Engineering from University College Dublin in 2006. From 2006 to 2009 he worked as RFIC analog engineer at CSR Sweden AB. From 2009 to 2012 he was Research Assistant in the Department of Electronics and Telecommunications at Politecnico di Torino. Since 2018 he is Scientific Collaborator with the Department of Microelectronics, Brno University of Technology, Brno, Czech Republic. Since 2012 he is Scientific Collaborator in the Faculty of Electrical and Computer Engineering, Technische Universität Dresden, where he is currently pursuing a Habilitation in Fundamentals of Electrical Engineering. His research interests lie in the area of nonlinear circuits and systems, networks of oscillators, Cellular Nonlinear Networks and memristors. Dr. Ascoli was honored with the International Journal of Circuit Theory and its Applications (IJCTA) 2007 Best Paper Award. He acts as Secretary for the Cellular Nanoscale Networks and Array Computing Technical Committee (CNNAC) since May 2017. In April 2017 he was conferred the habilitation title as Associate Professor in Electrical Circuit Theory from the Italian Ministry of Education. In November 2017 he was conferred a Performance Bonus Award from Technische Universität Dresden. Since 2014 he is Management Committee Substitute for Germany in the COST Action IC1401 MemoCIS "Memristors - Devices, Models, Circuits, Systems, and Applications". He has been Program Chair and Special Session Chair for the 15th International Workshop on Cellular Nanoscale Networks and their Applications (CNNA) in 2016. He is the Technical Program Chair for the International Conference on Memristive Materials, Devices, and Systems (MEMRISYS) 2019. W02.1 Registration Desk opens 07:30 - 08:30 W02.2 Opening session 08:30 - 10:00 Chair:Kyeong-Sik Min, Kookmin University, KR 8:30-8:45 Opening session 8:45-10:00 (Keynote) Leon O. Chua, UC Berkeley, USA (Title: No Backtracking Rules the foundation of all non-volatile memristors, will be presented by Prof. Corinto, Politecnico di Torino, Italy) W02.3 Coffee break 1 10:00 - 10:30 W02.4 Morning session 10:30 - 12:00 Chair:Kyeong-Sik Min, Kookmin University, KR 10:30-11:00 (Invited) Daniele Ielmini, Politecnico Milano, Italy (Title: Emerging devices and circuits for analogue in-memory computing, will be presented by Dr. Zhong Sun, Politecnico Milano, Italy) 11:00-11:30 (Invited) Hyunsang Hwang, POSTECH, Korea (Title: Resistive switching based Synapse and Threshold switching based Neuron Devices for neuromorphic system) 11:30-12:00 (Invited) Wei Lu, Univ. of Michigan, USA (Title: RRAM foundations for neuromorphic and in-memory computing systems) W02.5 Lunch break 12:00 - 13:00 W02.6 Afternoon session#1 13:00 - 14:30 Chair:Fernando Corinto, Politecnico di Torino, IT 13:00-13:30 (Invited) Said Hamdioui, TU Delft, Netherlands (Title: Computation-in-Memory Based on Memristive Devices: What is all about and what is still missing?) 13:30-14:00 (Invited) Mirko Prezioso, Mentium Technologies Inc., USA (Title: Memristive circuits for neurocomputing and beyond: a progress update) 14:00-14:30 (Invited) Abu Sebastian, IBM Zurich, Swiss (Title: Computing using imprecise computational memory) W02.7 Coffee break 2 14:30 - 15:00 W02.8 Afternoon session#2 15:00 - 17:10 Chair:Fernando Corinto, Politecnico di Torino, IT 15:00-15:30 (Invited) Qiangfei Xia, University of Massachusetts, Amherst, USA (Title: Memristive Crossbar Arrays for Brain-Inspired Computing) 15:30-15:55 (Invited) Kyeong-Sik Min, Kookmin Univ., Korea (Title: Memristor-crossbar-based neural networks: from ideal to reality) 15:55-16:20 (Invited) Fernando Corinto, Politecnico di Torino, Italy (Title: Computing with Memristor Oscillatory Networks) 16:20-16:45 (Invited) Ronald Tetzlaff, TU Dresden, Germany (Title: Memristor Cellular Neural Network-inspired Paradigms for Signal Processing, will be presented by Dr. Ioannis Messaris, TU Dresden, Germany) 16:45-17:10 (Invited) Alon Ascoli, TU Dresden, Germany (Title: Store/Retrieve Gene Design and Analysis for Bistable-like Memristor CNN) W02.9 Workshops end 17:30 - 17:30 W03 DATE Workshop on Autonomous Systems Design (ASD2019) Room 1 0830 - 1700 Organisers:Rolf Ernst, Technische Universität Braunschweig, DE Selma Saidi, Hamburg University of Technology, DE Dirk Ziegenbein, Robert Bosch GmbH, DEPublicity Chair:Sebastian Steinhorst, Technische Universität München, DE ASD is the 1st international workshop on Autonomous Systems Design. The goal of ASD is to explore recent industrial and academic methods and methodologies in autonomous systems design. This includes several areas: Embedded and cyber-physical systems platforms that implement and execute the autonomous system functions including their architectures, hardware, software and communication. The design for autonomous systems including processes, modelling, optimization, verification, validation, and test. All aspects of dependable systems design for autonomous systems including, but not limited to, functional safety concepts, fail-operational systems design, functional safety for applications with machine learning, safe and secure changes and updates, autonomous systems security. NEW: Proceedings are available for download on the following link: http://drops.dagstuhl.de/portals/oasics/index.php?semnr=16104 Highlights The workshop consists of regular sessions with papers selected from an open call for papers, complemented by invited talks, and an exhibition with posters and live demos. In addition, the workshop will feature the two following distinguished keynotes: Keynote 1: Challenges of Automated and Connected Driving Speaker: Thomas Form, Head of Electronics and Vehicle Research, Volkswagen AG, Germany Summary: In recent years, various publications and presentations from a lot of companies have shown the improvements in the sector of automated driving. The vehicle- and mobility-concept SEDRIC is a current example from the Volkswagen AG. However, for a release of these technologies there are several unresolved issues regarding sensor technologies, redundancies as well as verification and validation questions. Regarding sensors, the main objectives are miniaturization and reduction of system costs. Advantages and disadvantages of existing solutions have to be evaluated. In addition to economic aspects, ensuring the redundancy of the system is absolute necessary. Is, for example, Artificial Intelligence able to provide an independent second or third function path? Regarding verification and validation concepts, current discussions are focused on which scenarios have to be tested and how, in order to enable regulatory authorities to approve the release of automated driving functions? It is conceivable, that this is an automotive industry wide task that can only be solved in cooperation with all stakeholders Biography: Born in 1959, Thomas Form studied Electrical Engineering at the University of Braunschweig, Germany, joined the Institute for Communication Engineering as research fellow in 1987 and received his Ph.D. in 1992. Up to 2002 he worked as a senior engineer in the Centre for Electromagnetic Compatibility of Volkswagen AG. In 2002 Dr. Form was appointed as the head of Telephone-/Telematics and Antenna systems development. He became a professor for "Electronic Vehicle Systems" in the Institute of Control Engineering at the Technical University Braunschweig in 2005 and participated with the CAROLO-Team in the finals of the DARPA URBAN Challenge 2007. From 2007 to 2009 he was responsible for concept development, module- and project management in the VW Electric/Electronic development. In 2009 he was appointed as head of the "Electronics and Vehicle Research" within Volkswagen Group research. Major achievements were the presentation of AUDI "Jack" vehicle driving in L3 automatic mode with Journalists from San Francisco to CES 2015 in Las Vegas and the presentation of the autonomous driving pod "SEDRIC" in 2017. Since 2016 he is the coordinator of the German national funded project PEGASUS which wants to answer the question "L3 Highway Chauffeur - how safe is safe enough and how to prove it". He got the Uni-DAS e.V. ADAS Award for significant influence on the development and introduction of driver assistance systems in 2017. Keynote 2: AUTOSAR Adaptive - Challenging the Impossible Speaker: Masaki Gondo, CTO at eSOL Co., Ltd., JP Summary: The vast researches related to autonomous driving seem steadily progressing - it no longer makes news to just have some research vehicle drive autonomously. However, bringing this technology to the market, with all the associated legal, societal, and ethical responsibilities, with justifiable cost efficiency, is hard at its best, and impossible at its worst. Furthermore, the automotive industry is facing drastic challenges in electric vehicles, connected services, which also heavily impact the whole vehicle architecture.AUTOSAR (AUTomotive Open System ARchitecture) is a worldwide development partnership of automotive interested parties. One of its latest challenges is to develop the software platform specification for the highly automated and autonomous driving, named AUTOSAR Adaptive Platform. This talk gives an overview of the challenges of such a platform, followed by the solution approach of AUTOSAR reflecting the industrial needs, and the overall architecture of AUTOSAR Adaptive. It also introduces a new multi-kernel OS technology the author develops, describing why such OS architecture is essential for coping with the challenge in the long run. Biography: Masaki is CTO at eSOL, the company that provides POSIX/AUTOSAR/TRON RTOS, various software development tools, and various engineering services. Graduated from the State University of New York, Masaki has more than 20 years of experience in the field of OS architecture and related technologies for use in wide range of embedded system applications including automotive, industrial, and electronic appliances. He has authored/co-authored multiple popular Japanese books/international articles on OS and embedded systems, and given technical talks in conferences worldwide. While serving as a CTO directing the technology strategy and architecture at eSOL, he acts as one of the architects in Task Force Architecture of Adaptive Platform. His interest in recent years spans from next-generation OS/platform architectures, parallel processing, adaptive systems including machine learning, as well as scrum/kanban based development. W03.1 Registration Desk opens 07:30 - 08:30 W03.2 Keynotes Session 08:30 - 09:50 Keynote 1: Challenges of Automated and Connected DrivingSpeaker: Thomas Form, Head of Electronics and Vehicle Research, Volkswagen AG, DEKeynote 2: AUTOSAR Adaptive - Challenging the ImpossibleSpeaker: Masaki Gondo, CTO at eSOL Co., Ltd., JP W03.3 Interactive Presentations 09:50 - 10:00 IP1: A Dependable Detection Mechanism for Intersection Management of Connected Autonomous VehiclesRachel Dedinsky, Mohammad Khayatian, Mohammadreza Mehrabian and Aviral ShrivastavaArizona State University, USAIP2: A LIDAR Only Perception System for Autonomous VehicleMohamed Yazid Lachachi, Abdelmalik Taleb-Ahmed, Smail Niar and Mohamed OuslimUniversité Polytechnique Hauts-de-France, FRIP3: Generation of a Reconfigurable Probabilistic Decision Making Engine based on Decision Networks: UAV Case StudySara Zermani and Catherine DezanLab-STICC, FR W03.4 Coffee break 1 10:00 - 10:30 W03.5 Development Approaches for Autonomous Systems 10:30 - 12:00 10h30 Bringing the Next Generation Robot Operating System on Deeply Embedded Autonomous PlatformsRalph Lange, Robert Bosch GmbH, DE11h00 IDF-Autoware: Integrated Development Framework for ROS-based Self-driving Systems Using MATLAB/SimulinkShota Tokunaga(1), Yuki Horita(2), Yasuhiro Oda(2) and Takuya Azumi(3)(1)Graduate School of Engineering Science, Osaka University (2)Hitachi Automotive Systems, Ltd, (3)Graduate School of Science and Engineering, Saitama University, JP11h20 Feasibility Study and Benchmarking of Embedded MPC for Vehicle PlatoonsInaki Martin Soroa(1), Amr Ibrahim(1), Dip Goswami(1) and Hong Li(2)(1) Eindhoven University of Technology (2) NXP Semiconductor, NL11h40 A Multiview Approach Toward Updatable Vehicle Automation SystemsMarcus Nolte, Mischa Möstl, Johannes Schlatow and Rolf ErnstTechnical University of Braunschweig, DE W03.6 Lunch break 12:00 - 13:00 W03.7 Dependable Autonomous Systems 13:00 - 14:30 13h00 Autonomous Data Center - Feedback Control for Predictable Cloud ComputingMartina Maggio, University of Lund, SE13h30 Fault-Tolerance by Graceful Degradation for Car PlatoonsMohammed Baha E. Zarrouki(1), Verena Klös(1), Markus Grabowski(2) and Sabine Glesner(1)(1)Technische Universität Berlin, DE, (2)Assystem Germany GmbH13h50 Safety and Security Analysis of AEB for L4 Autonomous Vehicle using STPAShefali Sharma(1), Adan Flores(1), Chris Hobbs(2), Jeff Stafford(3) and Sebastian Fischmeister(1)(1)University of Waterloo, CA (2)QNX Software Systems Limited,CA (3) Renesas Electronics America Inc.14h10 Towards a Formal Model of Recursive Self-ReflectionAxel JantschTU Wien, AT W03.8 Coffee break 2 14:30 - 15:00 W03.9 Research Clusters on Autonomous Systems 15:00 - 16:30 15h00 An approach to automotive service-oriented software architectures in a multi-partner research projectStefan Kowalewski, RWTH Aachen, DE15h30 Controlling Concurrent Change- Design Automation for Critical Systems IntegrationRolf Ernst, TU Braunschweig, DE 16h00 Panel Discussion W03.10 Closing & Exhibition 16:30 - 17:00 W03.11 Workshops end 17:30 - 17:30 W04 6th Workshop on Design Automation for Understanding Hardware Designs (DUHDE6) Room 9 0830 - 1700 Organisers:Christian Krieg, Vienna University of Technology, AT Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DEProgramme Committee Members:Maciej Ciesielski, University of Massachusetts, US Azadeh Davoodi, University of Wisconsin - Madison, US Görschwin Fey, Technische Universität Hamburg, DE Tara Ghasempouri, Tallinn University of Technology, EE Ian Harris, University of Californa Irvine, US Jan Malburg, German Aerospace Center, DE Heinz Riener, EPFL, CH Jannis Germany Stoppe, DFKI GmbH, DE Pramod Subramanyan, Indian Institute of Technology Kanpur, IN Georg Weissenbacher, Vienna University of Technology, AT Clifford Wolf, Symbiotic EDA, AT Cunxi Yu, EPFL, CH Understanding a hardware design can be a tough process. When entering a large team as a new member, when extending a legacy design, or when documenting a new design, a lack in understanding the details of a design is a major obstacle for productivity. In software engineering, topics like software maintenance, software understanding or reverse engineering are well established in the research community and partially tackled by tools. In the hardware area, the re-use of IP-blocks, the growing size of designs and design teams leads to similar problems. Understanding of hardware requires deep insight into concurrently operating units, optimizations to reduce the required area, and specially tailored functional units for a particular use. In hardware security, it is vital to verify properties for security-critical paths of a design, which includes to fully understand a design pre- and post-synthesis. Topics The workshop focus includes but is not limited to the following topics in design understanding: Design descriptions from the formal specification level (FSL) to electronic system level(ESL) down to register transfer level (RTL) Extraction of high-level properties Knowledge extraction from design structures at any level of abstraction Feature localization: Localization of code implementing specialized functionality Data/Control path extraction Reverse engineering Innovative GUIs for design and verification Analysis of interaction between hardware and software Metrics for (open-source) intellectual property (IP) cores Formal methods for design understanding Machine learning for design understanding Future applications of design understanding Submissions may be extended abstracts of 2 pages or full papers of 6 pages in IEEE or ACM conference style. Informal proceedings will be distributed electronically. Please submit your contributions at: https://www.softconf.com/date19/DUHDe W04.1 Registration Desk opens 07:30 - 08:30 W04.2 Workshop opening 08:30 - 08:45 Moderators:Christian Krieg, TU Wien, AT Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE W04.3 Invited talk: Addressing Integrated Circuit Integrity Using Statistical Analysis and Machine Learning Techniques 08:45 - 09:30 Speaker:Burcin Cakir, Princeton University, US Bio: Burcin Cakir received her B.S. degree from Electrical Engineering Department of Bilkent University, and her Ph.D. degree from Princeton University. Her research motivation is formulating models that can represent real systems accurately and express mathematical bases/frameworks for further analysis. She had experience in developing algorithms and analyses to help design secure hardware systems. She is a recipient of Francis Robbins Upton Fellowship award from Princeton University. Her work on Hardware Trojan detection received Best Paper Award at DATE Conference (2015). She also has served as a referee on various journals and conferences and gave workshop and seminar talks. Besides her work at Princeton, she also had experience in industry research with two internships at Microsoft Research (MSR) in Redmond and Cambridge Labs. W04.4 Paper presentation block 1 09:30 - 10:00 Moderators:Christian Krieg, TU Wien, AT Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE 09:30 W04.4.1 Towards Gate-Level Design of QCA Circuits W04.5 Coffee break 1 10:00 - 10:30 W04.6 Paper presentation block 2 10:30 - 12:00 Moderators:Christian Krieg, TU Wien, AT Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE 10:30 W04.6.1 Deductive Binary Code Verification Based on Source-Code-Level ACSL Specifications 11:00 W04.6.2 Extracting Assertions for Conflicts in HDL Descriptions 11:30 W04.6.3 Complete Specification Mining W04.7 Lunch break 12:00 - 13:00 W04.8 Invited talk: Reverse Engineering for Security: Views From the Top and the Bottom. 13:00 - 14:00 Moderators:Christian Krieg, TU Wien, AT Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE Speaker:Pramod Subramanyan, Indian Institute of Technology Kaipur, IN Abstract: Recent years have seen much hand-wringing about security concerns posed by malicious hardware designs. Seemingly at the other end of the spectrum are inadvertent hardware design flaws that lead to security breaches. The former concern has led to development of algorithmic reverse engineering techniques, Hardware Trojan detection algorithms and side-channel analysis algorithms -- all of which aim to algorithmically discover malicious behavior from the bottom up. The latter concern has led to the progress in top-down security verification techniques based on model checking and syntax-guided synthesis. In this talk, I will try to review some recent progress in both top-down and bottom-up analysis. I will argue that both top-down and bottom-up techniques can synergistically benefit each other. Bio: Pramod Subramanyan is an Assistant Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology, Kanpur. He obtained his Ph.D. from Princeton University and subsequent to his Ph.D., he was a postdoctoral scholar at the University of California, Berkeley. His research interests lie at the intersection of systems security and formal methods. His current research is focused on system-building techniques that can provide verifiable guarantees of security. Pramod's research has won several awards including the Best Paper Award at the ACM Computer and Communication Security conference, the ACM SIGDA Outstanding Ph.D. Dissertation in Electronic Design Automation Award, the Best Student Paper Award at IEEE Symposium on Hardware-Oriented Security and Trust. W04.9 Paper presentation block 3 14:00 - 14:30 Moderators:Christian Krieg, TU Wien, AT Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE 14:00 W04.9.1 Generating a UML Sequence Diagram from a Natural Language Scenario Description W04.10 Coffee break 2 14:30 - 15:00 W04.11 Invited talk: Project Trellis: open bitstream documentation for the Lattice ECP5 FPGAs 15:00 - 16:00 Moderators:Christian Krieg, TU Wien, AT Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE Speaker:David Shah, Symbiotic EDA, GB Abstract:The Lattice ECP5 is a family of mid-range (up to 85k logic cells) FPGAs. Project Trellis has created open source bitstream, architecture and timing documentation for them; in order to open up a better understanding of their internals. This has led to the development of an end-to-end open source Verilog to bitstream flow for these parts using Yosys for synthesis and nextpnr for place-and-route, and opens the door to low-level experimentation not possible within the constraints of the vendor FPGA tools. Open source compilers such as GCC and LLVM are now widely used and accepted in the software development community; and developing open bitstream documentation is a first step to bringing the FPGA ecosystem to parity with this. This talk will describe the processes used to build this open documentation, detail some of the interesting lessons learnt along the way, and describe some of the possibilities that bitstream documentation bring for development and verification - with almost everything discussed equally applicable to FPGAs from other vendors. Bio: David Shah is a engineer at Symbiotic EDA and a Electronic and Information Engineering student at Imperial College London. He entered the world of open source FPGAs by extending Project Icestorm, the iCE40 bitstream documentation project, to include the newer iCE40 UltraPlus FPGAs. As well developing Project Trellis, he has been involved in the development of a new open source FPGA place-and-route tool, nextpnr. W04.12 Paper presentation block 4 16:00 - 17:30 Moderators:Christian Krieg, TU Wien, AT Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE 16:00 W04.12.1 Engineering of an Effective Automatic Assertion-based Verification Platform 16:30 W04.12.2 Design Mapper: Dataflow Analysis for Better Floorplans 17:00 W04.12.3 Using AI for the Performance Verification of High-End Processors 17:15 W04.12.4 The Verification Cockpit - Harnessing Data Analytics for the HW Verification Process W04.13 Workshops end 17:30 - 17:30 W05 AxC: 4th Workshop on Approximate Computing Room 5 0830 - 1700 Programme Chair:Alberto Bosio, INL, FRGeneral Co-Chairs:Mario Barbareschi, University of Naples Federico II, IT Claus Braun, University of Stuttgart, DE Aim of the Workshop: the investigation of connections between AxC paradigm and the verification, the test and the reliability of digital circuits from two points of view: how the approximate computing paradigm impacts the design and manufacturing flow of integrated circuits; how the verification, testing and reliability disciplines can be exploited in the approximate computing paradigms. Keynotes: The organizing committee of AxC19 is proud to announce two keynote speeches, which will be given by Prof. Kaushik Roy, title: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, Systems. and Approximations Dr. Cristiano Malossi, title: Transprecision Computing for Energy-Efficiency For further details about Workshop program, keynotes and other information, please visit the AxC19 website at: http://embedded.unina.it/AxC19 Submission website is already available: https://easychair.org/conferences/?conf=axc19 For this edition, authors of accepted papers will be invited to submit their work for a special issue on "Advancing on Approximate Computing: Methodologies, Architectures and Algorithms", planned to be published onto Future Generation Computer Systems (Q1, IF 4.639, H index 85). You can find details about AxC19 from the CfP available at http://embedded.unina.it/AxC19/call-for-paper/ W05.1 Registration Desk opens 07:30 - 08:30 W05.2 Opening Session 08:30 - 09:00 W05.3 Keynote 1 09:00 - 10:00 Keynote "Transprecision Computing for Energy-Efficiency" by dr. Cristiano Malossi from IBM Research of Zurich W05.4 Coffee Break 10:00 - 10:30 W05.5 Technical Session 1 10:30 - 12:00 Resilience-based Mapping of Deep Neural Network Operations to Approximate Computing UnitsChristoph Schorn (Robert Bosch GmbH), Matthias Roth (Esslingen University of Applied Sciences), Andre Guntoro (Robert Bosch GmbH) and Gerd Ascheid (RWTH Aachen University)Noise Budgeting in Multiple-Kernel Word-Length OptimizationVan-Phu Ha (University of Rennes 1), Tomofumi Yuki (University of Rennes 1) and Olivier Sentieys (University of Rennes 1) Reliability Evaluation of Mixed-Precision ArchitecturesPaolo Rech (UFRGS), Fernando Fernandes dos Santos (UFRGS), and Daniel Oliveira (UFRGS) Approximate Computing of Transcendental Functions Applied to Artificial Neural NetworksXin Fan (IDS, RWTH Aachen Univ), Arthur Ruder (IDS, RWTH Aachen Univ), Cecilia Höffler (IDS, RWTH Aachen Univ), and Tobias Gemmeke (IDS, RWTH Aachen Univ) W05.6 Lunch break 12:00 - 13:00 W05.7 Invited Talk 13:00 - 13:30 Approximate Computing in HPC: building from ground upAlessandro Cilardo (Università degli Studi di Napoli Federico II) W05.8 Keynote 2 13:30 - 14:30 Keynote : Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, Systems. and Approximations" by prof. Kaushik Roy from School of Electrical and Computer Engineering of Purdue University. W05.9 Coffee Break 14:30 - 15:00 W05.10 Technical Session 2 15:00 - 17:00 Targeting Approximation through Data Lifetime: A Quest for Optimization MetricsAlessandro Savino (Politecnico di Torino), Michele Portolan (Univ. Grenoble Alpes, TIMA), Stefano Di Carlo (Politecnico di Torino) and Regis Leveugle (Univ. Grenoble Alpes, TIMA)Jump Search: A Fast Technique for the Synthesis of Approximate CircuitsLinus Witschen (Paderborn University), Hassan Ghasemzadeh Mohammadi (Paderborn University), Matthias Artmann (Paderborn University) and Marco Platzner (Paderborn University)An Approximate Communication Technique for Energy Efficient Networks on ChipGiuseppe Ascia (University of Catania), Vincenzo Catania (University of Catania), John Jose (Indian Institute of Technology Guwahati), Salvatore Monteleone (University of Catania), Maurizio Palesi (University of Catania) and Davide Patti (University of Catania)Adjustable Precision Computing Using Redundant ArithmeticAli Skaf (TIMA), Mona Ezzadeen (TIMA), Mounir Benabdenbi (TIMA) and Laurent Fesquet (TIMA)Towards One Million Component Library of Approximate CircuitsLukas Sekanina (Brno University of Technology), Zdenek Vasicek (Brno University of Technology) and Vojtech Mrazek (Brno University of Technology)Exploiting Approximate Computing to Increase System LifetimeE. Sanchez (Politecnico di Torino), P. Bernardi (Politecnico di Torino) and W. J. Perez-Holguin (Universidad Pedagógica y Tecnológica de Colombia) Approximate Computing for Sizing Hidden Layer in CNNStefano Marrone (University of Naples Federico II) and Carlo Sansone (University of Naples Federico II) W06 2nd International Workshop on Embedded Software for the Industrial IoT (ESIIT 2019) Room 6 0830 - 1700 Organisers:Oliver Bringmann, Eberhard Karls Universität Tübingen, DE Wolfgang Ecker, Infineon Technologies, DE Wolfgang Müller, Universität Paderborn, DE Daniel Müller-Gritschneder, Technische Universität München, DE Motivation and Objectives The Internet-of-things (IoT) is emerging as the backbone for industrial automation. The tremendous impact of IoT to industrial applications is a key reason for IoT research and developments to grow dramatically in importance and economic impact for the next decade. At the edge of the IoT, ultra-thin devices with extremely small software memory footprints need to be cheap and capable to run with extremely small amounts of energy support over a very long lifetime. At the same time, IoT software must provide smart functions including real-time computing capabilities, connectivity, security, safety, and remote update mechanisms. These constraints put a high pressure on IoT software development based on the specific properties of IoT devices. The ESIIT 2019 joint academic/industry workshop will focus on software development and maintenance of IoT devices addressing the very limited resources and power dissipation of IoT edge nodes in the context of a very long life cycle in an operational IoT network. This covers issues like software synthesis, configurability, safety, security, upgrades, fault recovery, maintenance as well as constraints and opportunities from newly emerging IoT hardware platforms. The workshop intends to provide an open platform for exchange and communication on new directions and requirements to academia and industry. We plan to especially give industrial speakers and leading research experts a platform to present the requirements and most recent results in today's and future industrial IoT-constrained software development and maintenance. The main objectives are: to invite industrial experts to present current and future needs and requirements to present and discuss novel technologies and ideas from different research areas and domains to explore and align trends and future needs for IoT platform development and maintenance from the perspective of academia and industry. Highlights ESIIT 2019 will feature a range academic talks with poster presentation as well as 3 invited industrial presentations. Invited talk from Michael Velten (Infineon Technologies AG)) Title: Proposals for IP-XACT Extensions from Embedded Controller Use Cases Invited talk from Aljoscha Kirchner (Robert Bosch GmbH) Title: Automation of Embedded Software Development for Smart Sensor ASICs Invited talk from Thomas Kuhn (Fraunhofer IESE)Title: BaSys 4.0: An Open Source Middle for the Industrial Internet of Things Registration ESIIT Workshop is a DATE 2019 Friday Workshop (Friday Workshop W06). Workshop registration is still possible onsite. Workshop Presentations can be downloaded here. Tentative Workshop Proceedings can be downloaded here. W06.1 Registration Desk opens 07:30 - 08:30 W06.2 Opening 08:45 - 17:51 W06.3 Session I: Invited Industrial Session 09:00 - 17:51 09:00 W06.3.1 Proposals for IP-XACT Extensions from Embedded Controller Use Cases Authors: Michael Velten and Wolfgang Ecker, Infineon Technologies, DE 09:30 W06.3.2 Automation of Embedded Software Development for Smart Sensor ASICs Authors: Aljoscha Kirchner¹, Jan-Hendrik Oetjens¹ and Oliver Bringmann^{2 1}Robert Bosch GmbH, DE; ²Universität Tübingen, DE W06.4 Break: Refreshments & Poster Discussions 10:00 - 17:51 W06.5 Session II: Applications for the IOT 10:30 - 17:51 10:30 W06.5.1 An Experimental Platform for Cooperative Work with Context-Oriented Programming and Hardware Reconfiguration for Industry IoT Authors: Harumi Watanabe¹, Mikiko Sato¹, Ikuta Tanigawa², Mariya Kawamura¹, Nobuhiko Ogura³ and Takeshi Ohkawa^{4 1}Tokai University, JP; ²Kyushu University, JP; ³Tokyo City University, JP; ⁴Utsunomiya University, JP 10:45 W06.5.2 Inertial Sensor Based Robot Gesture Detection for Safe Human-Robot Interaction Authors: Johann-Peter Wolff¹, Christian Haubelt¹, Rolf Schmedes² and Kim Grüttner^{2 1}University of Rostock, DE; ²OFFIS - Institut für Informatik, DE 11:00 W06.5.3 An Open-Source, IoT-Tailored Face Detection Software Authors: Panagiotis Kalodimas¹, Antonis Nikitakis¹ and Ioannis Papaefstathiou^{2 1}Technical University of Crete, GR; ²Aristotle University of Thessaloniki, GR 11:15 W06.5.4 Component-based FPGA Development of Intelligent Image Processing for Industrial IoT Devices Authors: Kenta Arai, Takeshi Ohkawa, Kanemitsu Ootsu and Takashi Yokota, Utsunomiya University, JP W06.6 Session III: Invited Industrial Presentations 11:30 - 17:51 11:30 W06.6.1 BaSys 4.0: An Open-Source Middleware for the Industrial Internet of Things Authors: Frank Schnicke, Markus Damm and Thomas Kuhn, Fraunhofer IESE, DE W06.7 Break: Lunch & Poster Discussions 12:00 - 17:51 W06.8 Session IV: Safety, Security, Performance and Power Optimizations & Analysis for the IoT 13:00 - 17:51 13:00 W06.8.1 Firmware-Driven Optimization of the Hardware/Software Interface for IoT Nodes Authors: Rafael Stahl, Daniel Müller-Gritschneder and Ulf Schlichtmann, TUM, DE 13:15 W06.8.2 A Heuristic for Multi Objective Software Application Mappings on Heterogeneous MPSoCs Authors: Gereon Führ¹, Ahmed Hallawa¹, Rainer Leupers¹, Gerd Ascheid¹ and Awaid-Ud-Din Shaheen^{2 1}RWTH Aachen, DE; ²Silexica GmbH, DE 13:30 W06.8.3 Source-level Power Simulation of IoT Firmware for Energy Evaluation Authors: Michael Kuhn and Oliver Bringmann, Universität Tübingen, DE 13:45 W06.8.4 Towards Distributed Runtime Monitoring with C++ Contracts Authors: Rolf Schmedes and Philipp Ittershagen, OFFIS - Institut für Informatik, DE 14:00 W06.8.5 Security Chain Tool for IoT Secure Applications Authors: Christoph Schmittner and Abdelkader Magdy Shaaban, Austrian Institute of Technology, AT 14:15 W06.8.6 QEMU for Dynamic Memory Analysis of Security Sensitive Software Authors: Peer Adelt¹, Bastian Koppelmann¹, Wolfgang Müller¹, Christoph Scheytt¹ and Benedikt Driessen^{2 1}Heinz Nixdorf Institute, DE; ²Kasper & Oswald GmbH, DE W06.9 Break: Refreshments & Poster Discussions 14:30 - 17:51 W06.10 Session V: Model Based Frameworks for IoT Software Development 15:00 - 17:51 15:00 W06.10.1 A Syntax Oriented Code Generation Approach for SoC Design Automation Authors: Michael Werner, Andreas Neumeier and Wolfgang Ecker, Infineon Technologies, DE 15:15 W06.10.2 Ecosystem for Agile Design of Future-Proof RISC-V Based IoT-Devices Authors: Leon Hielscher¹, Frederik Haxel¹, Arthur Kühlwein¹, Sebastian Reiter¹, Alexander Viehl¹, Oliver Bringmann¹ and Wolfgang Rosenstiel^{2 1}FZI Forschungszentrum Informatik, DE; ²University of Tübingen, DE 15:30 W06.10.3 Towards Stateflow Model-Aware Debugging Using Model-to-Source Tags with LLDB Authors: Bewoayia Kebianyor, Philipp Ittershagen and Kim Grüttner, OFFIS - Institut für Informatik, DE 15:45 W06.10.4 Tackling the Challenges of Internet-of-Things-Development Using Models Authors: Rupert Schlick and Willibald Krenn, Austrian Institute of Technology, AT W06.11 Plenary Discussions & Closing 16:00 - 17:51 W06.12 End of Workshop 16:15 - 17:51 W07 Workshop on Machine Learning for CAD Room 7 0830 - 1700 Organisers:Hussam Amrouch, Karlsruhe Institute of Technology (KIT), DE Jörg Henkel, Karlsruher Institut für Technologie (KIT), DE Marilyn Wolf, Georgia Tech, US Workshop Focus This workshop focuses on machine learning methods for all aspects of CAD and electronic system design. Advances in machine learning (ML) over the past half-dozen years have revolutionized the effectiveness of ML for a variety of applications. However, design processes present challenges that require parallel advances in ML and CAD as compared to traditional ML applications such as image classification. As such, the purpose of the workshop is to discuss, define and provide a roadmap for the special needs for ML for CAD where CAD is broadly defined as design time techniques as well as run-time techniques. The results of the workshop will be published in a special issue at ACM Transactions on Design Automation of Electronic Systems (TODAES). Invited Speakers and Panelists Krishnendu Chakrabarty; Duke University Rolf Drechsler; University of Bremen Paul Franzon; North Carolina State University Siddharth Garg; New York University Georges Gielen; KU Leuven Rajesh Gupta; UC San Diego Ulf Schlichtmann; TU Munich Dimitrios Soudris; University of Athens Norbert Wehn; TU Kaiserslautern Kai-Chiang Wu; National Chiao Tung University, Taiwan Lilia Zaourar; CEA-LIST Agenda Time Label Session 07:30 W07.1 Registration Desk Opens 08:30 W07.2 Design Space Exploration using Machine Learning08:30-09:00: Ulf Schlichtmann, TU Munich, Title: Machine Learning Approaches for Efficient Design Space Exploration of Application-specific NoCs (abstract).09:00-09:30: Lilia Zaourar, CEA-LIST, Title: Machine Learning for Design Space Exploration of CPS (abstract).09:30-10:00: Rajesh Gupta, UC San Diego,Title: TBA 10:00 W07.3 Morning Coffee Break 10:30 W07.4 Design for Reliability using Machine Learning10:30-11:00: Rolf Drechsler, Univ. of Bremen, Title: Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques (abstract).11:00-11:30: Siddharth Garg, New York University, Title: ML4TPU: Machine Learning for Energy Efficient and Reliable ML Hardware (abstract).11:30-12:00: Kai-Chiang, National Chiao Tung University, Title: Learning-based methodologies for assessing chip health in terms of aging and reliability (abstract). 12:00 W07.5 Lunch Break 13:00 W07.6 Design-Time and Run-Time Machine Learning Techniques for SoCs13:00-13:30: Paul Franzon, North Carolina State University, Title: Designing Your Circuits with Robots (abstract).13:30-14:00: Krishnendu Chakrabarty, Duke University, Title: Predictive Analytics for Run-Time Anomaly Detection and Failure Prediction in Complex Core Routers (abstract).14:30-15:00: Dimitrios Soudris, Univ. of Athens, Title: A Methodology for Application Implementation onto 3-D FPGAs (abstract). 14:30 W07.7 Afternoon Coffee Break 15:00 W07.8 Machine Learning for Circuit Modeling15:00-15:30: Georges Gielen, KU Leuven, Title: AI learning techniques in design and test of analog integrated circuits (abstract).15:30-16:00: Norbert Wehn, TU Kaiserslautern, Title: Modeling of DRAM Behavior with Recurrent Neural Networks (abstract).16:00-16:15: (Poster) Lukas Sekanina, Title: Machine Learning in Logic Synthesis.16:15-16:30: (Poster) Huiyuan Song, Title: Fast FPGA Routing Algorithm using Graph Neural Network. 16:30 W07.9 Panel: Where Do We Go From Here?Panelists: Paul Franzon, Rajesh Gupta, Nicholas Ventroux, Norbert WehnModerator: Marilyn Wolf 17:30 W07.10 Workshop Wrap-up 18:30 Joint dinner with discussion of future plans (buy-your-own-meal)Location: Ristorante Buca Mario (google maps) W07.1 Registration Desk opens 07:30 - 08:30 W07.2 Workshops start 08:30 - 08:30 W07.3 Coffee break 1 10:00 - 10:30 W07.4 Lunch break 12:00 - 13:00 W07.5 Coffee break 2 14:30 - 15:00 W07.6 Workshops end 17:30 - 17:30 W08 Grand Challenges and Research Tools for Quantum Computing Room 10 0830 - 1700 Organiser:Ali Javadi, IBM, US Link to Videos on Youtube Links to installation (instructions + workshop script) are below. Preinstall software before the workshop. The Docker + Docker image file size is ~7GB, so please start the installation process now. LINUX MAC WINDOWS Participation Abstract: In this workshop, we are interested in exploring the role that computer scientists can play in making quantum computing a reality. We will introduce major themes in quantum computing research, including applications, error correction, compilation and optimization. We will then discuss some grand open challenges and ask what role computer science plays in optimizing the full software/hardware stack of quantum computers. No prior quantum computing knowledge is necessary to participate. Workshop Details: Quantum computing is at an inflection point, where 72-qubit (quantum bit) machines have been built, 100-qubit machines are just around the corner, and even 1000-qubit machines are perhaps only a few years away. These machines have the potential to fundamentally change our concept of what is computable and demonstrate practical applications in areas such as quantum chemistry, optimization, and quantum simulation. Yet a significant resource gap remains between practical quantum algorithms and near-term machines. Software and architectures are what are needed to increase the efficiency of algorithms and machines and close this gap. There is a urgent shortage of the necessary computer scientists to work on closing this gap (there are over 60 public and private companies trying to hire in this area). This workshop will outline the grand research challenges in closing this gap, including programming language design, software and hardware verification, defining and perforating abstraction boundaries, cross-layer optimization, managing parallelism and communication, mapping and scheduling computations, reducing control complexity, machine-specific optimizations, and many more. Some of these challenges can be approached with minimal quantum computing background and some will require greater depth. We will introduce the basic concepts and resources to enable researchers to begin to delve into these challenges. We will also introduce quantum algorithms of near-term significance. Finally, we will provide an overview and hands-on experience with an end-to-end set of software tools from a high-level programming language to running experiments on cloud-access IBM quantum machines. These tools will be a combination of the Scaffold Quantum Programming Language/Compiler and the IBM Qiskit tools and interfaces. This workshop will be highly interactive. Participants will install our tools and work with code examples running on real quantum hardware at IBM, all organized within Jupyter notebooks, throughout the afternoon. ORGANIZERS Fred Chong (UChicago) -- co-author of the Scaffold compiler and simulation tools for quantum computing and a synthesis lecture on quantum computing for computer architects. Ken Brown (Duke) -- Leading researcher in the control of quantum systems for both understanding the natural world and developing new technologies. His current research areas are the development of robust quantum computers and the study of molecular properties at cold and ultracold temperatures. Andrew Cross (IBM Research) - Researcher in quantum computing theory, author of the Quantum Assembly (QASM) language and the Qiskit compiler for cloud-access to IBM quantum machines, and expert in quantum error correction. Diana Franklin (UChicago) -- Education lead of EPiQC. Co-author of the Scaffold compiler and simulation tools for quantum computing. Ali Javadi-Abhari (IBM Research) -- co-author of the Scaffold compiler and simulation tools for quantum computing and researcher for IBM's Qiskit quantum computing tools and cloud access to IBM's prototype machines. TEACHING ASSISTANTS Pranav Gokhale (UChicago) -- second year PhD student in quantum computer architecture Xin-Chuan (Ryan) Wu (UChicago) -- third year PhD student in quantum computer architecture AGENDA 7:30 W08.1 Registration Desk Opens 8:30 W08.2 Intro to Grand Challenges in Quantum ComputingFred Chong (UChicago) 10:00 W08.3 Morning Coffee Break 10:30 W08.4 Basics of Quantum ComputingDiana Franklin (UChicago) 12:00 W08.5 Lunch Break 13:00 W08.6 Basic Algorithms, Tools for Compilation (Hands-on Demo)Ali Javadi-Abhari (IBM) 14:30 W08.7 Afternoon Coffee Break 15:00 W08.8 Algorithms for Quantum ChemistryKen Brown (Duke) 17:30 W08.9 Workshop Wrap-up W09 Quo vadis, Logic Synthesis? Room 8 0830 - 1700 Organisers:Tiziano Villa, Università di Verona, IT Luca Carloni, Columbia University, USSpeakers:Luca Amaru, Synopsys, US Anna Bernasconi, Università di Pisa, IT Valentina Ciriani, University of Milano, IT Jordi Cortadella, Universitat Politecnica de Catalunya, ES Masahiro Fujita, University of Tokyo, JP Jie-Hong Jiang, National Taiwan University, TW Weikang Qian, Shanghai Jiao Tong University, CN Sherief Reda, Brown University, US Marc Riedel, University of Minnesota, US Tsutomu Sasao, Meiji University, JP Mathias Soeken, Integrated System Laboratory – EPFL, CH Andres Takach, Calypto Design Systems, US Gabriella Trucco, Universita' degli Studi di Milano, IT Luca Carloni, Columbia University, US Tiziano Villa, Università di Verona, IT In 1984, the book on Espresso by R. Brayton, G. Hachtel, C. McMullen and A. Sangiovanni-Vincentelli provided the first layer of the foundations of modern logic synthesis. The work done around that time by leading academic and industrial research laboratories triggered the first wave of modern logic design tools like Espresso, MIS, SIS and VIS, which then became the backbone of the industrial design chains offered by the newborn Electronic Design Automation Industry. After many research breakthroughs and industrial successes, it is time for an assessment of the perspectives of logic synthesis, both as a core technology in digital system design and an enabling technology in other domains (biological synthesis, machine learning for data analysis, etc.). To achieve this goal, this workshop brings together an inclusive list of speakers from both academia and industry, to report on the state-of-art and strategic directions of the field. Program 7:30-8:30 Registration desk opens 8:30-8:40 Introduction by Luca Carloni and Tiziano Villa 8:40-9:00 Thirty-five years after the Espresso book: a retrospective on logic synthesis, Tiziano Villa 9:00-10:00 Algorithmic foundations of logic synthesis - Part 1 - Extracting functions from Boolean relations, Jordi Cortadella - Expressing flexibility in logic synthesis by Boolean relations, Anna Bernasconi 10:00-10:15 Coffee break 10:15-11:15 Algorithmic foundations of logic synthesis - Part 2 - Craig interpolation in logic synthesis applications, Jie-Hong Jiang - SAT in logic synthesis, Mathias Soeken 11:15-12:15 Synthesis for emerging technologies - XOR gates in emerging technologies, Valentina Ciriani - Majority Logic Synthesis, Luca Amaru' 12:15-13:15 Lunch 13:15-14:15 Approximate synthesis - Approximate logic synthesis for area and delay optimization, Weikang Qian - Systematic approaches to approximate logic synthesis, Sherief Reda 14:15-15:15 High-level synthesis - High-level synthesis: status and future trends, Andres Takach - How high-level synthesis enables design for reusability of hardware accelerators, Luca Carloni 15:15-15:30 Coffee break 15:30-16:30 Logic synthesis and machine learning - Automated synthesis of distributed/parallel computing through templates and inductive reasoning, Masahiro Fujita - On the minimization of variables to represent sparse multi-valued input decision diagrams, Tsutomu Sasao 16:30-17:30 Logic synthesis and biological models - Synthetic biology: application of logic synthesis to biological models, Gabriella Trucco - Stochastic logic applied to DNA computing, Marc Riedel W10 Workshop on Open-Source Design Automation for FPGAs - OSDA Room 4 0830 - 1700 Organisers:Eddie Hung, University of British Columbia, CA Christian Krieg, Vienna University of Technology, AT Clifford Wolf, Symbiotic EDA, ATProgramme Committee Members:Andrea Borga, oliscience, NL Xin Fang, Northeastern University, US Shane Fleming, Imperial College London, GB Hipolito Guzman-Miranda, University of Sevilla, ES Steve Hoover, Redwood EDA, US Dirk Koch, University of Manchester, GB Mieszko Lis, University of British Columbia, CA Brent Nelson, Brigham Young University, US Steffen Reith, RheinMain University of Applied Sciences, DE Davide Rossi, University of Bologna, IT FPGAs are increasingly finding themselves in huge data-centers as well as in the hands of hobbyists. However the wide availability of these high and low cost devices contrasts with the narrow ways in which one can access them -- through proprietary closed-source tools and IP -- which can hamper the realisation and deployment of novel FPGA-based applications and EDA innovations. Open-source is a proven and prevalent success when it comes to CPU and GPU silicon, and there are already efforts to drive reconfigurable silicon towards the same trend. This one-day workshop aims to bring together industrial, academic, and hobbyist actors to explore, disseminate, and network over ongoing efforts for open design automation, with a view to enabling unfettered research and development, improving EDA quality, and lowering the barriers and risks to entry for industry. These aims are particularly poignant due to the recent efforts across the European Union (and beyond) that mandate "open access" for publicly funded research to both published manuscripts as well as any code necessary for reproducing its conclusions. Extended motivation Topics of interest at OSDA include, but are not limited to: Open-source FPGA tools -- the latest developments, breakthroughs, challenges and surveys on the toolflows required to target real silicon parts: synthesis, simulation, place and route, etc. Open-source IP for FPGAs -- contributions that enrich the IP ecosystem and reduce the need to "re-invent the wheel", e.g. PCIe and DDR controllers, debug infrastructure, etc. Design methodologies provided as open-source -- such as alternative hardware description languages (e.g. derived from Python, Scala), domain specific languages (DSL), high level synthesis (HLS), asynchronous methods, and others. Directions on where the open-source FPGA movement should go, current weaknesses in the toolchain, and/or perspectives from industry on how open-source can affect aspects of safety, security, verification, IP protection, time-to-market, datacenter/cloud infrastructure, etc. Discussions and case studies on how to license, acquire funding, and commercialise technologies surrounding open-source hardware, which may be different to open software. Important dates Submission deadline 17 December 2018 Notification of acceptance 14 January 2019 Camera-ready final version   11 February 2019 Workshop 29 March 2019 Submission details and requirements Prospective authors are invited to submit original contributions (up to six pages), extended abstracts describing work-in-progress or position papers (not exceeding two pages), and demo proposals that would be of general interest. Papers must be submitted as an A4-sized PDF, in the IEEE conference format. In line with OSDA's mission, we encourage and will favour submissions that make all artifacts used for experimentation (benchmarks, code, etc.) available for private peer-review. Accepted submissions are required to publish these artifacts under an OSI-approved (preferably permissive) license. The proceedings of this workshop containing all accepted papers will be published on the open-access arXiv repository. Every accepted paper must have at least one author registered to the workshop by 31 January. Selected papers may also be considered for a special-issue journal; student authors may be eligible for travel assistance from our sponsors. W10.1 Registration Desk opens 07:30 - 08:30 W10.2 Workshops start 08:30 - 08:30 W10.3 Welcome 08:45 - 09:00 W10.4 Keynote -- "PULP: An Open-Source RISC-V Based Multi-Core Platform for In-Sensor Analytics" Davide Rossi (University of Bologna) 09:00 - 10:00 Speaker:Davide Rossi, Università di Bologna, IT Talk synopsis:The "internet of everything" envisions trillions of connected objects loaded with high- bandwidth sensors requiring massive amounts of local signal processing, fusion, pattern extraction and classification. While silicon access cost is naturally decreasing due to the twilight of the Moore's law, the access to hardware IPs still represents a huge barrier for innovative start-ups and companies approaching the market of IoT. In this context, the recent growth of high-quality open source hardware IPs represents a promising way to surpass this barrier, paving the way for a number of exciting applications of open-source electronics. In this talk, I will describe the evolution of the open-source Parallel-Ultra-Low-Power (PULP) platform as well as opportunities and challenges for next generation open source computing systems. Speaker biography:Davide Rossi, received the PhD from the University of Bologna, Italy, in 2012. He has been a post doc researcher in the Department of Electrical, Electronic and Information Engineering "Guglielmo Marconi" at the University of Bologna since 2015, where he currently holds an assistant professor position. His research interests focus on energy efficient digital architectures in the domain of heterogeneous and reconfigurable multi and many-core systems on a chip. This includes architectures, design implementation strategies, and runtime support to address performance, energy efficiency, and reliability issues of both high end embedded platforms and ultra-low-power computing platforms targeting the IoT domain. In these fields, he has published more than 80 paper in international peer- reviewed conferences and journals. W10.5 Coffee break 1 + Demos 10:00 - 10:30 nextpnr -- a portable FPGA place and route tool David Shah and Eddie Hung (SymbioticEDA, AT) OpenFPGA: a Complete Open Source Framework for FPGA Prototyping Baudouin Chauviere, Aurélien Alacchi, Edouard Giacomin, Xifan Tang and Pierre-Emmanuel Gaillardon (University of Utah, USA) Please check website for the most up-to-date list of demos: https://osda.gitlab.io/ W10.6 Session 1: Full Papers 10:30 - 11:30 LiteX: an open-source SoC builder and library based on Migen Python DSL Florent Kermarrec, Sébastien Bourdeauducq, Jean-Christophe Le Lann and Hannah Badier (Enjoy-Digital, FR) On Hardware Verification In An Open Source Context Ben Marshall (University of Bristol, UK) PyGears: A Functional Approach to Hardware Design Bogdan Vukobratović, Andrea Erdeljan and Damjan Rakanović (University of Novi Sad, RS) W10.7 "LegUp High-Level Synthesis and its Commercialization" Jason Anderson (University of Toronto) 11:30 - 12:00 Speaker:Jason Anderson, University of Toronto, CA Talk synopsis:High-level synthesis (HLS) is the automated synthesis of a hardware circuit from a software program First proposed in the 1980s, and spending decades on the sidelines of mainstream RTL digital design, there has been tremendous buzz around HLS technology in recent years. HLS is on the upswing as a design methodology for field-programmable gate arrays (FPGAs) to improve designer productivity and ultimately, to make FPGA technology accessible to software engineers having limited hardware expertise. The hope is that down the road, software developers can use HLS to realize FPGA-based accelerators customized to applications that work in tandem with standard processors to raise computational throughput and energy efficiency. In this talk, I will overview the trends behind the recent drive towards FPGA HLS and why the need for, and use of, HLS will only become more pronounced in the coming years. The talk will highlight current HLS research directions and expose some of the challenges for HLS that may hinder its update in the digital design community. I will describe work underway in the LegUp HLS project at the University of Toronto -- a publicly available HLS research tool that has been downloaded by over 5000 groups from around the world. LegUp HLS technology is being commercialized in a start-up company, LegUp Computing Inc. (https://www.legupcomputing.com/), which was founded in 2015 and received seed funding from Intel Capital in 2018. A key value proposition of LegUp HLS is FPGA-vendor agnosticism — synthesized circuits can be targeted to any FPGA. Speaker biography W10.8 Lunch break 12:00 - 13:00 W10.9 Panel discussion: "How does one commercialise/undertake research on open-source EDA/IP?" [nid:66134] 12:45 - 13:30 Panelists:Andrea Borga, oliscience, NL Ulrich Drepper, Red Hat, DE Hipolito Guzman, University of Sevilla, ES Clifford Wolf, Symbiotic EDA, AT Panellists: Andrea Borga (Oliscience, Netherlands) -- biography Uli Drepper (Red Hat, Germany) -- biography Hipólito Guzmán (University of Seville, Spain) -- biography Clifford Wolf (Symbiotic EDA, Austria) -- biography will be discussing whether it is possible to build a (stable!) business or research group around open-source -- when the things that you are building is ostensibly given away for free. Topics explored will be panellist's experiences with doing this, their opinions on the various open-source licenses (copyleft versus permissive) in the context of hardware, their views on whether open and closed-source can co-exist, and the momentum within the EU to mandate "open access" research.Panelists: W10.10 "VHDL Reuse: from Vendor Independence to Open Source" Daniel van der Schuur (ASTRON, Netherlands) 13:30 - 14:00 Speaker:Daniel van der Schuur, ASTRON, NL Talk synopsis:ASTRONs mission is to make discoveries in radio astronomy happen. The high performance streaming data systems we build to do that naturally have FPGAs at their hearts. To balance project requirements, cost and availability of FPGA devices, ASTRON uses an approach that is both vendor and application independent. With generic, universal FPGA platforms (UniBoard, UniBoard2, Perentie), new science applications can take advantage of already available hardware. By also having a vendor independent VHDL library and tool flow, new FPGA hardware can also be adopted/developed with minimal firmware rework needed. This talk is about the advantages of vendor independence and how we chose to implement this, covering VHDL source code, vendor IP, library structures and simulation and synthesis tools. Another important aspect is the automated regression testing of the firmware library as it is updated on a daily basis. All this is made possible and structured by ASTRONs scripted tool flow, which is to be released as open source on OpenCores.org. Finally, this talk will cover how and why ASTRON is going to release its firmware library on OpenCores, and the technical challanges in doing so. Speaker biography:Daniel van der Schuur is a digital designer at the Netherlands Institute for Radio Astronomy (ASTRON). As ASTRON designs, builds and operates complex high performance hybrid (FPGA, GPU, CPU, fiber networks) systems to make new discoveries, Daniel is passionate about reducing the time to science - from streaming system design to VHDL implementation. W10.11 Session 2 -- Lightning Talks 14:00 - 14:30 Enabling FPGA Domain-specific Compilers Through Open Source Alireza Kaviani and Chris Lavin (Xilinx Research Labs, USA) Minitracer: A minimalist requirements tracer for HDL designs Carlos López-Melendo and Hipólito Guzmán-Miranda (University of Seville, ES) OpenFPGA: a Complete Open Source Framework for FPGA Prototyping Baudouin Chauviere, Aurélien Alacchi, Edouard Giacomin, Xifan Tang and Pierre-Emmanuel Gaillardon (University of Utah, USA) Please check website for the most up-to-date list of speakers: https://osda.gitlab.io/ W10.12 Coffee break 2 + Posters 14:30 - 15:00 W10.13 "UVVM - The fastest growing FPGA verification methodology world-wide!" Espen Tallaksen (Bitvis, Norway) 15:00 - 15:45 Speaker:Espen Tallaksen, Bitvis, NO Talk synopsis:On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with only minor adjustments and no extra cost. For an FPGA design we all know that the architecture - all the way from the top to the micro architecture - is critical for both the FPGA quality and the development time. It should really be obvious that this also applies to the testbench. UVVM (the open source Universal VHDL Verification Methodology) was developed to solve this and will reduce the verification time significantly while at the same time improving the product quality. UVVM provides a very simple and powerful architecture that allow designers to build their own test harness much faster than ever before - using a mix of their own and open source verification components. UVVM also provides an architecture, methodology and library to allow VHDL verification components to be made extremely efficiently. And maybe the most important feature - UVVM allows the best possible testbench and test case overview using high level commands for both DUT interface control and synchronization. The great overview, maintainability, extensibility, modifiability and reuse has resulted in an extraordinary fast spread of this methodology - and according to the 2018 Wilson Research report UVVM was the by far fastest growing FPGA verification methodology over the last two years. UVVM is the new standardised VHDL testbench architecture, recommended by Doulos and backed by ESA (the European Space Agency) through a contract for further extension of the UVVM functionality. This presentation will show you how simple this is to understand, build and control. It will also show the latest features from the ESA project and further planned extensions. Speaker biography W10.14 Session 3 -- Full papers 15:45 - 16:45 PRGA: An Open-source Framework for Building and Using Custom FPGAs Ang Li and David Wentzlaff (Princeton University, USA) An Open-source Framework for Xilinx FPGA Reliability Evaluation Aitzan Sari, Vasileios Vlagkoulis and Mihalis Psarakis (University of Piraes, GR) Python Wraps Yosys for Rapid Open-Source EDA Application Development Benedikt Tutzer, Christian Krieg, Clifford Wolf and Axel Jantsch (TU Wien, AT) W10.15 "FuseSoC - Cores never been so much fun" Olof Kindgren (Qamcom Research & Technology/FOSSi Foundation) 16:45 - 17:15 Speaker:Olof Kindgren, Qamcom Research & Technology, SE Talk synopsis:In many ways, HDL developers have been many years behind their counterparts in the software world. One such area is core management. Where the software developers simply specify which libraries they depend on, HDL developers rely on copying around source code. Where software developers can select their build tool with a flick of a switch, HDL developers use tool-specific project files powered by custom makefiles. FuseSoC rectifies this by bringing a modern package manager and a uniform build system to HDL developers, making it easy to reuse existing code, change tools and move projects between FPGAs from different vendors. Having been around for seven years there are now hundreds of FuseSoC-compatible cores and 14 different simulation, synthesis and lint tools supported. This presentation will give an overview of where FuseSoC can help spending less time on the cores, and more time on the core business Speaker biography:Olof Kindgren is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations. Notable work include the FuseSoc IP core package manager; SERV, the award-winning RISC-V CPU and ipyxact, the IP-XACT Python library. In 2015, he also co-founded FOSSi Foundation, a vendor-independent organization with the mission to promote and assist Open Source Silicon in academia, the industry and for hobbyists alike. W10.16 Closing remarks 17:15 - 17:30 W10.17 Workshops end 17:30 - 17:30