Robert Wille, Johannes Kepler Universität Linz, AT (Contact Robert Wille)
All registered conference delegates and exhibition visitors are kindly invited to join the DATE 2018 Welcome Reception & subsequent PhD Forum, which will take place on Monday, March 19, 2018, from 1800 - 2100 in "Saal 1" of the ICC Dresden.
The PhD Forum of the DATE Conference is a poster session and a buffet style dinner hosted by the European Design Automation Association (EDAA), the ACM Special Interest Group on Design Automation (SIGDA), and the IEEE Council on Electronic Design Automation (CEDA). The purpose of the PhD Forum is to offer a forum for PhD students to discuss their thesis and research work with people of the design automation and system design community. It represents a good opportunity for students to get exposure on the job market and to receive valuable feedback on their work.
| Time | Label | Session |
|---|---|---|
| 18:00 | FM01 | Reception & PhD Forum, hosted by EDAA, ACM SIGDA, and IEEE CEDA Chair: |
| 18:00 | FM01-1 | Adaptive Runtime Resource Management for Mobile CMPs through Self-awareness Bryan Donyanavard, University of California at Irvine, US Address and Affiliation: Department of Computer Science Donald Bren School of Information and Computer Sciences University of California, Irvine Irvine, CA 92697-3435, USA Advisor: Nikil Dutt Email: bdonyana@uci.edu Phone: +1-661-713-7479 Thesis Summary: We explore self-awareness in resource management for mobile systems by addressing autonomy and emergent behavior as they apply to mobile MPSoCs. In our initial investigation, we implement a software hierarchical resource manager as part of the operating system for multicore platforms that controls multiple distributed leaf controllers which implement management policies. The supervisory controller provides autonomy by monitoring the operating conditions and prioritizing a small set of simple goals dynamically. The supervisory controller manages emergent behavior by coordinating the leaf controllers and their objectives in unity toward the current goal. The final contribution of this thesis will explore self-awareness in a multicore system that integrates both hardware and software resource managers. We will address emergent behavior challenges that arise when resource managers at different layers of abstraction (HW/SW) exist, with both overlapping and independent policies. We will provide autonomy for distributed machine-learning-based hardware resource managers and create a holistic self-aware resource management infrastructure through software enhancement. |
| 18:00 | FM01-3 | Optimization of Trustworthy Biomolecular Quantitative Analysis Using Cyber-Physical Microfluidic Platforms Mohamed Ibrahim, Duke University, US The thesis tackles important problems related to key stages of the biomolecular workflow. The results emerging from this book provide the first set of optimization and security methodologies for the realization of biomolecular protocols using microfluidic biochips. |
| 18:00 | FM01-5 | Analysis and Optimization of Reliability Issues of VLSI Power Grid Networks Sukanta Dey, Indian Institute of Technology Guwahati, IN Designing reliable power grids for modern chips or System-on-Chip (SoC) is the main aim of the power grid designers for reliability and longevity of the chip. Generally, due to the ill-suited design techniques large power grid networks of a modern chip suffer from serious voltage drop noises which creates reliability issues and can malfunction the chip if voltage drop noise exceeds a particular threshold value. Locating and minimizing the voltage drop noise is very much required and it is a time-consuming process. Therefore, the first part of the report introduces a fast method for locating the voltage drop noise. In the later part, a framework was devised to minimize the voltage drop noise. |
| 18:00 | FM01-6 | Computer-Aided Design for Quantum Computing Alwin Zulehner, Johannes Kepler University Linz, AT Currently, there is an ongoing "race" to build the first practically useful quantum computer between large companies like IBM, Intel, Rigetti, and Google. Although still limited by the number of available qubits and low fidelity, they provide the first step towards the dream of building a fault-tolerant quantum computer with the capability of running quantum algorithms for dedicated problems in domains such as quantum chemistry and physical simulation—or for factoring large numbers in polynomial time. The Computer-Aided Design (CAD) community needs to be ready for this revolutionizing new technology. While research on automatic design methods for quantum computers is currently underway, there is still far too little coordination between the CAD community and the quantum community. Consequently, many CAD approaches proposed in the past have either addressed the wrong problems, or failed to reach the end users. To overcome this issue, the thesis contributes solutions to actually relevant design problems that are required for making quantum computing accessible to end users. More precisely, the introduced CAD methods include the design of quantum circuits (given a high level description of the respective algorithm), their simulation, as well as technology mapping required to run the circuits on real hardware devices. |
| 18:00 | FM01-7 | New Views for Stochastic Computing: From Time-Encoding to Deterministic Processing M. Hassan Najafi, University of Louisiana at Lafayette, US Stochastic computing (SC), a paradigm first introduced in the 1960s, has received considerable attention in recent years as a potential paradigm for emerging technologies and "post-CMOS" computing. Logical computation is performed on random bitstreams where the signal value is encoded by the probability of obtaining a one versus a zero. This unconventional representation of data offers some intriguing advantages over conventional weighted binary. Implementing complex functions with simple hardware (e.g., multiplication using a single AND gate), tolerating soft errors (i.e., bit flips), and progressive precision are the primary advantages of SC. The obvious disadvantage, however, is latency. A stochastic representation is exponentially longer than conventional binary radix. Long latencies translate into high energy consumption, often higher than that of their binary counterpart. Generating bit-streams is also costly. Factoring in the cost of the bit-stream generators, the overall hardware cost of an SC implementation is often comparable to a conventional binary implementation. This dissertation begins by proposing a highly unorthodox idea: performing computation with digital constructs on time-encoded analog signals. We introduce a new, energy-efficient, high-performance, and much less costly approach for SC using time-encoded pulse signals. Instead of encoding data in space, as random bit-streams, we encode values in time. We show how analog periodic pulse signals can be used in performing essential stochastic operations. We explore the design and implementation of arithmetic operations on time-encoded data and discuss the advantages, challenges, and potential applications. The approach is an excellent fit for low-power applications that include time-based sensors, for instance, image processing circuits in vision chips. Experimental results on image processing applications show up to 99% performance speedup, 98% saving in energy dissipation, and 40% area reduction compared to prior stochastic implementations. We further introduce a novel area- and power-efficient synthesis approach for implementing sorting network circuits based on unary bit-streams. The proposed method inherits the fault tolerance and low-cost design advantages of processing random stochastic bit-streams while producing completely accurate result. Synthesis results of complete sorting networks show more than 90% area and power savings compared to the costs of the conventional binary implementation. However, the latency increases. To mitigate the increased latency, we use our developed time-encoding method. Time-based encoding of data is exploited for fast and energy-efficient processing of data with the developed sorting circuits. The approach is validated by implementing a low-cost, high-performance, and energy-efficient implementation of an important application of sorting, median filtering. Poor progressive precision is the main challenge with the recently developed deterministic methods of SC. Relatively prime stream length, clock division, and rotation of bit-streams are the three deterministic methods of processing bit-streams that are initially proposed based on unary bit-streams. For applications that slight inaccuracy is acceptable, these unary stream-based approaches must run for a relatively long time to produce acceptable results. This long processing time makes the deterministic approaches energy-inefficient compared to the conventional random stream-based SC. We propose a high-quality down-sampling method which significantly improves the processing time and the energy consumption of the deterministic methods by pseudo-randomizing bit-streams. We also propose two novel deterministic methods of processing bit-streams by using low-discrepancy sequences. Significant improvement in the processing time and energy consumption is observed using the proposed methods. We further demonstrate that computation on stochastic bit-streams has another compelling advantage: circuits naturally and effectively tolerate very high clock skew. Exploiting this advantage, we investigate Polysynchronous Clocking, a design strategy for optimizing the clock distribution networks of SC systems. Clock domains are split at a very fine level, reducing power on an otherwise large global clock tree. Each domain is synchronized by an inexpensive local clock. Alternatively, the skew requirements for a global clock tree network can be relaxed. The proposed design approach allows for a higher working frequency and so lower latency. It also results in significant area and energy savings for a wide variety of applications. Next, we develop a low-cost SC-based hardware implementation of a large Restricted Boltzmann Machine (RBM) Classifier completely on a single FPGA. Conventional binary implementation of a fully parallel design of a large neural network is expensive, involves extra design overheads, and in most cases cannot be fit on a single FPGA. We also develop a new reconfigurable architecture and methodology for synthesizing any given target function stochastically using finite state machines. When the target function is relatively complex, such as the exponentiation, the hyperbolic tangent, or high-order polynomial functions, our developed sequential logic-based implementation is more efficient than the prior combinational architectures. Our synthesis method also has the ability to implement multi-input functions at a very low cost. Compared to prior combinational logic-based approaches, the proposed reconfigurable architecture can save hardware area and energy consumption by up to 30% and 40%, respectively, while achieving a higher processing speed. Finally, as the first study of its kind to the best of our knowledge, we rethink the memory system design for SC. We integrate analog memory with conventional stochastic systems to reduce the energy wasted in conversion units. We propose a seamless stochastic system, StochMem, which features analog memory to trade the energy and area overhead of data conversion for computation accuracy. Comparing to a baseline system which features conventional digital memory, StochMem can reduce the energy and area significantly at the cost of slight loss in computation accuracy. |
| 18:00 | FM01-9 | System-level Mapping and Synthesis of Data Flow-Oriented Applications on MPSoCs Tobias Schwarzer1 and Jürgen Teich2 1Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE; 2University of Erlangen-Nuremberg, DE Design methodologies for modern Multi-Processor System-on-a-Chips (MPSoCs) need to capture the diverse and arising architectural innovations. This extended abstract presents two novel application mapping methodologies for data flow applications: First, (i) a system-level mapping and synthesis approach for multi-cores is presented that introduces a novel system compilation flow to combine system synthesis and the use of Quasi-Static Schedules (QSSs) within a Design Space Exploration (DSE). To reduce the exploration time of this approach, we additionally investigate DSE strategies that are able to dynamically trade off between (a) approximating heuristics and (b) accurate performance evaluation, i.e., compilation of the application and subsequent performance measurement on the target platform. Then, (ii) a hybrid application mapping (HAM approach on many-cores is described that combines the strengths of design-time analysis and optimization with the flexibility of adaptive run-time resource management. The design-time analysis involves a novel meta-heuristic DSE that eliminates architectural symmetries by abstracting the problem of mapping tasks to concrete instances of processors to a clustering of tasks and their mapping to processor types which serve as generic mapping constraints. Finally, for dynamic resource management, we propose with (a) a problem-specific backtracking approach and (b) an approach that adopts a general-purpose SAT solver two exact techniques for solving the mapping constraints at run-time. |
| 18:00 | FM01-14 | Compositional Circuit Design with Asynchronous Concepts Jonathan Beaumont, Imperial College London, GB Asynchronous Concepts is a domain-specific language used for capturing the behaviours of an asynchronous circuit. It features a library containing multiple levels of concepts, for signal-, gate- and protocol-level descriptions of circuits, and each concept is composable, allowing these behaviours to be automatically combined. A tool, Plato, automatically compiles Asynchronous Concept specifications, and translates these to Signal Transition Graphs, for use with existing EDA tools for verification and synthesis. A design flow for Asynchronous Concepts has also been developed, allowing a full design to be carried out through the use of Workcraft, into which Plato and Asynchronous Concepts has been integrated. |
| 18:00 | FM01-15 | Automatic Methods for the Design of Droplet Microfluidics Andreas Grimmer, Johannes Kepler University Linz, AT Microfluidics deals with the manipulation of small amounts of fluids. For implementing a microfluidic chip, droplet microfluidics using closed microchannels provides a well-established and highly potential platform. However, when designing a microfluidic network implementing the required operations, a huge number of physical specifications need to be considered. This results in a complex task, where, thus far, the designer often has very few methods to derive a design. This thesis aims to change this state of the art. To this end, this thesis contributes (1) simulation and design methods which support the design process of droplet microfluidics in general and (2) design methods for a dedicated droplet routing mechanism, which eventually can be combined to a first integrated design process. |
| 18:00 | FM01-16 | Worst-Case Execution Time Guarantees for Runtime-Reconfigurable Architectures Marvin Damschen, Lars Bauer and Joerg Henkel, Karlsruhe Institute of Technology, DE Real-time embedded systems need to be analyzable for timing guarantees. Despite significant scientific advances, however, timing analysis lags years behind current microarchitectures with out-of-order scheduling pipelines, several hardware threads and multiple (shared) cache layers. To satisfy the increasing performance demands, analyzable performance features are required. In this paper, a novel timing analysis approach is proposed that introduces processors with a runtime-reconfigurable instruction set as one way to escape the scarcity of timing-analyzable performance features. It is shown how runtime reconfiguration can be realized to adhere to timing constraints, and the problem of selecting reconfigurable custom instructions to optimize the worst-case execution time of an application is solved. An approach is presented that for the first time combines optimized static WCET guarantees and runtime optimization of the average-case execution (maintaining WCET guarantees) using runtime reconfiguration of hardware accelerators. Ultimately, runtime reconfiguration of accelerators is shown as a key feature to achieve predictable performance. |
| 18:00 | FM01-17 | Architecture and Programming Model Support For Reconfigurable Accelerators in Multi-Core Embedded Systems Satyajit Das, Université de Bretagne-Sud, FR The research for the PhD thesis was conducted at the Université Bretagne Sud, France in collaboration with University of Bologna, Italy. The Supervisors of the thesis were Philippe Coussy and Luca Benini, and the co-supervisors were Kevin Martin and Davide Rossi. The submitted text is an extended abstract of my PhD thesis. It describes the novel CGRA design, implementation, integration in a computing system for ultra-low power IoT targets, and compilation for the CGRA. It also describes the performance, area and energy results compared to the state of the art CGRA architectures. The document contains the results showcasing the efficiency of the proposed compilation flow compared to the state of the art algorithms used in the classical compilation techniques for CGRAs. Since the thesis is about energy efficient programmable accelerators in a heterogeneous platform, the proposed CGRA is integrated as a programmable accelerator in an open source multi-core platform PULP. The submitted document contains performance and energy efficiency results while operating in a heterogeneous environment compared to the homogeneous solution. Furthermore, the document is self contained with all the necessary references. I also have submitted one paper published at the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) along with the abstract. |
| 18:00 | FM01-18 | Supervised Testing of Embedded Concurrent Software Jasmin Jahic, Fraunhofer IESE, DE Finding bugs in multithreaded software is hard because of the non-deterministic interleaving of operations that threads perform on shared memory. Dynamic analysis of the execution trace is more precise than static analysis, but is still prone to false warnings due to instrumentation-based approaches for execution monitoring, ignoring implicit synchronization by scheduling, and not being able to properly cope with synchronization intentions. We describe an approach that is using non-intrusive execution monitoring, integrates scheduling synchronization with state-of-the-art Lockset algorithm for finding concurrency bugs, and considers synchronization intentions at the architectural level. |
| 18:00 | FM01-19 | Advanced 3D-Integrated Memory Subsystems for Embedded and High Performance Computing Systems Deepak Mathew, University of Kaiserslautern, DE The efficiency in terms of compute power and energy of today's computing systems are more and more limited by the underlying memory architectures. This not only applies to embedded devices, such as smartphones and tablets, but also to servers. Various applications demand for higher bandwidth (e.g. image processing, artificial neural networks etc.), larger capacity (e.g. graph processing, deep learning etc.), and better energy efficiency in the main memory system. This puts Dynamic Random Access Memory (DRAM) in the focus to improve performance and energy efficiency of advanced computing systems. Therefore, the design space of existing main memory systems, which is composed of DRAMs must be revisited and optimized to meet these new computing demands. Furthermore, the main memory system can be augmented with new emerging Non-Volatile Memory (NVM) technologies such as Resistive Random Access Memory (RRAM), 3D-Xpoint, STT-MRAM etc. These NVMs offer larger capacities and better energy efficiency at the expense of higher access latencies in comparison to DRAM. These new memory technologies are still in research or in early stages of production and thus there exists no accurate architectural models. This is one of the major challenges to incorporate these new memory technologies into the existing main memory systems. Based on the above requirements, this thesis conducted research on the following two dimensions: •Optimize the existing DRAM main memory subsystem to further improve bandwidth and energy efficiency •Incorporate new emerging Storage Class Memory (SCM) technologies (e.g. RRAM) into the main memory subsystem to increase the total memory capacity |
| 18:00 | FM01-20 | Controlling Writes for Energy Efficient Non-Volatile Cache Management in Chip Multiprocessors Sukarn Agarwal, Indian Institute of Technology Guwahati, IN Large processing demands by many cores require larger on-chip caches. Conventional caches made up of SRAM fall short in fulfilling these demands in terms of power, performance, and scalability. The evolution of Non-Volatile Memories (NVM) draws the attention of computer architects to look beyond the conventional memory technologies in the memory hierarchy. The benefits offered by these NVMs are high density, good scalability, and low static power consumption. However, such NVM caches suffer from costly write operations and weak write endurance. We present three techniques to deal with these challenges of NVM caches. To overcome the costly write operations, our first technique considers the existence of private blocks and allocates dataless entries for such blocks in the non-volatile region of a hybrid cache. In order to deal with the weak write endurance, our other two policies reduce the inter and intra-set write variations present in the cache. To reduce the intra-set write variation, our policy logically partitions the cache into multiple windows and disperses the writes among these windows by using write restriction. On the other hand, our inter-set wear leveling technique exploits the concept of Dynamic Associativity Management to redirect the writes from one set to another. We implemented our proposed techniques on a full system simulator GEM-5 and the experimental evaluations show significant improvements over the existing techniques. |
| 18:00 | FM01-21 | Design Techniques for Energy-Quality Scalable Digital Systems Daniele Jahier Pagliari, Politecnico di Torino, IT Energy-Quality (EQ) scalable digital systems systematically trade off the quality of computations with energy efficiency, by relaxing the precision, the accuracy, or the reliability of internal software and hardware components in exchange for energy reductions. This design paradigm is believed to offer one of the most promising solutions to the impelling need for low-energy computing. However, the current state-of-the-art in EQ scalable design suffers from important shortcomings. First, the great majority of techniques proposed in literature focus only on processing hardware and software components. Nonetheless, for many real devices, processing contributes only to a small portion of the total energy consumption, which is dominated by other components (e.g. I/O, memory or data transfers). Second, in order to fulfill its promises and become diffused in commercial devices, EQ scalable design needs to achieve industrial level maturity. This involves moving from purely academic research based on high-level models and theoretical assumptions to engineered flows compatible with existing industry standards. Third, the time-varying nature of error tolerance, both among different applications and within a single task, should become more central in the proposed design methods. This involves designing "dynamic" systems in which the precision or reliability of operations (and consequently their energy consumption) can be dynamically tuned at runtime, rather than "static" solutions, in which the output quality is fixed at design-time. This thesis introduces several new EQ scalable design techniques for digital systems that take the previous observations into account. Besides processing, the proposed methods apply the principles of EQ scalable design also to interconnects and peripherals, which are often relevant contributors to the total energy in sensor nodes and mobile systems respectively. Regardless of the target component, the presented techniques pay special attention to the accurate evaluation of benefits and overheads deriving from EQ scalability, using industrial-level models, and on the integration with existing standard tools and protocols. Moreover, all the works presented in this thesis allow the dynamic reconfiguration of output quality and energy consumption. |
| 18:00 | FM01-23 | MuTARe: A Multi-Target Adaptive Reconfigurable Architecture Marcelo Brandalero, UFRGS - Universidade Federal do Rio Grande do Sul, BR Adaptability is a fundamental requirement in modern computing systems since a wide range of applications with distinct requirements must efficiently execute in a single hardware. This work proposes MuTARe, a Multi-Target Adaptive Reconfigurable architecture that combines different adaptability techniques in a single design to best optimize for different targets (performance or energy), enabling better Pareto-Optimal trade-offs. MuTARe employs a reconfigurable accelerator coupled to a set of heterogeneous cores, offering the ability to create customized data paths for critical application kernels, while also providing adaptability for those code sequences that cannot be mapped to the accelerator. MuTARe can either work transparently (i.e., with no changes to binaries already deployed) or manually through instruction set extensions. In manual mode, additional support for approximate computing is provided to improve performance and energy in error-tolerant applications. |
| 18:00 | FM01-25 | Bitstream-level Proof-Carrying Hardware Tobias Wiersema, Paderborn University, DE Using a host of third party IP cores in reconfigurable designs is the de-facto standard today, to greatly increase productivity in reconfigurable hardware design. Trust in these modules is usually not warranted, however, and thus techniques that replace the need for trust with facts and proofs are sorely needed. In my project I have proposed and implemented one such technique, Proof-Carrying Hardware at the bitstream level, where it can unlock its full verification potential while maintaining its core advantage: To shift the considerable cost-of-trust from the receiving IP core customer to its vendor. |
| 18:00 | FM01-26 | Efficient Virtual Prototype Verification Techniques: Theory, Implementation and Application Vladimir Herdt, University of Bremen, DE This thesis advances the state-of-the-art on Virtual Prototype (VP) verification and analysis techniques. We provide various techniques related to verification of functional as well as non-functional properties. A particular focus of this thesis is on formal verification of SystemC-based VPs. |
| 18:00 | FM01-27 | Hybrid-DBT: Hardware-Accelerated Dynamic Binary Translation targeting VLIW processors Simon Rokicki, Irisa, FR |
| 18:00 | FM01-28 | Low-power Architectures for Automatic Speech Recognition Hamid Tabani, Barcelona Supercomputing Center, ES Automatic Speech Recognition (ASR) is one of the most important applications in the area of cognitive computing. Fast and accurate ASR is emerging as a key application for mobile and wearable devices. These devices, such as smartphones, have incorporated speech recognition as one of the main interfaces for user interaction. This trend towards voice-based user interfaces is likely to continue in the next years which is changing the way of human-machine interaction. In the first place, we have done a thorough analysis to identify the performance bottlenecks and the sources of energy drain when running ASR application on mobile and desktop CPUs. This thesis introduces several techniques at the software level to improve the efficiency of ASR systems running on modern processors. In the second place, we propose a novel register renaming technique for Out-of-Order processors, which is able to reuse single-use registers to reduce the pressure on the register file. Unlike previous works, our scheme is able to precisely recover the state of the processor after the event of branch mispredictions, interrupts and exceptions. The proposed scheme is implemented by applying some changes to the renaming table, issue queue and register files while it does not need any changes in the compiler nor the ISA. In third place, we design and propose a hardware accelerator for GMM evaluation. Our accelerator consumes less energy and outperforms CPUs and GPUs by orders of magnitude. Our accelerator implements in hardware our scheme to predict the active senones in a batch of frames. We provide a comprehensive study of different lossy and lossless compression schemes and an analysis of GMM parameters. We propose a novel clustering scheme which provides significantly higher Compression/WER ratio in comparison with traditional schemes. |
| 18:00 | FM01-30 | Low Overhead & Energy Efficient Storage Path for Next Generation Computer Systems Athanasios Stratikopoulos, The University of Manchester, GB The rise of social networks along with the growth of big data have driven storage systems to cope with large scale of data volume. In recent years, the emergence of the Non-Volatile Memory Express (NVMe) standard has enabled SSD drives to deliver high I/O rates by leveraging the fastest available interconnect (i.e. PCIe) to the processing chip. Additionally, the appearance of FPGAs in data centres is creating opportunities to accelerate not only application functionality but also OS operations. Although the majority of the servers in data centres have been connected to the FPGAs via the PCIe interconnect, there are now also available heterogeneous System on Chips (SoCs) with multi-cores and FPGAs integrated on the same die, resulting in low latency and energy efficient communication. This work analyses the source of performance overhead in existing state-of-the-art storage devices and proposes a novel low overhead and energy efficient storage path called FastPath, that operates transparently to the processing cores. The experimental results showed that FastPath can achieve up to 82% lower latency, up to 12x higher performance, and up to 10x more energy efficiency for standard microbenchmark on an Arm-FPGA Zynq 7000 SoC. Further experiments were conducted on a state-of-the-art SoC, such as the Zynq UltraScale+ MPSoC, using a real application, such as the Redis in-memory database, which received requests by the Yahoo! Cloud Serving Benchmark (YCSB). The experimental evaluation showed that FastPath achieved up to 60% lower latency and 15% higher throughput than the baseline storage path in the Linux kernel. |
| 18:00 | FM01-31 | A Model driven Framework with Assertion Based Verification Support for Embedded Systems Design Automation Muhammad Waseem Anwar, National University of Sciences & Technology (NUST), PK In this PhD thesis, a model driven framework with full Assertion Based Verification (ABV) support is introduced to perform both static as well as dynamic ABV. Firstly, a modeling methodology is proposed to model system design (structure + behavior) and verification constraints (assertions) of embedded systems. Particularly, UML and SysML based modeling approach is introduced to model system design i.e. Block Definition Diagram (BDD) is used to represent system structure and State Machine Diagram (SMD) is used to represent system behavior. Moreover, SVOCL (SystemVerilog in Object Constraint Language), an OCL temporal extension for SystemVerilog, is proposed to represent the verification constraints by means of SVA's. Furthermore, a Natural Language for Computational Tree Logic (NLCTL) is introduced to represent system assertions by means of CTL properties at higher abstraction level. Secondly, a complete transformation engine is implemented to generate synthesizable SystemVerilog RTL code, SystemVerilog Assertions code, Timed automata model and CTL properties from the source high level models. Particularly, transformation rules are developed to perform conceptual mapping between BDD / SMD constructs and SystemVerilog RTL / Timed Automata constructs. Furthermore, rules are also developed to convert SVOCL and NLCTL constraints into SVA's and CTL properties respectively. Finally, the implementation of transformation rules is carried out in JAVA language and Acceleo tool through Model-to-text transformation approach. As SystemVerilog RTL and assertions code is automatically generated from models through transformation engine, any UVM complaint simulator can be used to perform dynamic ABV. In this research, ABV is performed through QuestaSIM simulator. Similarly, UPPAAL tool is used to perform static ABV. The applicability of the proposed framework is demonstrated through eight benchmark case studies i.e. Traffic Lights Controller (TLC), Car Collison Avoidance System (CCAS), Arbiter, Elevator, Unmanned Aerial Vehicle (UAV), ATM, Train Gate and Bridge Crossing system. |
| 18:00 | FM01-32 | Optimization and Analysis for Dependable Software on Unreliable Hardware Platforms Kuan-Hsun Chen, Technical University of Dortmund, DE Due to the invention of semiconductor-based integrated circuits, embedded systems have become ubiquitous even in safety-critical domains. In these domains, the correctness of the system behaviors depends not only on the functional correctness but also upon the timeliness of the time instant at which the results are delivered. As chip technology keeps on shrinking towards higher densities and lower operating voltages, memory and logic components are now vulnerable to electromagnetic inference and radiation, leading to transient faults in the underlying hardware, which may jeopardize the correctness of software execution, so-called soft errors. Instead of sorely addressing transient faults at the hardware level, embedded-software developers have started to deploy Software-Implemented Hardware Fault Tolerance (SIHFT) techniques. However, the main expenditure is significant amount of time from the overhead of using SIHFT techniques. To support safety-critical systems, real-time systems technology have been primarily used and widely studied. Even without considering any performance overhead incurred by SIHFT techniques, making a predictable real-time system is a challenge matter. While considering hardware faults and SIHFT techniques, classic stories in real-time systems might turn over a new leaf. In this dissertation, there are three main contributions providing analyses and optimizations for transient fault-tolerance of system software. The contributions presented in this dissertation have been published in peer-reviewed international conferences and journals, and have been used by researches. |
| 18:00 | FM01-33 | Multiple NoC based Custom Implementation and Traffic Distribution to attain Energy Efficient CMPs sonal yadav, Vijay Laxmi and Manoj Singh Gaur, MNIT Jaipur, IN Multi-NoCs are primarily implemented for application-specific processors e.g. SoC, MPSoC, and FPGAs. Contrary, general-purpose processors are less explored for multi-NoCs implementations. CMPs run a wide variety of applications with unpredictable low/high heterogeneous runtime traffic variations. For these processors, it is difficult to design a static power efficient customised multi- NoC that should dynamically adapt traffic distribution according to runtime variations of fine-grain messages from computation bound to communication and memory-bound applications. We have addressed a difficult challenge to design energy efficient multi-NoC for CMPs. To attain it, NoC power consumption should be proportional to the network demand without compromising communication delays. In our thesis, multiple NoCs itself hardware implementation is customised for static power along with fine-grain traffic distribution exploration for improving energy efficiency of CMP's runtime traffic. Our novel contributions are as follows: 1) Customised Multi-NoC Architecture to Attain Power Efficiency 2) Target Multi-NoC Architecture 3) Case Study: Message Distribution Problem of Multi-NoC in CMPs 4) Runtime Adaptive Fine Grained Message Distribution for improved Runtime Utilisation of Multi-NoCs |
| 18:00 | FM01-37 | True Random Number Generators for FPGAs Bohan Yang, ESAT/COSIC and iMinds, KU Leuven, BE A True Random Number Generator (TRNG) circuit is designed to be sensitive to a particular physical phenomenon when it is in use, and to be resistant to process variations and other unwanted random physical phenomena. TRNGs are used in cryptography for generating session keys, nonces, and random challenges in various authentication protocols. The subject of my PhD thesis is the study of TRNG, which can be implemented on FPGA hardware. Our contributions to TRNG designs include two novel digital noise sources, a method to measure timing jitter, two design methodologies for online tests and the exploration of implementation tradeoffs of one post-processing algorithm. |
| 18:00 | FM01-38 | HW/SW Co-Design Methodology for Mixed-Criticality and Real-Time Embedded Systems Vittoriano Muttillo, University of L'Aquila, IT In the last years, the spread and importance of embedded systems are even more increasing, but it is still not yet possible to completely engineer their system-level design flow. The main design problems are to model functional (F) and non-functional (NF) requirements and to validate the system before implementation. Designers commonly use one or more system-level models (e.g. block diagrams, UML, SystemC, etc.) to have a complete problem view and to perform a check on HW/SW resources allocation by simulating the system behavior. In this scenario, SW tools able to support designers to reduce cost and overall complexity of systems development are even more of fundamental importance. Co-existence of functional and non-functional requirements is the most relevant challenge. Unfortunately, there are no general methodologies defined for this purpose and, often, the only option is to refer to experienced designer indications with respect to empirical criteria and qualitative assessments. In such a context, this Ph.D. work faces the problem of the HW/SW co-design of dedicated (possibly embedded and real-time) systems based on heterogeneous parallel architectures and presents a framework (with related methodology and prototypal tools), called Hepsycode, able to support the development of such kind of systems in different application domains considering mixed-criticality and real-time requirements. |
| 18:00 | FM01-41 | Improving Bundled-Data Handshake Circuits Norman Kluge, Hasso-Plattner-Institut, University of Potsdam, DE Balsa provides an open-source design flow where asynchronous circuits are created from high-level specifications, but the syntaxdriven translation often results in performance overhead. The thesis presents an adopted design flow tackling core drawbacks of the original Balsa design flow: To improve the performance of the circuits, the fact that bundled-data circuits can be divided into data and control path is exploited. Hence, tailored optimisation techniques can be applied to both paths separately. For control path optimisation, STG-based resynthesis has been used (applying logic minimisation). To optimise the data path a standard combinatorial optimiser is used. However, this removes the matched delays needed for a properly working bundled-data circuit. Therefore, two algorithms to automatically insert proper matched delays are used. Circuit latency improvements of up to 44 % and energy consumption improvements of up to 60 % compared to the original Balsa implementation can be shown. |
| 18:00 | FM01-43 | IC Design of an Inductorless DC/DC Converter with Wide Input Voltage Range in Low-Cost CMOS Gabriele Ciarpi, University of Pisa, IT This work shows the design and implementation of an inductorless DC/DC converter. It is able to convert a wide input voltage range (form 6 V to 60 V) in two regulated output voltages (5 V and 1.65 V) for low power applications. A 3D implementatio of the converter is proposed for area and cost reduction. The achieved results, from experimental measurements, prove the suitability of this integrated DC/DC converter, using 3-D technology, for applications where low-power loads (e.g., sensors, memories, and processors) have to be supplied by high-voltage power supplies. |
| 18:00 | FM01-44 | Monolithic-3D Integration based Memory Design techniques towards Robust and in-memory computing srivatsa rangachar srinivasa1, John (Jack) Sampson2, Meng-Fan (Marvin) Chang3 and Vijaykrishnan Narayanan4 1penn state university, US; 2Penn State, US; 3National Tsing Hua University, TW; 4Penn State University, US With the dominance of data-centric applications two important memory design challenges namely: 'speed and robustness' and 'energy efficiency' are of critical importance. Emerging 3D technology like Monolithic-3D integration (M3D-IC) has the potential to address both these issues in memories. In this work we exploit several key characteristics of M3D-IC to design novel SRAM based 3D memories offering reliability, multidimensional data read capability and in-memory compute support. We propose two flavors of memory designs for Boolean and search oriented in-memory computations. We also investigate architectural enhancements required to incorporate these memories into a processing environment with seamless computation offload. |
| 18:00 | FM01-47 | Cross-Layer Synthesis and Integration Methodology of Wavelength-Routed Optical Networks-on-Chip for 3D-Stacked Parallel Computing Systems Mahdi Tala, University of Ferrara, IT This work has contributed to bridge the gap between developers of silicon photonic devices and system designers through a cross-layer synthesis and integration methodology of wavelength-routed optical networks-on-chip (WRONoC). In particular, the design space of WRONoC topologies has been populated with new solutions which outperform the state of the art topologies. The work has characterized quality metrics of design points by including a high-impact component that is typically overlooked, that is the bridge with the electronic section of the system. As a result, the work has identified the most energy-efficient configurations of the network as a whole, demonstrating feasibility of 1pJ/bit signaling, provided identified cost, signal integrity and fabrication challenges are overcome. |
| 18:00 | FM01-48 | Adaptive Knobs for Resource Efficient Computing Anil Kanduri, University of Turku, FI Performance demands of emerging domains such as artificial intelligence, machine learning and vision, Internet-of-things etc., continue to grow. Given the increase in power densities, fixed power and energy budgets and thermal constraints, meeting performance requirements become challenging. This leaves an open problem on extracting the required performance within the power and energy limits, while also ensuring thermal safety. Architectural solutions including asymmetric and heterogeneous cores and custom acceleration improve performance-per-watt. Despite the efforts in architecture and run-time systems, satisfying applications' performance requirements under dynamic and unknown workload scenarios subject to varying system dynamics of power, temperature and energy requires intelligent run-time management. This dissertation proposes adaptive run-time strategies for resource efficient computing, considering unknown and dynamic workload scenarios, diverse application requirements and characteristics and variable effect of power actuation on performance. Our specific contributions are i) run-time mapping approach to improve power budgets for higher throughput, ii) thermal aware performance boosting for efficient utilization of power budget and higher performance, iii) approximation as a run-time knob exploiting accuracy-performance trade-offs for maximizing performance under power caps at minimal loss of accuracy and iv) co-ordinated approximation for heterogeneous systems through joint actuation of dynamic approximation and power knobs for performance guarantees with minimal power consumption. |
| 18:00 | FM01-52 | Device-Circuit Co-design Employing Phase Transitioning Materials for Low Power Digital Applications Ahmedullah Aziz, Purdue University, US Phase transitioning materials (PTM) belong to the family of emerging technologies which have tremendous prospect but also pose unique challenges. My doctoral research reports several innovative ideas (with thorough analyses) for devices/circuits utilizing unique properties of these materials. I have worked on different levels of abstraction (materials to systems) to properly analyze the implications of the novel techniques. I have proposed solutions to several prevailing issues in concurrent digital electronics and sought to overcome the limitations of existing technologies. I have established design methodologies for my proposed devices and circuits to enable optimization and guide future exploration of useful PTMs. |
| 18:00 | FM01-53 | Advanced CAD Frameworks for Design IP Protection Satwik Patnaik, NEW YORK UNIVERSITY, US Regular design IP may be duplicated without consent, resulting in financial loss for the IP owner. Besides, the tools and know-how for reverse engineering (RE) are becoming more widely available, thus rendering the scenario of malicious end users obtaining some IP a practical threat. Besides, adversaries in an untrustworthy fab can readily obtain the underlying IP from the design files given to them. We propose several advanced CAD frameworks, which allow concerned designers to properly protect their IP while exploring the inherent trade-offs for layout cost and commercial cost. Our techniques have been demonstrated to advance the state-of-the-art protection schemes. Besides covering regular 2D CMOS integration, we also explore emerging devices and 3D integration for their interesting prospects toward IP protection. |
| 18:00 | FM01-54 | Emerging Computing: Acceleration of Big Data Applications Mohsen Imani, University of California San Diego, US This proposal seeks to build systems capable of responding to the diverse needs in real time with orders of magnitude more energy efficient operation. We propose a novel hardware/software co-design of a hybrid Processing In-Memory platform which accelerates fundamental operations and diverse data analytic procedures using processing in-memory technology. In the hardware layer, the proposed platform has a hybrid structure comprising of two units: PIM-enabled processors and PIM-based accelerators. The PIM-enabled processors enhance traditional processors by supporting fundamental block-parallel operations inside processor cache structure and associated memory, e.g., addition, multiplication or bitwise computations. This capability will be implemented through the memory hierarchy in a similar way to the conventional architecture. To fully get the advantage of PIM for popular data processing procedures and machine learning algorithms, we design specialized accelerator blocks using in-memory processing technology. Our platform can process several applications including machine learning, graph, and query processing completely in-memory without using any processing cores. |
Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR (Contact Haralampos-G. Stratigopoulos)
Yiorgos Makris, University of Texas at Dallas, US (Contact Yiorgos Makris)
| Time | Label | Session |
|---|---|---|
| 13:30 | M01.1 | Tutorial and Conference Registration |
| 14:00 | M01.2 | Tutorials start |
| 14:00 | M01.3 | Introduction and Motivation Speakers: Part I will motivate the need, the challenges, and the benefits of using machine learning and will discuss its utility on actual test- and yield-related industrial problems. We will give an abstract representation of problems that can be tackled using machine learning. We will also illustrate the link between machine learning and semiconductor manufacturing and test. |
| 14:20 | M01.4 | Overview of Machine Learning Applications in Semiconductor Manufacturing and Test Speaker: Part II will provide a concise and comprehensive overview of applications of machine learning in semiconductor manufacturing and test. For each application, we will define the problem, we will explain how machine learning can come to the rescue, and we will show a case study on industrial datasets. Applications include: alternate test for analog/mixed-signal/RF ICs, test compaction, fault diagnosis, yield learning, post-manufacturing tuning, outlier detection, adaptive test, wafer-level spatial & lot-level spatiotemporal correlation modeling, analog test metrics estimation, neuromorphic on-chip testers, hotspot detection, board-level fault diagnosis, trimming, die inking, pre-silicon verification and post-silicon validation, yield estimation in fab-to-fab migration, yield estimation when transitioning from one design generation to the next. |
| 15:30 | M01.5 | Coffee Break for Tutorials |
| 16:00 | M01.6 | Recommendations for Practitioners Speaker: Part III will illustrate the main practical issues when applying machine learning techniques. It will provide several recommendations based on the presenters' own experience in developing several applications in the past. Practical issues that will be discussed include: types of learning machines, feature extraction, feature selection, training and validation processes, dataset preparation, limited and unbalanced datasets, non-stationary datasets, metrics for generalization error, mitigating the generalization error, explainable artificial intelligence. |
| 16:45 | M01.7 | Selected Applications in Depth Speakers: Part IV will describe in more detail selected applications of machine learning in semiconductor manufacturing and test. We will delve into the following four mainstream applications: alternate test for analog/mixed-signal/RF ICs, adaptive test, yield learning, and hotspot detection. For each application we will discuss the collection of training data, the choice of learning models, the training procedures, etc., and we will provide several cases studies on actual industrial data. |
| 17:45 | M01.8 | Emerging Applications Speaker: Part V will discuss emerging applications. In particular, we will discuss whether deep learning methods open new opportunities for solving efficiently test and semiconductor manufacturing problems. We will also discuss the "inverse" problem of testing machine learning hardware. In particular, we will discuss to what extent testing machine learning hardware is any different from testing any regular integrated circuit. We will also discuss fault tolerance methods that gain interest thanks to the integration of machine learning hardware in autonomous vehicles and systems. |
| 18:00 | M01.9 | Tutorials end |
| 18:00 | M01.10 | Welcome Reception & PhD Forum |
Tobias Kenter, University of Paderborn, DE (Contact Tobias Kenter)
| Time | Label | Session |
|---|---|---|
| 13:30 | M02.1 | Tutorial and Conference Registration |
| 14:00 | M02.2 | Tutorials start |
| 14:00 | M02.3 | OpenCL and FPGA design: common constructs and patterns Speaker: |
| 14:40 | M02.4 | Key differences between Intel FPGA and Xilinx tools: outer loop pipelining, local memory ports and replication Speaker: |
| 15:30 | M02.5 | Coffee Break for Tutorials |
| 16:00 | M02.6 | Simple, yet efficient matrix multiplication designs with OpenCL Chair:
|
| 17:10 | M02.8 | OpenCL FPGA success stories, complex design examples, libraries Speaker: |
| 18:00 | M02.7 | Tutorials end |
| 18:00 | M02.9 | Welcome Reception & PhD Forum |
Daniel Menard, INSA Rennes/IETR, FR (Contact Daniel Menard)
Alberto Bosio, INL, FR (Contact Alberto Bosio)
Olivier Sentieys, INRIA, FR (Contact Olivier Sentieys)
| Time | Label | Session |
|---|---|---|
| 13:30 | M03.1 | Tutorial and Conference Registration |
| 14:00 | M03.2 | Tutorials start |
| 15:30 | M03.3 | Coffee Break for Tutorials |
| 18:00 | M03.4 | Tutorials end |
| 18:00 | M03.5 | Welcome Reception & PhD Forum |
Basel Halak, University of Southampton, GB (Contact Basel Halak)
ChairBasel Halak, University of Southampton, GB (Contact Basel Halak)
Co-ChairMaire O'Neill, Queen's University Belfast, GB (Contact Maire O'Neill)
SpeakersBasel Halak, University of Southampton, GB (Contact Basel Halak)
Maire O'Neill, Queen's University Belfast, GB (Contact Maire O'Neill)
Yier Jin, The University of Central Florida, US (Contact Yier Jin)
Gang Qu, University of Maryland, College Park, US (Contact Gang Qu)
| Time | Label | Session |
|---|---|---|
| 13:30 | M04.1 | Tutorial and Conference Registration |
| 14:00 | M04.2 | Chair Introduction Chair: The security of the internet of things is one of the major challenges facing both engineers and researcher alike. This technology has led to billions of low power devices to become entrenched in our lives. Reports state that currently 15 billion IoT devices are currently deployed, and deployment is expected to reach 50 billion by the year 2020. This massive deployment of devices has led to significant security concerns. Various attacks have shown weaknesses in IoT infrastructure, with a swarm of light bulbs potentially leaving a city in darkness, rogue devices attacking infrastructure to attacks in critical infrastructure. This tutorial a combined effort of four leading international universities in the field of hardware-based IoT security, it aims to disseminate the latest research results and state-pf the art-techniques in this field DATE community. The tutorial will be highly beneficial for both experienced researchers and students considering delving into this topic. The tutorial has the following objectives;
|
| 14:05 | M04.3 | Hardware based Lightweight Authentication for IoT Application Speaker: In many embedded systems and the Internet of Things (IoT) applications, resources like CPU, memory, and battery power are limited that they cannot afford the classic cryptographic security solutions. Meanwhile, the security requirement on these systems/devices is not as high as the traditional secure systems. In this talk, we use authentication as an example to demonstrate how hardware and physical characteristics can help to build lightweight security primitives such as authentication protocols. More specifically, we will report our recent work that utilizes the traditional CMOS, the emerging RRAM technologies, and voltage over scaling (VoS) technique for user and device authentication as well as GPS spoofing detection. These practical approaches are promising alternatives for the classical crypto-based authentication protocols for the embedded and IoT devices in the smart world. |
| 14:45 | M04.4 | Device Attestation for IoT and Resources-Constrained Systems Speaker: In recent years we have seen a rise in popularity of networked devices. As a consequence, a need to ensure secure and reliable operation of these devices has also risen. Device attestation is a promising solution to the operational demands of embedded devices, especially those widely used in Internet of Things (IoT) and Cyber-Physical System (CPS). In this tutorial, we summarize the basics of device attestation. We then present a summary of attestation approaches by classifying them based on their functionality and reliability guarantees they provide to networked devices. Lastly, we discuss the limitations and potential issues current mechanisms exhibit and propose new research directions. |
| 15:30 | M04.5 | Coffee Break for Tutorials |
| 16:00 | M04.6 | Securing IoT Devices using Physically Unclonable Functions Speaker: Physically Unclonable Functions (PUFs) exploit the intrinsic manufacturing process variations to generate a unique signature for each silicon chip; this technology allows building lightweight cryptographic primitive suitable for resource-constrained IoT devices. The first part of this tutorial provides a comprehensive overview on the design principles of physically unclonable functions and their main evaluation metrics. The second part explains why we need the PUF technology and how to use it to build robust defense mechanisms against emerging security threats facing IoT technologies, in this context, we give specific examples that includes; secure cryptographic keys generation/storage, authentication protocols, and low cost secure sensors. The final part of this tutorial outlines the outstanding security challenges facing PUF technology and their potential countermeasures, including mathematical modelling attacks using machine-learning algorithms, side channel attacks and physical cloning attacks. The tutorial concludes with a summary of learned lessons and directions for the future |
| 16:45 | M04.7 | Practical Design Guidelines PUF using FPGA Speaker: A Physical unclonable function (PUF) is a security primitive which enables the extraction of a digital identifier from electronic devices, based on the inherent silicon variation between devices which occurs during the manufacturing process. Many PUF implementations for ASICs and FPGAs have been proposed to date. However, on FPGA they often offer insufficient uniqueness and reliability, and consume excessive FPGA resources. This talk will focus on how to design efficient, lightweight and scalable PUF identification (ID) generator circuits specifically for FPGAs that offer compact designs, high uniqueness and good reliability. It will also discuss the challenges in designing challenge-response PUF circuits on FPGAs, including their vulnerability to machine-learning attacks. This talk will focus on how to design efficient, lightweight and scalable PUF identification (ID) generator circuits specifically for FPGAs that offer compact designs, high uniqueness and good reliability. It will also discuss the challenges in designing challenge-response PUF circuits on FPGAs, including their vulnerability to machine-learning attacks. |
Srivaths Ravi, Texas Instruments, IN (Contact Srivaths Ravi)
SpeakersPrasanth Viswanathan Pillai, Texas Instruments, IN (Contact Prasanth Viswanathan Pillai)
Srivaths Ravi, Texas Instruments, IN (Contact Srivaths Ravi)
| Time | Label | Session |
|---|---|---|
| 13:30 | M05.1 | Tutorial and Conference Registration |
| 14:00 | M05.2 | Tutorials start |
| 14:00 | M05.3 | Introduction PART A: Introduction starts with a brief overview of the top level trends in automotive and semiconductor industries that are driving various design requirements, including the emerging concerns of safety and security. |
| 14:20 | M05.4 | Automotive Functional Safety I PART B: Automotive Functional Safety I is the first of a two part module on automotive functional safety for a semiconductor developer. Using the presenters' experience in leading functional safety compliant chip development and certification, the module examines various aspects of the automotive functional safety standard ISO 26262 and its parent industrial safety standard IEC61508. We start with the foundations of functional safety including key terminology and metrics, safety compliant development process for HW/SW, component and system level safety mechanisms, and qualitative safety analysis. |
| 15:30 | M05.5 | Coffee Break for Tutorials |
| 16:00 | M05.6 | Automotive Functional Safety II PART C: Automotive Functional Safety II is the second of a two part module on automotive functional safety for a semiconductor developer. This module first covers the various techniques that are used in the quantitative safety analysis phase that follows qualitative safety analysis. We then survey the readiness of safety EDA ecosystem today from the eyes of a semiconductor developer. We conclude with emerging functional safety topics of interest and review the key changes in the 2nd edition of ISO26262. |
| 16:50 | M05.7 | Automotive Security: Moving from Ad-hoc to Standards PART D: Automotive Security: Moving from Ad-hoc to Standards is a module crafted to share the latest knowhow from a rapidly evolving domain - automotive security. The module starts with a detailed look at attack surface of an automobile and the various threat "opportunities". Then, we survey the foundational HW/SW mechanisms necessary to secure automotive electronics and also review emerging standards for secure automotive semiconductor development. Finally, we examine the curious relationship of security and safety that designers need to grapple with. |
| 18:00 | M05.8 | Tutorials end |
| 18:00 | M05.9 | Welcome Reception & PhD Forum |
Leon Stok, IBM, US (Contact Leon Stok)
SheshaShayee Raghunathan, IBM, IN (Contact SheshaShayee Raghunathan)
Leon Stok, IBM, US (Contact Leon Stok)
SheshaShayee Raghunathan, IBM, IN (Contact SheshaShayee Raghunathan)
Robert Perricone, IBM, US (Contact Robert Perricone)
| Time | Label | Session |
|---|---|---|
| 13:30 | M07.1 | Tutorial and Conference Registration |
| 14:00 | M07.2 | Tutorials start |
| 15:30 | M07.3 | Coffee Break for Tutorials |
| 18:00 | M07.4 | Tutorials end |
| 18:00 | M07.5 | Welcome Reception & PhD Forum |
Norbert Wehn, University of Kaiserslautern, DE (Contact Norbert Wehn)
Alberto Bosio, INL, FR (Contact Alberto Bosio)
Georgios Karakonstantis, Queen's University Belfast, GB (Contact Georgios Karakonstantis)
Masahiro Fujita, University of Tokyo, JP (Contact Masahiro Fujita)
Jose Luis de la Vara, Universidad Carlos III de Mardrid, ES (Contact Jose Luis de la Vara)
Cristina Dabacan, Digilent, RO (Contact Cristina Dabacan)
Norbert Wehn, University of Kaiserslautern, DE (Contact Norbert Wehn)
Paolo Burgio, University of Modena and Reggio Emilia, IT (Contact Paolo Burgio)
Marko Bertogna, Modena and Reggio Emilia, IT (Contact Marko Bertogna)
The F1/10 is an open-source, affordable, and high-performance 1/10 scale autonomous vehicle testbed. The F1/10 carries a full suite of sensors, perception, planning, control, and networking software stacks that are similar to full scale solutions. The F1/10 testbed enables research and education in autonomous and cooperative systems, making autonomy more accessible.
Indeed, a F1/10 vehicle featuring most advanced sensors can be set-up in on week with few thousands euros following our tutorials, and is currently used by universities around the world to do research in the field of computer vision, machine learning, real-time systems, autonomous systems, vehicle dynamics control, highly-cooperative fleets of vehicles and drones.
During the event, the High-Performance Real-Time Lab (HiPeRT - https://hipert.unimore.it/) from University of Modena and Reggio Emilia will bring its fully autonomous F1/10 prototypes, and perform demo sessions of:
These vehicles will participate in the 4th F1/10 International Autonomous Racing Competition (http://f1tenth.org/), which gathers researchers and makers from all around the world in two days of challenges and networking, fostering the exchange of ideas and cooperations in the community.
The competition is held twice per year between Europe and North America, and now is at its fourth edition. Last event was in Turin, and the next one will take place in Montreal, Canada in April 2019.
Join the community!
The demo sessions will take place during the break times of the Friday Workshops.
All participants, who are registered for one of the Friday Workshops, are cordially invited to join the presentation area in front of Room 1.
Jiang Xu, Hong Kong University of Science and Technology, HK (Contact Jiang Xu)
Mahdi Nikdast, Colorado State University, US (Contact Mahdi Nikdast)
Gabriela Nicolescu, Ecole Polytechnique de Montréal, CA (Contact Gabriela Nicolescu)
Sébastien Le Beux, Lyon Institute of Nanotechnology, FR (Contact Sébastien Le Beux)
Programme Committee MembersAlan Mickelson, University of Colorado Boulder, US (Contact Alan Mickelson)
Ayse Coskun, Boston University, US (Contact Ayse Coskun)
Nikos Hardavellas, Northwestern University, US (Contact Nikos Hardavellas)
Olivier Sentieys, INRIA, FR (Contact Olivier Sentieys)
Tohru Ishihara, Kyoto University, JP (Contact Tohru Ishihara)
Yaoyao Ye, Shanghai Jiao Tong University, CN (Contact Yaoyao Ye)
José Abellán, Universidad Católica de Murcia (UCAM), ES (Contact José Abellán)
Yoan Léger, CNRS – FOTON, FR (Contact Yoan Léger)
| Time | Label | Session |
|---|---|---|
| 07:30 | W01.1 | Registration Desk opens |
| 08:30 | W01.2 | Workshops start |
| 08:30 | W01.3 | Introduction to OPTICS |
| 08:40 | W01.4 | From system level simulations to silicon photonic circuit fabrication 08:40 - 09:40 (Keynote) Vladimir Stojanovic, UC Berkeley (US) 09:40 - 10:00 (invited) Jean Christophe Crebier, CMP (FR) |
| 10:00 | W01.5 | Coffee break 1 |
| 10:30 | W01.6 | Silicon Photonics for on-chip interconnects, IO and computing 10:30-10:50 (invited) Timo Aalto, VTT (Finland) 10:50-11:10 (invited) Fabio Pavanello, IMEC (BE) 11:10-11:30 (invited) Bert Offrein, IBM Zurich (CH) 11:30-11:50 (invited) Jun Shiomi, Kyoto University (JP) |
| 11:50 | W01.7 | Poster Presentation (session 1) Design Automation for Wavelength-Routed Optical NoCs High-Radix Nonblocking Integrated Optical Switching Fabric for Data Center Integrated spiking nanolaser BOSIM: Holistic Optical Switch Models for Silicon Photonic Networks Stochastic Computing with Integrated Optics |
| 12:00 | W01.8 | Lunch break |
| 13:00 | W01.9 | New Devices for New Architectures 13:00-13:20 (invited) Laurent Vivien, C2N (FR) 13:20-13:40 (invited) Christophe Peucheret, Foton (FR) 13:40-14:00 (invited) Fabrice Raineri, Paris-Sud University (FR) 14:00-14:20 (invited) Zheng Zhao, Zhoufeng Ying, Ray T. Chen, and David Z. Pan, The University of Texas at Austin (US) |
| 14:20 | W01.10 | Poster presentation (session 2) FODON: Ultra-High-Radix Low-Loss Optical Switching Fabric All-optical sampling with hybrid III-V on Silicon nano-resonators for photonic computing MOCA: an Inter/Intra-Chip Optical Network for Memory Enabling System-Level Design with Optical Nrworks-On-Chip Through Architecture Integration and Topology Synthesis Quantitative Analysis of Optical/Electrical Interconnects and Optical-Electrical Interfaces Light Up your Many Core Crosstalk Noise Reduction through Adaptive Power Control in Inter/Intra-Chip Optical Networks |
| 14:30 | W01.11 | Coffee break 2 |
| 15:00 | W01.12 | Toward large scale on-chip optical interconnects 15:00-15:20 (invited) Umar Khan, IMEC (BE) 15:20-15:40 (invited) Ulf Schlichtmann, TUM (DE) 15:40-16:00 (invited) Aditya Narayan, Boston University (US) 16:00-16:20 (invited) Cédric Killian, IRISA/INRIA (FR) |
| 16:20 | W01.13 | Panel: Bringing on-chip optical interconnects into the real world Davide Bertozzi, University of Ferrara (IT), chair |
| Panelists: | ||
| 17:20 | W01.14 | Concluding Remarks and Closing Session |
| 17:30 | W01.15 | Workshops end |
Kyeong-Sik Min, Kookmin University, KR (Contact Kyeong-Sik Min)
Ronald Tetzlaff, Technische Universität Dresden, DE (Contact Ronald Tetzlaff)
Fernando Corinto, Politecnico di Torino, IT (Contact Fernando Corinto)
| Time | Label | Session |
|---|---|---|
| 07:30 | W02.1 | Registration Desk opens |
| 08:30 | W02.2 | Opening session Chair: 8:30-8:45 Opening session 8:45-10:00 (Keynote) Leon O. Chua, UC Berkeley, USA (Title: No Backtracking Rules the foundation of all non-volatile memristors, will be presented by Prof. Corinto, Politecnico di Torino, Italy) |
| 10:00 | W02.3 | Coffee break 1 |
| 10:30 | W02.4 | Morning session Chair: 10:30-11:00 (Invited) Daniele Ielmini, Politecnico Milano, Italy (Title: Emerging devices and circuits for analogue in-memory computing, will be presented by Dr. Zhong Sun, Politecnico Milano, Italy) 11:00-11:30 (Invited) Hyunsang Hwang, POSTECH, Korea (Title: Resistive switching based Synapse and Threshold switching based Neuron Devices for neuromorphic system) 11:30-12:00 (Invited) Wei Lu, Univ. of Michigan, USA (Title: RRAM foundations for neuromorphic and in-memory computing systems) |
| 12:00 | W02.5 | Lunch break |
| 13:00 | W02.6 | Afternoon session#1 Chair: 13:00-13:30 (Invited) Said Hamdioui, TU Delft, Netherlands (Title: Computation-in-Memory Based on Memristive Devices: What is all about and what is still missing?) 13:30-14:00 (Invited) Mirko Prezioso, Mentium Technologies Inc., USA (Title: Memristive circuits for neurocomputing and beyond: a progress update) 14:00-14:30 (Invited) Abu Sebastian, IBM Zurich, Swiss (Title: Computing using imprecise computational memory) |
| 14:30 | W02.7 | Coffee break 2 |
| 15:00 | W02.8 | Afternoon session#2 Chair: 15:00-15:30 (Invited) Qiangfei Xia, University of Massachusetts, Amherst, USA (Title: Memristive Crossbar Arrays for Brain-Inspired Computing) 15:30-15:55 (Invited) Kyeong-Sik Min, Kookmin Univ., Korea (Title: Memristor-crossbar-based neural networks: from ideal to reality) 15:55-16:20 (Invited) Fernando Corinto, Politecnico di Torino, Italy (Title: Computing with Memristor Oscillatory Networks) 16:20-16:45 (Invited) Ronald Tetzlaff, TU Dresden, Germany (Title: Memristor Cellular Neural Network-inspired Paradigms for Signal Processing, will be presented by Dr. Ioannis Messaris, TU Dresden, Germany) 16:45-17:10 (Invited) Alon Ascoli, TU Dresden, Germany (Title: Store/Retrieve Gene Design and Analysis for Bistable-like Memristor CNN) |
| 17:30 | W02.9 | Workshops end |
Rolf Ernst, Technische Universität Braunschweig, DE (Contact Rolf Ernst)
Selma Saidi, Hamburg University of Technology, DE (Contact Selma Saidi)
Dirk Ziegenbein, Robert Bosch GmbH, DE (Contact Dirk Ziegenbein)
Sebastian Steinhorst, Technische Universität München, DE (Contact Sebastian Steinhorst)
| Time | Label | Session |
|---|---|---|
| 07:30 | W03.1 | Registration Desk opens |
| 08:30 | W03.2 | Keynotes Session Keynote 1: Challenges of Automated and Connected Driving |
| 09:50 | W03.3 | Interactive Presentations IP1: A Dependable Detection Mechanism for Intersection Management of Connected Autonomous Vehicles |
| 10:00 | W03.4 | Coffee break 1 |
| 10:30 | W03.5 | Development Approaches for Autonomous Systems 10h30 Bringing the Next Generation Robot Operating System on Deeply Embedded Autonomous Platforms |
| 12:00 | W03.6 | Lunch break |
| 13:00 | W03.7 | Dependable Autonomous Systems 13h00 Autonomous Data Center - Feedback Control for Predictable Cloud Computing |
| 14:30 | W03.8 | Coffee break 2 |
| 15:00 | W03.9 | Research Clusters on Autonomous Systems 15h00 An approach to automotive service-oriented software architectures in a multi-partner research project 16h00 Panel Discussion |
| 16:30 | W03.10 | Closing & Exhibition |
| 17:30 | W03.11 | Workshops end |
Christian Krieg, Vienna University of Technology, AT (Contact Christian Krieg)
Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE (Contact Oliver Keszöcze)
Maciej Ciesielski, University of Massachusetts, US (Contact Maciej Ciesielski)
Azadeh Davoodi, University of Wisconsin - Madison, US (Contact Azadeh Davoodi)
Görschwin Fey, Technische Universität Hamburg, DE (Contact Görschwin Fey)
Tara Ghasempouri, Tallinn University of Technology, EE (Contact Tara Ghasempouri)
Ian Harris, University of Californa Irvine, US (Contact Ian Harris)
Jan Malburg, German Aerospace Center, DE (Contact Jan Malburg)
Heinz Riener, EPFL, CH (Contact Heinz Riener)
Jannis Germany Stoppe, DFKI GmbH, DE (Contact Jannis Germany Stoppe)
Pramod Subramanyan, Indian Institute of Technology Kanpur, IN (Contact Pramod Subramanyan)
Georg Weissenbacher, Vienna University of Technology, AT (Contact Georg Weissenbacher)
Clifford Wolf, Symbiotic EDA, AT (Contact Clifford Wolf)
Cunxi Yu, EPFL, CH (Contact Cunxi Yu)
| Time | Label | Session |
|---|---|---|
| 07:30 | W04.1 | Registration Desk opens |
| 08:30 | W04.2 | Workshop opening Moderators: |
| 08:45 | W04.3 | Invited talk: Addressing Integrated Circuit Integrity Using Statistical Analysis and Machine Learning Techniques Speaker: Bio: Burcin Cakir received her B.S. degree from Electrical Engineering Department of Bilkent University, and her Ph.D. degree from Princeton University. Her research motivation is formulating models that can represent real systems accurately and express mathematical bases/frameworks for further analysis. She had experience in developing algorithms and analyses to help design secure hardware systems. She is a recipient of Francis Robbins Upton Fellowship award from Princeton University. Her work on Hardware Trojan detection received Best Paper Award at DATE Conference (2015). She also has served as a referee on various journals and conferences and gave workshop and seminar talks. Besides her work at Princeton, she also had experience in industry research with two internships at Microsoft Research (MSR) in Redmond and Cambridge Labs. |
| 09:30 | W04.4 | Paper presentation block 1 Moderators: |
| 09:30 | W04.4.1 | Towards Gate-Level Design of QCA Circuits |
| 10:00 | W04.5 | Coffee break 1 |
| 10:30 | W04.6 | Paper presentation block 2 Moderators: |
| 10:30 | W04.6.1 | Deductive Binary Code Verification Based on Source-Code-Level ACSL Specifications |
| 11:00 | W04.6.2 | Extracting Assertions for Conflicts in HDL Descriptions |
| 11:30 | W04.6.3 | Complete Specification Mining |
| 12:00 | W04.7 | Lunch break |
| 13:00 | W04.8 | Invited talk: Reverse Engineering for Security: Views From the Top and the Bottom. Moderators: Speaker: Abstract: Recent years have seen much hand-wringing about security concerns posed by malicious hardware designs. Seemingly at the other end of the spectrum are inadvertent hardware design flaws that lead to security breaches. The former concern has led to development of algorithmic reverse engineering techniques, Hardware Trojan detection algorithms and side-channel analysis algorithms -- all of which aim to algorithmically discover malicious behavior from the bottom up. The latter concern has led to the progress in top-down security verification techniques based on model checking and syntax-guided synthesis. In this talk, I will try to review some recent progress in both top-down and bottom-up analysis. I will argue that both top-down and bottom-up techniques can synergistically benefit each other. Bio: Pramod Subramanyan is an Assistant Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology, Kanpur. He obtained his Ph.D. from Princeton University and subsequent to his Ph.D., he was a postdoctoral scholar at the University of California, Berkeley. His research interests lie at the intersection of systems security and formal methods. His current research is focused on system-building techniques that can provide verifiable guarantees of security. Pramod's research has won several awards including the Best Paper Award at the ACM Computer and Communication Security conference, the ACM SIGDA Outstanding Ph.D. Dissertation in Electronic Design Automation Award, the Best Student Paper Award at IEEE Symposium on Hardware-Oriented Security and Trust. |
| 14:00 | W04.9 | Paper presentation block 3 Moderators: |
| 14:00 | W04.9.1 | Generating a UML Sequence Diagram from a Natural Language Scenario Description |
| 14:30 | W04.10 | Coffee break 2 |
| 15:00 | W04.11 | Invited talk: Project Trellis: open bitstream documentation for the Lattice ECP5 FPGAs Moderators: Speaker: Abstract: |
| 16:00 | W04.12 | Paper presentation block 4 Moderators: |
| 16:00 | W04.12.1 | Engineering of an Effective Automatic Assertion-based Verification Platform |
| 16:30 | W04.12.2 | Design Mapper: Dataflow Analysis for Better Floorplans |
| 17:00 | W04.12.3 | Using AI for the Performance Verification of High-End Processors |
| 17:15 | W04.12.4 | The Verification Cockpit - Harnessing Data Analytics for the HW Verification Process |
| 17:30 | W04.13 | Workshops end |
Alberto Bosio, INL, FR (Contact Alberto Bosio)
General Co-ChairsMario Barbareschi, University of Naples Federico II, IT (Contact Mario Barbareschi)
Claus Braun, University of Stuttgart, DE (Contact Claus Braun)
| Time | Label | Session |
|---|---|---|
| 07:30 | W05.1 | Registration Desk opens |
| 08:30 | W05.2 | Opening Session |
| 09:00 | W05.3 | Keynote 1 Keynote "Transprecision Computing for Energy-Efficiency" by dr. Cristiano Malossi from IBM Research of Zurich |
| 10:00 | W05.4 | Coffee Break |
| 10:30 | W05.5 | Technical Session 1 Resilience-based Mapping of Deep Neural Network Operations to Approximate Computing Units Reliability Evaluation of Mixed-Precision Architectures Approximate Computing of Transcendental Functions Applied to Artificial Neural Networks |
| 12:00 | W05.6 | Lunch break |
| 13:00 | W05.7 | Invited Talk Approximate Computing in HPC: building from ground up |
| 13:30 | W05.8 | Keynote 2 Keynote : Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, Systems. and Approximations" by prof. Kaushik Roy from School of Electrical and Computer Engineering of Purdue University. |
| 14:30 | W05.9 | Coffee Break |
| 15:00 | W05.10 | Technical Session 2 Targeting Approximation through Data Lifetime: A Quest for Optimization Metrics Approximate Computing for Sizing Hidden Layer in CNN |
Oliver Bringmann, Eberhard Karls Universität Tübingen, DE (Contact Oliver Bringmann)
Wolfgang Ecker, Infineon Technologies, DE (Contact Wolfgang Ecker)
Wolfgang Müller, Universität Paderborn, DE (Contact Wolfgang Müller)
Daniel Müller-Gritschneder, Technische Universität München, DE (Contact Daniel Müller-Gritschneder)
| Time | Label | Session |
|---|---|---|
| 07:30 | W06.1 | Registration Desk opens |
| 08:45 | W06.2 | Opening |
| 09:00 | W06.3 | Session I: Invited Industrial Session |
| 09:00 | W06.3.1 | Proposals for IP-XACT Extensions from Embedded Controller Use Cases Michael Velten and Wolfgang Ecker, Infineon Technologies, DE |
| 09:30 | W06.3.2 | Automation of Embedded Software Development for Smart Sensor ASICs Aljoscha Kirchner1, Jan-Hendrik Oetjens1 and Oliver Bringmann2 1Robert Bosch GmbH, DE; 2Universität Tübingen, DE |
| 10:00 | W06.4 | Break: Refreshments & Poster Discussions |
| 10:30 | W06.5 | Session II: Applications for the IOT |
| 10:30 | W06.5.1 | An Experimental Platform for Cooperative Work with Context-Oriented Programming and Hardware Reconfiguration for Industry IoT Harumi Watanabe1, Mikiko Sato1, Ikuta Tanigawa2, Mariya Kawamura1, Nobuhiko Ogura3 and Takeshi Ohkawa4 1Tokai University, JP; 2Kyushu University, JP; 3Tokyo City University, JP; 4Utsunomiya University, JP |
| 10:45 | W06.5.2 | Inertial Sensor Based Robot Gesture Detection for Safe Human-Robot Interaction Johann-Peter Wolff1, Christian Haubelt1, Rolf Schmedes2 and Kim Grüttner2 1University of Rostock, DE; 2OFFIS - Institut für Informatik, DE |
| 11:00 | W06.5.3 | An Open-Source, IoT-Tailored Face Detection Software Panagiotis Kalodimas1, Antonis Nikitakis1 and Ioannis Papaefstathiou2 1Technical University of Crete, GR; 2Aristotle University of Thessaloniki, GR |
| 11:15 | W06.5.4 | Component-based FPGA Development of Intelligent Image Processing for Industrial IoT Devices Kenta Arai, Takeshi Ohkawa, Kanemitsu Ootsu and Takashi Yokota, Utsunomiya University, JP |
| 11:30 | W06.6 | Session III: Invited Industrial Presentations |
| 11:30 | W06.6.1 | BaSys 4.0: An Open-Source Middleware for the Industrial Internet of Things Frank Schnicke, Markus Damm and Thomas Kuhn, Fraunhofer IESE, DE |
| 12:00 | W06.7 | Break: Lunch & Poster Discussions |
| 13:00 | W06.8 | Session IV: Safety, Security, Performance and Power Optimizations & Analysis for the IoT |
| 13:00 | W06.8.1 | Firmware-Driven Optimization of the Hardware/Software Interface for IoT Nodes Rafael Stahl, Daniel Müller-Gritschneder and Ulf Schlichtmann, TUM, DE |
| 13:15 | W06.8.2 | A Heuristic for Multi Objective Software Application Mappings on Heterogeneous MPSoCs Gereon Führ1, Ahmed Hallawa1, Rainer Leupers1, Gerd Ascheid1 and Awaid-Ud-Din Shaheen2 1RWTH Aachen, DE; 2Silexica GmbH, DE |
| 13:30 | W06.8.3 | Source-level Power Simulation of IoT Firmware for Energy Evaluation Michael Kuhn and Oliver Bringmann, Universität Tübingen, DE |
| 13:45 | W06.8.4 | Towards Distributed Runtime Monitoring with C++ Contracts Rolf Schmedes and Philipp Ittershagen, OFFIS - Institut für Informatik, DE |
| 14:00 | W06.8.5 | Security Chain Tool for IoT Secure Applications Christoph Schmittner and Abdelkader Magdy Shaaban, Austrian Institute of Technology, AT |
| 14:15 | W06.8.6 | QEMU for Dynamic Memory Analysis of Security Sensitive Software Peer Adelt1, Bastian Koppelmann1, Wolfgang Müller1, Christoph Scheytt1 and Benedikt Driessen2 1Heinz Nixdorf Institute, DE; 2Kasper & Oswald GmbH, DE |
| 14:30 | W06.9 | Break: Refreshments & Poster Discussions |
| 15:00 | W06.10 | Session V: Model Based Frameworks for IoT Software Development |
| 15:00 | W06.10.1 | A Syntax Oriented Code Generation Approach for SoC Design Automation Michael Werner, Andreas Neumeier and Wolfgang Ecker, Infineon Technologies, DE |
| 15:15 | W06.10.2 | Ecosystem for Agile Design of Future-Proof RISC-V Based IoT-Devices Leon Hielscher1, Frederik Haxel1, Arthur Kühlwein1, Sebastian Reiter1, Alexander Viehl1, Oliver Bringmann1 and Wolfgang Rosenstiel2 1FZI Forschungszentrum Informatik, DE; 2University of Tübingen, DE |
| 15:30 | W06.10.3 | Towards Stateflow Model-Aware Debugging Using Model-to-Source Tags with LLDB Bewoayia Kebianyor, Philipp Ittershagen and Kim Grüttner, OFFIS - Institut für Informatik, DE |
| 15:45 | W06.10.4 | Tackling the Challenges of Internet-of-Things-Development Using Models Rupert Schlick and Willibald Krenn, Austrian Institute of Technology, AT |
| 16:00 | W06.11 | Plenary Discussions & Closing |
| 16:15 | W06.12 | End of Workshop |
Hussam Amrouch, Karlsruhe Institute of Technology (KIT), DE (Contact Hussam Amrouch)
Jörg Henkel, Karlsruher Institut für Technologie (KIT), DE (Contact Jörg Henkel)
Marilyn Wolf, Georgia Tech, US (Contact Marilyn Wolf)
| Time | Label | Session |
|---|---|---|
| 07:30 | W07.1 | Registration Desk opens |
| 08:30 | W07.2 | Workshops start |
| 10:00 | W07.3 | Coffee break 1 |
| 12:00 | W07.4 | Lunch break |
| 14:30 | W07.5 | Coffee break 2 |
| 17:30 | W07.6 | Workshops end |
Ali Javadi, IBM, US (Contact Ali Javadi)
Tiziano Villa, Università di Verona, IT (Contact Tiziano Villa)
Luca Carloni, Columbia University, US (Contact Luca Carloni)
Luca Amaru, Synopsys, US (Contact Luca Amaru)
Anna Bernasconi, Università di Pisa, IT (Contact Anna Bernasconi)
Valentina Ciriani, University of Milano, IT (Contact Valentina Ciriani)
Jordi Cortadella, Universitat Politecnica de Catalunya, ES (Contact Jordi Cortadella)
Masahiro Fujita, University of Tokyo, JP (Contact Masahiro Fujita)
Jie-Hong Jiang, National Taiwan University, TW (Contact Jie-Hong Jiang)
Weikang Qian, Shanghai Jiao Tong University, CN (Contact Weikang Qian)
Sherief Reda, Brown University, US (Contact Sherief Reda)
Marc Riedel, University of Minnesota, US (Contact Marc Riedel)
Tsutomu Sasao, Meiji University, JP (Contact Tsutomu Sasao)
Mathias Soeken, Integrated System Laboratory – EPFL, CH (Contact Mathias Soeken)
Andres Takach, Calypto Design Systems, US (Contact Andres Takach)
Gabriella Trucco, Universita' degli Studi di Milano, IT (Contact Gabriella Trucco)
Luca Carloni, Columbia University, US (Contact Luca Carloni)
Tiziano Villa, Università di Verona, IT (Contact Tiziano Villa)
Eddie Hung, University of British Columbia, CA (Contact Eddie Hung)
Christian Krieg, Vienna University of Technology, AT (Contact Christian Krieg)
Clifford Wolf, Symbiotic EDA, AT (Contact Clifford Wolf)
Andrea Borga, oliscience, NL (Contact Andrea Borga)
Xin Fang, Northeastern University, US (Contact Xin Fang)
Shane Fleming, Imperial College London, GB (Contact Shane Fleming)
Hipolito Guzman-Miranda, University of Sevilla, ES (Contact Hipolito Guzman-Miranda)
Steve Hoover, Redwood EDA, US (Contact Steve Hoover)
Dirk Koch, University of Manchester, GB (Contact Dirk Koch)
Mieszko Lis, University of British Columbia, CA (Contact Mieszko Lis)
Brent Nelson, Brigham Young University, US (Contact Brent Nelson)
Steffen Reith, RheinMain University of Applied Sciences, DE (Contact Steffen Reith)
Davide Rossi, University of Bologna, IT (Contact Davide Rossi)
| Time | Label | Session |
|---|---|---|
| 07:30 | W10.1 | Registration Desk opens |
| 08:30 | W10.2 | Workshops start |
| 08:45 | W10.3 | Welcome |
| 09:00 | W10.4 | Keynote -- "PULP: An Open-Source RISC-V Based Multi-Core Platform for In-Sensor Analytics" Davide Rossi (University of Bologna) Speaker: Talk synopsis: Speaker biography: |
| 10:00 | W10.5 | Coffee break 1 + Demos
|
| 10:30 | W10.6 | Session 1: Full Papers
|
| 11:30 | W10.7 | "LegUp High-Level Synthesis and its Commercialization" Jason Anderson (University of Toronto) Speaker: Talk synopsis: |
| 12:00 | W10.8 | Lunch break |
| 12:45 | W10.9 | Panel discussion: "How does one commercialise/undertake research on open-source EDA/IP?" [nid:66134] Panelists: Panellists:
will be discussing whether it is possible to build a (stable!) business or research group around open-source -- when the things that you are building is ostensibly given away for free. Topics explored will be panellist's experiences with doing this, their opinions on the various open-source licenses (copyleft versus permissive) in the context of hardware, their views on whether open and closed-source can co-exist, and the momentum within the EU to mandate "open access" research. |
| Panelists: | ||
| 13:30 | W10.10 | "VHDL Reuse: from Vendor Independence to Open Source" Daniel van der Schuur (ASTRON, Netherlands) Speaker: Talk synopsis: Speaker biography: |
| 14:00 | W10.11 | Session 2 -- Lightning Talks
|
| 14:30 | W10.12 | Coffee break 2 + Posters |
| 15:00 | W10.13 | "UVVM - The fastest growing FPGA verification methodology world-wide!" Espen Tallaksen (Bitvis, Norway) Speaker: Talk synopsis: |
| 15:45 | W10.14 | Session 3 -- Full papers
|
| 16:45 | W10.15 | "FuseSoC - Cores never been so much fun" Olof Kindgren (Qamcom Research & Technology/FOSSi Foundation) Speaker: Talk synopsis: Speaker biography: |
| 17:15 | W10.16 | Closing remarks |
| 17:30 | W10.17 | Workshops end |
For speakers and session chairs and co-chairs on the day of their presentation.
An important opportunity to meet other members of your session and receive AV instructions.
Since the introduction of Park Distance Control and Adaptive Cruise Control in the Mid 2000s, PORSCHE follows a systematic strategy to adapt driver assistance and automated driving to their product lines. There is no contradiction to the philosophy of a sports car: customers that enjoy driving on their own in case of appropriate traffic conditions expect significant ease of driving in stressful, time-consuming situations like traffic jams, or heavily occupied parking spaces. Furthermore, new functionalities like the predictive Innodrive system enabling efficient cruise control based on sophisticated planning algorithms provides a perfect contribution to the PORSCHE Intelligent Performance strategy.
Although the common discussion focuses on the higher levels of automation from SAE Level 3 to Level 4, at least for the next decade Level 1 and 2 systems will play a significant role being the technological state-of-the-art for a majority of cars. Therefore, PORSCHE focuses on increasing the performance and functionality of Level1/2 driver assistance system in parallel to participating in development programs to enable Level3/4 automated driving. This offers the opportunity to systematically build the necessary competency both in the technological fields of sensing, sensor fusion, planning and control as well as the necessary processes, methods and tools that are mandatory to develop, approve and release higher level automated systems. Systems Engineering has to be combined with approaches to process very large amounts of data whereas traditional random road based testing has to be replaced by a combination of virtual and systematic real world testing. Last but not least, a new end-to-end EE architecture is necessary to provide the seamless integration of the vehicle into an IT based service infrastructure.
The keynote will address the following topics:
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.
Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.
Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
In this session the Electronic System Design Alliance will present their newest initatives and results. Mentor, a Siemens Business will discuss approaches for application of Machine Learning for designing and producing microelectronics products. IngeniArs will analyze scenarios for realizing smart edge devices by using accelerators for executing Machine Learning and Deep Learning algorithms.
The Golden Age of machine learning is upon EDA. Over the past four years, we have seen large EDA suppliers and customers grow their internal ML teams and strategies, and ML research projects are emerging in all areas of EDA. But, we have not yet seen much of this investment convert into real production flows and work. This talk reviews a set of challenges that make it difficult to bring ML solutions to production for semiconductor design, and discusses approaches for solving them. We will discuss how these approaches are already benefiting variation-aware design and characterization flows, and the broader applicability to analog and digital verification.
Machine Learning, Deep Learning and AI are a technology that lots of enterprise are using to provide smarter services to their customer. Usually, data are acquired by sensors and then sent to a cloud or a remote server to perform inference and get the results. This is no longer the only way, in fact, commercial products are already available to offload the execution of ML and deep-Learning algorithms from the CPU of small devices. In this talk we will analyse some scenarios in which these accelerators, like Neural Compute Stick, can be useful in meeting design goals and allow the realization of smarter edge device.
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.
Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.
Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
Collaborative interdisciplinary research is considered of paramount importance today for the achievement of breakthroughs and jumps in technical innovation. In this session, program director Dr. Andreas Raabe introduces which types of collaborative funding instruments are offered by the Deutsche Forschungsgemeinschaft (DFG) in Germany, but also funding opportunities for international cooperations. After an introduction into different funding instruments for short, medium and long term collaborative research, concrete example initiatives in the scope of topics of DATE will be shortly introduced and summarized by representatives with a majority of these initiatives also exhibiting during the conference week.
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.
Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.
Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
This publisher´s session invites all attendees to discuss how and why to publish their research work with Springer Nature. Charles Glaser, Editorial Director for Springer, will present his advice for collaboration in research dissemination. He will be available in this session, as well as the entire exhibition, to discuss the publication of your next book.
For speakers and session chairs and co-chairs on the day of their presentation.
An important opportunity to meet other members of your session and receive AV instructions.
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.
Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.
Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
One of the most demanding challenge for Europe's Industry is to implement information technologies. Besides technical problems during the installation and replacement of analogue processes, digitalization touches the whole process of interaction and exchange in and outside companies. Threats like hacks with misuse of personal data, system blackouts or lack of qualified IT experts are heavily discussed and prevent many players, especially smaller SMEs, from fostering digitalization so far. But even if all those problems will be solved the question about the contribution of digitalization to CO2 reduction and lower energy consumption is still remaining. New promising innovations like blockchain technologies seem to completely fail at least from the energy saving point of view. To receive solutions for all aspects of digitalization with focus on Cyber Physical Systems (CPS) and via the instrument of Digital Innovation Hubs (DIH) the European Commission started its Smart Anything Everywhere (SAE) Initiative to foster transfer from research to business. The Horizon 2020 Innovation Action TETRAMAX is one of them offering smart and individual funding schemes for European university-industry cooperation. The technology transfer concept focuses on direct cooperation - Technology Transfer Experiments (TTX) - between universities and SMEs supported by open innovation networks and other stakeholders like investors. The session speakers will demonstrate in a pragmatic way and by use of concrete examples how technology transfer can be initiated and implemented in practice and to overcome the associated pitfalls and use the innovation opportunities. Amongst others, the goal is to motivate more stakeholders to engage in international technology transfer and become part of TETRAMAX.
During the session, TETRAMAX representatives will share their experiences and insights as researcher, founder, entrepreneur, investor or consultant.
TETRAMAX as part of the SAE Initiative started in 2017 and is funded by Horizon 2020. The project supports application experiments between academia and industry (SMEs) related to Internet of Things (IoT) technologies and focusing on customized low energy computing (CLEC).
The project builds on three major activity lines:
(1) Stimulating, organizing, co-funding, and evaluating different types of cross-border Application Experiments, providing "EU added value" via innovative CLEC technologies to first-time users and broad markets in European ICT-related industries,
(2) Building and leveraging a new European CLEC competence center network, offering technology brokerage, one-stop shop assistance and CLEC training to SMEs and mid-caps, and with a clear evolution path towards new regional digital innovation hubs where needed, and
(3) Paving the way towards self-sustainability based on pragmatic and customized long-term business plans
The project impact will be measured based on 50+ performance indicators. The immediate ambition of TETRAMAX within its duration is to support 50+ industry clients and 3rd parties in the entire EU with innovative technologies, leading to an estimated revenue increase of 25 Mio. € based on 50+ new or improved CLEC-based products, 10+ entirely new businesses/SMEs initiated, as well as 30+ new permanent jobs and significant cost and energy savings in product manufacturing. Moreover, in the long term, TETRAMAX will be the trailblazer towards a reinforced, profitable, and sustainable ecosystem infrastructure, providing CLEC competence, services and a continuous innovation stream at European scale, yet with strong regional presence as favoured by SMEs.
EVErMORE: Energy-efficient Variation awarE MulticORE: EVErMORE TTX experiment aims at developing the next generation [GAP-8 IoT processor from GreenWaves Technologies](https://greenwaves-technologies.com/en/gap8-the-internet-of-things-iot-application-processor/). Exploiting the adaptive management architecture for process and temperature compensation developed at University of Bologna, coupled to the low-voltage capabilities of 22nm FD-SOI technology, is expected to improve the energy efficiency of current generation GreenWaves Technology processors by 6x, enabling new applications and opening new market opportunities.
Carrots: Cooperative ARchitecture for gaRdening with Open moniToring Systems: Tomappo is a digital gardening assistant enabling anyone to grow their own vegetables. Within Carrots, Lifely's social sensors will be customized for use with Tomappo. This will add new dimension to Tomappo leading to a better product for users and new revenue stream for company receiving technology, while also benefit the owner of the technology by providing a new use-case for their sensors.
TETRaWIN: TEchnology Transfer of computational-Rfid Wirelessly-powered IoT Nodes: This TTX will transfer the University of Salento recognized skills on wirelessly-powered Computational-RFID technology for IoT to the SME Spica, by defining a new cost-effective battery-less CLEC-based tag enabling the smart traceability of fresh and frozen fish. By performing computation, communication, and sensing to check the food product integrity, the solution will improve the SME business.
High-Performance Computing (HPC) systems are of vital importance to the progress of science and technology. Europe has made significant progress in becoming a leader in HPC through industrial and application providers. In addition, ETP4HPC is driving a European HPC vision towards exascale systems. Despite such gains, excellence in HPC systems research is fragmented across Europe. Eurolab4HPC has the bold overall goal to strengthen academic research excellence and innovation in HPC in Europe.
This talk will highlight the key instruments used to structure the European HPC community; to promote entrepreneurship by building an innovation pipeline from general purpose entrepreneurial training, business prototyping, business plan development and helping with funding and to stimulate technology transfer by connecting with other technology transfer activities and providing competitive seed funding for HPC technology transfer. With EuroLab4HPC the objective is to raise the visibility of the European HPC community, attract more participants and eventually grow the interest and impact of Europe's Exascale research.
Open innovation is based on strong networks between academia and industry. ICT developments depend greatly on open innovation due to short innovation cycles and strong competition. To build an open innovation network which operates in a regional, national and international context was the idea behind the Enterprise Europe Network which started in 2008. The overall aim is to support the competitiveness and innovation capabilities of SMEs in Europe. Today, the Enterprise Europe Network is the largest innovation network in the world. It addresses every need in the whole value chain of the innovation process - from idea to product. Bernd Janson will explain how 600 partners and over 6000 consultants worldwide work together to improve the performance of SMEs in Europe. He also explains the Network's role within Tetramax.
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.
Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.
Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
This session (registration: link) aims to bring together recruiters - mostly companies large and small, as well as universities and research centres - with potential jobseekers in the technology areas covered by DATE and HiPEAC, including:
The progamme will be tailored to the needs of the students and researchers. It will include:
For students, this session is an opportunity to:
For companies, this session provides an excellent opportunity to:
HiPEAC is European Network of Experts on High Performance and Embedded Architecture and Compilation. We organize many activities and that can help to grow your career regardless you follow an academic or industrial career or as an innovator. In our presentation you will learn about our career opportunities, internships, educational opportunities, student competitions, events, conferences and many more.
Defining a career path in today's workplace can be a real challenge. During this presentation I will guide you through the key steps of career planning, from learning how to leverage your skills to branding yourself and networking.
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.
Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.
Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
This session (registration: link) aims to bring together recruiters - mostly companies large and small, as well as universities and research centres - with potential jobseekers in the technology areas covered by DATE and HiPEAC, including:
The progamme will be tailored to the needs of the students and researchers. It will include:
For students, this session is an opportunity to:
For companies, this session provides an excellent opportunity to:
The DATE Party traditionally states one of the highlights of the DATE week. As one of the main networking opportunities during the DATE week, it is a perfect occasion to meet friends and colleagues in a relaxed atmosphere while enjoying local amenities. It is scheduled on Wednesday, March 27, 2019, from 19:30 to 23:00.
Please kindly note that it is not a seated dinner.
All delegates, exhibitors and their guests are invited to attend the party. Please note that entrance is only possible with a valid party ticket. Each full conference registration includes a ticket for the DATE Party (which needs to be booked during the online registration process though). Additional tickets can be purchased on-site at the registration desk (subject to availability of tickets). Price for extra ticket: 70 € per person.
For speakers and session chairs and co-chairs on the day of their presentation.
An important opportunity to meet other members of your session and receive AV instructions.
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.
Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.
Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
The goal of Smart Anything Everywhere (SAE) inititiave is to support SMEs, start-ups and mid-caps to enhance their products and services through the inclusion of innovative digital technologies. SAE H2020 projects provide one stop-shops to help companies to become more competitive through the adoption of the latest digital technologies. A SME tailored service is now available to provide access to R&D and digital competences, training to develop technical skills, business management support and networking opportunities. Cascade funding is available through SAE open calls, but also I4MS focusing on manufacturing.
FED4SAE project aims at bringing innovative Cyber-Physical System technologies to businesses from any sectors and any companies. The presentation of awarded projects illustrate FED4SAE one-stop-shop to accelerate CPS developments combining i) Access to leading-edge CPS platforms, Advanced Technologies, and Testbeds from Industrials and R&D centers, ii) Technical coaching from domain experts, iii) Innovation Management support, iv) Up to €60k in financial support to innovative companies plus access to further VC funding, v) and Access to potential users and suppliers across value chains throughout Europe. This session will confront the view point of large industrial, RTOs and SMEs and their targeted objectives and impact.
The goal of Smart Anything Everywhere (SAE) inititiave is to support SMEs, start-ups and mid-caps to enhance their products and services through the inclusion of innovative digital technologies. SAE H2020 projects provide one stop-shops to help companies to become more competitive through the adoption of the latest digital technologies. A SME tailored service is now available to provide access to R&D and digital competences, training to develop technical skills, business management support and networking opportunities. Cascade funding is available through SAE open calls, but also I4MS focusing on manufacturing.
FED4SAE project aims at bringing innovative Cyber-Physical System technologies to businesses from any sectors and any companies. The presentation of awarded projects illustrate FED4SAE one-stop-shop to accelerate CPS developments combining i) Access to leading-edge CPS platforms, Advanced Technologies, and Testbeds from Industrials and R&D centers, ii) Technical coaching from domain experts, iii) Innovation Management support, iv) Up to €60k in financial support to innovative companies plus access to further VC funding, v) and Access to potential users and suppliers across value chains throughout Europe. This session will confront the view point of large industrial, RTOs and SMEs and their targeted objectives and impact.
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.
Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.
Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
MATLAB and Simulink provide a rich environment for embedded-system development, with libraries of proven, specialized algorithms ready to use for specific applications. The environment enables a model-based design workflow for fast prototyping and implementation of the algorithms on heterogeneous embedded targets, such as MPSoC. A system-level design approach enables architectural exploration and partitioning, as well as coordination between SW and HW development workflows. Functional verification throughout the design process improves coverage and test-case generation while reducing the time and resources required.
In this set of tutorial sessions, you will learn
On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.
Lunch Breaks (Lunch Area)On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.
Tuesday, March 26, 2019
Wednesday, March 27, 2019
Thursday, March 28, 2019
Part 2 of tutorial (see session 11.8 for description).