11.3 More than Moore Interconnects

Time	Label	Presentation Title Authors
14:00	11.3.1	HIGH PERFORMANCE COLLECTIVE COMMUNICATION-AWARE 3D NETWORK-ON-CHIP ARCHITECTURES Speaker: Biresh Joardar, Washington State University, US Authors: Biresh Joardar, Karthi Duraisamy and Partha Pande, Washington State University, US Abstract 3D Network-on-Chip (NoC) architectures are capable of achieving better performance and lower energy consumption compared to their planar counterparts. However, conventional 3D NoCs are not efficient in handling collective communication. Existing works mainly explore Path and Tree multicast distribution schemes for 3D NoCs. However, both these mechanisms involve high network latency and lack scalability. In this work, we propose a SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) 3D NoC architecture that is capable of achieving high-performance collective communication. The proposed High-Performance SMART (HP-SMART) 3D NoC achieves 65% and 31% latency improvements compared to the existing Path and Tree multicast-based 3D NoCs respectively. HP-SMART 3D NoC also achieves significant improvement in message latency compared to its 2D counterpart. Download Paper (PDF; Only available from the DATE venue WiFi)
14:30	11.3.2	A SOFT-ERROR RESILIENT ROUTE COMPUTATION UNIT FOR 3D NETWORKS-ON-CHIPS Speaker: Alexandre Coelho, TIMA Laboratory, FR Authors: Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Juan Fraire and Raoul Velazco, Université Grenoble Alpes, CNRS, Grenoble INP, FR Abstract Three-dimensional Networks-on-Chips (3D-NoCs) have emerged as an alternative to further enhance the performance, functionality, and packaging density of 2D-NoCs. However, the increasing complexity of NoC routers, the continuous miniaturization of silicon technology, the lower operating voltages, and the higher operating frequencies have made the NoC increasingly vulnerable to soft errors. In particular, transient faults occurring in the route computation unit (RCU) can provoke misrouting which may lead to severe effects such as deadlocks or packet loss, corrupting the operation of the entire chip. By combining a reliable fault detection circuit leveraging circuit-level double-sampling, with a cost-effective rerouting mechanism, we develop a full fault-tolerance solution that can efficiently detect and correct such fatal errors before the affected packets leave the router. To validate the proposed solution, we also introduce a novel method for simulation-based fault-injection based on the NoC's gate-level netlist. Experimental results obtained from a partially and vertically connected 3D-NoC indicate that our solution can provide a high level of reliability in the presence of errors, at the expense of an area and power overhead of 4.1% and 6.8% respectively. Download Paper (PDF; Only available from the DATE venue WiFi)
15:00	11.3.3	SPA: SIMPLE POOL ARCHITECTURE FOR APPLICATION RESOURCE ALLOCATION IN MANY-CORE SYSTEMS Speaker: Iraklis Anagnostopoulos, Southern Illinois University Carbondale, US Authors: Jayasimha Sai Koduri and Iraklis Anagnostopoulos, Southern Illinois University Carbondale, US Abstract The technology push by Moore's law brings a paradigm shift in the adaption of many core systems which replace high frequency superscalar processors with many simpler ones. On the software side, in order to utilize the available computational power, applications are following the high performance parallel/multi-threading model. Thus, many-core systems raise the challenges of resource allocation and fragmentation making necessary efficient run-time resource management techniques. In this paper, we propose SPA, a Simple Pool Architecture for managing resource allocation in many-core systems. The proposed framework follows a distributed approach in which cores are organized into clusters and multiple clusters form a pool. Clusters are created based on system's characteristics and the allocation of cores is performed in a distributed manner so as to take advantage of spatial features, shared resources and reduce scattering of cores. Experimental results show that SPA produces on average 15% better application response time while waiting time is reduced by 45% on average compared to other state-of-art methodologies. Download Paper (PDF; Only available from the DATE venue WiFi)
15:15	11.3.4	RSON: AN INTER/INTRA-CHIP SILICON PHOTONIC NETWORK FOR RACK-SCALE COMPUTING SYSTEMS Speaker: Peng Yang, Hong Kong University of Science and Technology, CN Authors: Peng Yang¹, Zhengbin Pang², Zhifei Wang¹, Zhehui Wang¹, Min Xie², Xuanqi Chen¹, Luan H.K. Duong¹ and Jiang Xu¹ ¹Hong Kong University of Science and Technology, HK; ²National University of Defense Technology, CN Abstract The increasing demand for more computational power from scientific computing, big data processing, and machine learning is pushing the development of HPC (high-performance computing) systems. As the basic HPC building blocks, modularized server racks with a large number of multicore nodes are facing performance and energy efficiency challenges. This paper proposes RSON, an optical network for rack-scale computing systems. RSON connects processor cores, caches, local memories, and remote memories through a novel inter/intra-chip silicon photonic network architecture. We develop a low-latency scalable channel partition and low-power dynamic path priority control scheme for RSON. Experimental results show that RSON can help rack-scale computing systems achieve up to 6.8X higher performance under the same energy consumption than state-of-the-art systems under the latest APEX (application performance at extreme scale) benchmarks. Download Paper (PDF; Only available from the DATE venue WiFi)
15:30	IP5-4, 228	UNDERSTANDING TURN MODELS FOR ADAPTIVE ROUTING: THE MODULAR APPROACH Speaker: Edoardo Fusella, Department of Electrical Engineering and Information Technologies, University of Naples Federico II, IT Authors: Edoardo Fusella and Alessandro Cilardo, University of Naples Federico II, IT Abstract Routing algorithms were extensively studied first in multi-computer systems, then in multi- and many-core architectures. Among the commonly used routing techniques, the turn model seems the most promising solution when targeting adaptiveness. Based on the turn model, several alternative approaches with different turn prohibition schemes were proposed. This paper gives a new theoretical background for designing deadlock-free partially adaptive logic-based distributed routing algorithms that are based on the turn model. Two properties are presented, including a necessary and sufficient condition to prove that a routing algorithm is deadlock-free as long as turn restrictions follow a modular distribution. Existing approaches can be considered a subset of the solution space identified by this work. Finally, we propose a novel routing algorithm exhibiting encouraging performance improvements over state-ofthe-art approaches. Download Paper (PDF; Only available from the DATE venue WiFi)
15:31	IP5-5, 29	QUATER-IMAGINARY BASE FOR COMPLEX NUMBER ARITHMETIC CIRCUITS Speaker: Souradip Sarkar, Nokia Bell Labs, BE Authors: Souradip Sarkar and Manil Dev Gomony, Nokia Bell Labs, BE Abstract Arithmetic operations involving complex numbers are widely used in the signal processing functions in the physical layer of modern wireless and wireline communication systems, electronic instrumentation and control systems. With the ever increasing throughput requirements of such systems, the power consumption of the hardware realization is increasing beyond the allowed budget. Arithmetic circuits based on binary numeral system that have been optimized rigorously over the past few decades are currently being used for the computation involving complex numbers. In this paper, we present the potential of arithmetic circuits for complex number computations based on the Quater-imaginary (QI) base numeral system to reduce power consumption. We show that for a simple multiplier implementation in the QI base, the savings in power and area consumption could be up to 40% when synthesized in 28nm TSMC standard cell technology node. Download Paper (PDF; Only available from the DATE venue WiFi)
15:30		End of session Coffee Break in Exhibition Area Coffee Breaks in the Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD). Lunch Breaks (Großer Saal + Saal 1) On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 20, 2018 Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:50 - 14:20 Coffee Break 16:00 - 17:00 Wednesday, March 21, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30 Awards Presentation and Keynote Lecture in "Saal 2" 13:30 - 14:20 Coffee Break 16:00 - 17:00 Thursday, March 22, 2018 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00 Keynote Lecture in "Saal 2" 13:20 - 13:50 Coffee Break 15:30 - 16:00

Time

Label

Presentation Title
Authors

14:00

11.3.1

HIGH PERFORMANCE COLLECTIVE COMMUNICATION-AWARE 3D NETWORK-ON-CHIP ARCHITECTURES
Speaker:
Biresh Joardar, Washington State University, US
Authors:
Biresh Joardar, Karthi Duraisamy and Partha Pande, Washington State University, US
Abstract
3D Network-on-Chip (NoC) architectures are capable of achieving better performance and lower energy consumption compared to their planar counterparts. However, conventional 3D NoCs are not efficient in handling collective communication. Existing works mainly explore Path and Tree multicast distribution schemes for 3D NoCs. However, both these mechanisms involve high network latency and lack scalability. In this work, we propose a SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) 3D NoC architecture that is capable of achieving high-performance collective communication. The proposed High-Performance SMART (HP-SMART) 3D NoC achieves 65% and 31% latency improvements compared to the existing Path and Tree multicast-based 3D NoCs respectively. HP-SMART 3D NoC also achieves significant improvement in message latency compared to its 2D counterpart.
Download Paper (PDF; Only available from the DATE venue WiFi)

14:30

11.3.2

A SOFT-ERROR RESILIENT ROUTE COMPUTATION UNIT FOR 3D NETWORKS-ON-CHIPS
Speaker:
Alexandre Coelho, TIMA Laboratory, FR
Authors:
Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Juan Fraire and Raoul Velazco, Université Grenoble Alpes, CNRS, Grenoble INP, FR
Abstract
Three-dimensional Networks-on-Chips (3D-NoCs) have emerged as an alternative to further enhance the performance, functionality, and packaging density of 2D-NoCs. However, the increasing complexity of NoC routers, the continuous miniaturization of silicon technology, the lower operating voltages, and the higher operating frequencies have made the NoC increasingly vulnerable to soft errors. In particular, transient faults occurring in the route computation unit (RCU) can provoke misrouting which may lead to severe effects such as deadlocks or packet loss, corrupting the operation of the entire chip. By combining a reliable fault detection circuit leveraging circuit-level double-sampling, with a cost-effective rerouting mechanism, we develop a full fault-tolerance solution that can efficiently detect and correct such fatal errors before the affected packets leave the router. To validate the proposed solution, we also introduce a novel method for simulation-based fault-injection based on the NoC's gate-level netlist. Experimental results obtained from a partially and vertically connected 3D-NoC indicate that our solution can provide a high level of reliability in the presence of errors, at the expense of an area and power overhead of 4.1% and 6.8% respectively.
Download Paper (PDF; Only available from the DATE venue WiFi)

15:00

11.3.3

SPA: SIMPLE POOL ARCHITECTURE FOR APPLICATION RESOURCE ALLOCATION IN MANY-CORE SYSTEMS
Speaker:
Iraklis Anagnostopoulos, Southern Illinois University Carbondale, US
Authors:
Jayasimha Sai Koduri and Iraklis Anagnostopoulos, Southern Illinois University Carbondale, US
Abstract
The technology push by Moore's law brings a paradigm shift in the adaption of many core systems which replace high frequency superscalar processors with many simpler ones. On the software side, in order to utilize the available computational power, applications are following the high performance parallel/multi-threading model. Thus, many-core systems raise the challenges of resource allocation and fragmentation making necessary efficient run-time resource management techniques. In this paper, we propose SPA, a Simple Pool Architecture for managing resource allocation in many-core systems. The proposed framework follows a distributed approach in which cores are organized into clusters and multiple clusters form a pool. Clusters are created based on system's characteristics and the allocation of cores is performed in a distributed manner so as to take advantage of spatial features, shared resources and reduce scattering of cores. Experimental results show that SPA produces on average 15% better application response time while waiting time is reduced by 45% on average compared to other state-of-art methodologies.
Download Paper (PDF; Only available from the DATE venue WiFi)

15:15

11.3.4

RSON: AN INTER/INTRA-CHIP SILICON PHOTONIC NETWORK FOR RACK-SCALE COMPUTING SYSTEMS
Speaker:
Peng Yang, Hong Kong University of Science and Technology, CN
Authors:
Peng Yang¹, Zhengbin Pang², Zhifei Wang¹, Zhehui Wang¹, Min Xie², Xuanqi Chen¹, Luan H.K. Duong¹ and Jiang Xu¹
¹Hong Kong University of Science and Technology, HK; ²National University of Defense Technology, CN
Abstract
The increasing demand for more computational power from scientific computing, big data processing, and machine learning is pushing the development of HPC (high-performance computing) systems. As the basic HPC building blocks, modularized server racks with a large number of multicore nodes are facing performance and energy efficiency challenges. This paper proposes RSON, an optical network for rack-scale computing systems. RSON connects processor cores, caches, local memories, and remote memories through a novel inter/intra-chip silicon photonic network architecture. We develop a low-latency scalable channel partition and low-power dynamic path priority control scheme for RSON. Experimental results show that RSON can help rack-scale computing systems achieve up to 6.8X higher performance under the same energy consumption than state-of-the-art systems under the latest APEX (application performance at extreme scale) benchmarks.
Download Paper (PDF; Only available from the DATE venue WiFi)

15:30

IP5-4, 228

UNDERSTANDING TURN MODELS FOR ADAPTIVE ROUTING: THE MODULAR APPROACH
Speaker:
Edoardo Fusella, Department of Electrical Engineering and Information Technologies, University of Naples Federico II, IT
Authors:
Edoardo Fusella and Alessandro Cilardo, University of Naples Federico II, IT
Abstract
Routing algorithms were extensively studied first in multi-computer systems, then in multi- and many-core architectures. Among the commonly used routing techniques, the turn model seems the most promising solution when targeting adaptiveness. Based on the turn model, several alternative approaches with different turn prohibition schemes were proposed. This paper gives a new theoretical background for designing deadlock-free partially adaptive logic-based distributed routing algorithms that are based on the turn model. Two properties are presented, including a necessary and sufficient condition to prove that a routing algorithm is deadlock-free as long as turn restrictions follow a modular distribution. Existing approaches can be considered a subset of the solution space identified by this work. Finally, we propose a novel routing algorithm exhibiting encouraging performance improvements over state-ofthe-art approaches.
Download Paper (PDF; Only available from the DATE venue WiFi)

15:31

IP5-5, 29

QUATER-IMAGINARY BASE FOR COMPLEX NUMBER ARITHMETIC CIRCUITS
Speaker:
Souradip Sarkar, Nokia Bell Labs, BE
Authors:
Souradip Sarkar and Manil Dev Gomony, Nokia Bell Labs, BE
Abstract
Arithmetic operations involving complex numbers are widely used in the signal processing functions in the physical layer of modern wireless and wireline communication systems, electronic instrumentation and control systems. With the ever increasing throughput requirements of such systems, the power consumption of the hardware realization is increasing beyond the allowed budget. Arithmetic circuits based on binary numeral system that have been optimized rigorously over the past few decades are currently being used for the computation involving complex numbers. In this paper, we present the potential of arithmetic circuits for complex number computations based on the Quater-imaginary (QI) base numeral system to reduce power consumption. We show that for a simple multiplier implementation in the QI base, the savings in power and area consumption could be up to 40% when synthesized in 28nm TSMC standard cell technology node.
Download Paper (PDF; Only available from the DATE venue WiFi)

15:30

End of session
Coffee Break in Exhibition Area

Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area (Terrace Level of the ICCD).

Lunch Breaks (Großer Saal + Saal 1)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the rooms "Großer Saal" and "Saal 1" (Saal Level of the ICCD) to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 20, 2018