2.7 EU Project Special Session: from Secure Clouds to reliable and variable HPC

Time	Label	Presentation Title Authors
11:30	2.7.1	HARPA: TACKLING PHYSICALLY INDUCED PERFORMANCE VARIABILITY Speaker: Dimitrios Soudris, ICCS, GR Authors: Nikolaos Zompakis¹ and Dimitrios Soudris² ¹ICCS/NTUA, GR; ²NTUA, GR Abstract Continuously increasing application demands on both High Performance Computing (HPC) and Embedded Systems (ES) are driving the IC manufacturing industry on an ever-lasting scaling of devices in silicon. Nevertheless, integration and miniaturization of transistors comes with an important and non-negligible trade-off: time-zero and time-dependent performance variability. Increasing guard-bands to battle variability is not scalable, since worst-case design margins are prohibitive for downscaled technology nodes. This paper discusses the FP7-612069-HARPA project of the European Commission which aims to enable next-generation embedded and high-performance heterogeneous many-cores to cost-effectively confront variations by providing Dependable-Performance: correct functionality and timing guarantees throughout the expected lifetime of a platform under thermal, power, and energy constraints. The HARPA novelty is in seeking synergies in techniques that have been considered virtually exclusively in the ES or HPC domains (worst-case guaranteed partly proactive techniques in embedded, and dynamic best-effort reactive techniques in high-performance). Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	2.7.2	DYNAMIC SOFTWARE RANDOMISATION: LESSONS LEARNED FROM AN AEROSPACE CASE STUDY Speaker: Leonidas Kosmidis, Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES Authors: Leonidas Kosmidis¹, Jaume Abella² and Francisco Cazorla³ ¹Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; ²Barcelona Supercomputing Center (BSC-CNS), ES; ³Barcelona Supercomputing Center and IIIA-CSIC, ES Abstract Timing Validation and Verification (V&V) is an important step in real-time system design, in which a system's timing behaviour is assessed via Worst Case Execution Time (WCET) estimation and scheduling analysis. For WCET estimation, measurement-based timing analysis (MBTA) techniques are widely-used and well-established in industrial environments. However, the advent of complex processors makes it more difficult for the user to provide evidence that the software is tested under stress conditions representative of those at system operation. Measurement-Based Probabilistic Timing Analysis (MBPTA) is a variant of MBTA followed by the PROXIMA European Project that facilitates formulating this representativeness argument. MBPTA requires certain properties to be applicable, which can be obtained by selectively injecting randomisation in platform's timing behaviour via hardware or software means. In this paper, we assess the effectiveness of the PROXIMA's dynamic software randomisation (DSR) with a space industrial case study executed on a real unmodified hardware platform and an industrial operating system. We present the challenges faced in its development, in order to achieve MBPTA compliance and the lessons learned from this process. Our results, obtained using a commercial timing analysis tool, indicate that DSR does not impact the average performance of the application, while it enables the use of MBPTA. This results in tighter pWCET estimates compared to current industrial practice. Download Paper (PDF; Only available from the DATE venue WiFi)
12:15	2.7.3	READEX: LINKING TWO ENDS OF THE COMPUTING CONTINUUM TO IMPROVE ENERGY-EFFICIENCY IN DYNAMIC APPLICATIONS Speaker: Per Gunnar Kjeldsberg, Norwegian University of Science and Technology, NO Authors: Per Gunnar Kjeldsberg¹, Andreas Gocht², Michael Gerndt³, Riha Lubomir⁴, Joseph Schuchart⁵ and Umbreen Sabir Mian² ¹Norwegian University of Science and Technology, NO; ²Technische Universität Dresden, DE; ³Technische Universität München, DE; ⁴IT4Innovations, Ostrava, CZ; ⁵Universität Stuttgart, DE Abstract In both the embedded systems and High Performance Computing domains, energy-efficiency has become one of the main design criteria. Efficiently utilizing the resources provided in computing systems ranging from embedded systems to current petascale and future Exascale HPC systems will be a challenging task. Suboptimal designs can potentially cause large amounts of underutilized resources and wasted energy. In both domains, a promising potential for improving efficiency of scalable applications stems from the significant degree of dynamic behaviour, e.g., runtime alternation in application resource requirements and workloads. Manually detecting and leveraging this dynamism to improve performance and energy-efficiency is a tedious task that is commonly neglected by developers. However, using an automatic optimization approach, application dynamism can be analysed at design time and used to optimize system configurations at runtime. The European Union Horizon 2020 READEX (Runtime Exploitation of Application Dynamism for Energy-efficient eXascale computing) project will develop a tools-aided auto-tuning methodology inspired by the system scenario methodology used in embedded systems. Dynamic behaviour of HPC applications will be exploited to achieve improved energy-efficiency and performance. Driven by a consortium of European experts from academia, HPC resource providers, and industry, the READEX project aims at developing the first of its kind generic framework to split design time and runtime automatic tuning while targeting heterogeneous system at the Exascale level. This paper describes plans for the project as well as early results achieved during its first year. Furthermore, it is shown how project results will be brought back into the embedded systems domain. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30	2.7.4	BASTION: BOARD AND SOC TEST INSTRUMENTATION FOR AGEING AND NO FAILURE FOUND Speaker: Matteo Sonza, Reorda, IT Authors: Erik Larsson¹, Matteo Sonza Reorda², Maksim Jenihhin³, Jaan Raik⁴, Hans Kerkhoff⁵, Rene Krenz-Baath⁶ and Piet Engelke⁷ ¹Lund University, SE; ²Politecnico di Torino - DAUIN, IT; ³Tallinn University of Technology, EE; ⁴Tallinn university of Technology, EE; ⁵University of Twente / CTIT-TDT, NL; ⁶Hochschule Hamm-Lippstadt University of applied Sciences, DE; ⁷Infineon Technologies, DE Abstract This is an overview paper that motivates and describes performed work done in the European Commission funded research project BASTION, which focuses on two critical problems of modern electronics: the No-Fault-Found (NFF) and CMOS ageing. New defect classes contributing to NFF have been identified, including timing related faults (TRF) at board level and intermittent resistive faults (IRF) at IC level. BASTION has addressed the mechanisms of ageing and developed several techniques to improve the longevity of electronic products. Embedded Instrumentation, monitors, and IEEE 1687 standard for reconfigurable scan networks (RSN) are seen as an important leverage that helped mitigating the impact of the above listed problems by facilitating a low-latency, scalable online system health monitoring and error localization infrastructure as well as integration of all heterogeneous technologies into a homogeneous demonstration platform. This paper helps the reader to get a general overview of the work performed and provides a collection of references to publications where the respective research results are described in detail. Download Paper (PDF; Only available from the DATE venue WiFi)
12:45	2.7.5	RETHINK BIG: EUROPEAN ROADMAP FOR HARDWARE AND NETWORKING OPTIMIZATIONS FOR BIG DATA Speaker: Osman Unsal, Barcelona Supercomputing Center, ES Authors: Gina Alioto¹ and Paul Carpenter² ¹Barcelona Supercomputing Center, ES; ²BSC, ES Abstract This paper discusses the results of the RETHINK big Project, a 2-year Collaborative Support Action funded by the European Commission in order to write the European Roadmap for Hardware and Networking optimizations for Big Data. This industry-driven project was led by the Barcelona Supercomputing Center (BSC), and it included large industry partners, SMEs and academia. The roadmap identifies business opportunities from 89 in-depth interviews with 70 European industry stakeholders in the area of Big Data and predicts the future technologies that will disrupt the state of the art in Big Data processing in terms of hardware and networking optimizations. Moreover, it presents coordinated technology development recommendations (focused on optimizations in networking and hardware) that would be in the best interest of European Big Data companies to undertake in concert as a matter of competitive advantage. Download Paper (PDF; Only available from the DATE venue WiFi)
13:00	IP1-8, 2001	COMPUTING WITH NANO-CROSSBAR ARRAYS: LOGIC SYNTHESIS AND FAULT TOLERANCE Speaker: Mustafa Altun, Istanbul Technical University, TR Authors: Mustafa Altun¹, Valentina Ciriani² and Mehdi Tahoori³ ¹Istanbul Technical University, TR; ²University of Milan, IT; ³Karlsruhe Institute of Technology, DE Abstract Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and can be fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, our project aims to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. First two work packages of the project are presented in this paper. These packages are on logic synthesis that aims to implement Boolean functions with nano-crossbar arrays with area optimization, and fault tolerance that aims to provide a full methodology in the presence of high fault densities and extreme parametric variations in nano-crossbar architectures. Download Paper (PDF; Only available from the DATE venue WiFi)
13:01	IP1-9, 2005	SECURECLOUD: SECURE BIG DATA PROCESSING IN UNTRUSTED CLOUDS Speaker: Rafael Pires, University of Neuchâtel, CH Abstract We present the SecureCloud EU Horizon 2020 project, whose goal is to enable new big data applications that use sensitive data in the cloud without compromising data security and privacy. For this, SecureCloud designs and develops a layered architecture that allows for (i) the secure creation and deployment of secure micro-services; (ii) the secure integration of individual micro-services to full-fledged big data applications; and (iii) the secure execution of these applications within untrusted cloud environments. To provide security guarantees, SecureCloud leverages novel security mechanisms present in recent commodity CPUs, in particular, Intel's Software Guard Extensions (SGX). SecureCloud applies this architecture to big data applications in the context of smart grids. We describe the SecureCloud approach, initial results, and considered use cases. Download Paper (PDF; Only available from the DATE venue WiFi)
13:02	IP1-10, 2010	WCET-AWARE PARALLELIZATION OF MODEL-BASED APPLICATIONS FOR MULTI-CORES: THE ARGO APPROACH Speaker: Steven Derrien, Universite de Rennes 1, FR Authors: Steven Derrien¹, Isabelle Puaut², Panayiotis Alefragis³, Marcus Bednara⁴, Harald Bucher⁵, Clément David⁶, Yann Debray⁶, Umut Durak⁷, Imen Fassi², Christian Ferdinand⁸, Damien Hardy², Angeliki Kritikakou², Gerard Rauwerda⁹, Simon Reder⁵, Martin Sicks⁸, Timo Stripf⁵, Kim Sunesen⁹, Timon ter Braak⁹, Nikolaos Voros³ and Jürgen Becker⁵ ¹IRISA, FR; ²University of Rennes 1 / IRISA, FR; ³TWG, GR; ⁴IIS/Franhofer, DE; ⁵Karlsruhe Institute of Technology, DE; ⁶Scilab, FR; ⁷DLR, DE; ⁸Absint, FR; ⁹Recore systems, FR Abstract Parallel architectures are nowadays not only confined to the domain of high performance computing, they are also increasingly used in embedded time-critical systems. The ARGO H2020 project provides a programming paradigm and associated tool flow to exploit the full potential of architectures in terms of development productivity, time-to-market, exploitation of the platform computing power and guaranteed real-time performance. In this paper we give an overview of the objectives of ARGO and explore the challenges introduced by our approach. Download Paper (PDF; Only available from the DATE venue WiFi)
13:03	IP1-11, 2011	EXPLORING THE UNKNOWN THROUGH SUCCESSIVE GENERATIONS OF LOW POWER AND LOW RESOURCE VERSATILE AGENTS Speaker: Martin Andraud, Eindhoven University of Technology, NL Authors: Martin Andraud¹ and Marian Verhelst² ¹Eindhoven University of Technology, NL; ²Katholieke Universiteit Leuven, BE Abstract The Phoenix project aims to develop a new approach to explore unknown environments, based on multiple measurement campaigns carried out by extremely tiny devices, called agents, that gather data from multiple sensors. These low power and low resource agents are configured specifically for each measurement campaign to achieve the exploration goal in the smallest number of iterations. Thus, the main design challenge is to build agents as much reconfigurable as possible. This paper introduces the Phoenix project in more details and presents first developments in the agent design. Download Paper (PDF; Only available from the DATE venue WiFi)
13:00		End of session Lunch Break in Garden Foyer Keynote Lecture session 3.0 in "Garden Foyer" 1350 - 1420 Lunch Break in the Garden Foyer On all conference days (Tuesday to Thursday), a buffet lunch will be offered in the Garden Foyer, in front of the session rooms. Kindly note that this is restricted to conference delegates possessing a lunch voucher only. When entering the lunch break area, delegates will be asked to present the corresponding lunch voucher of the day. Once the lunch area is being left, re-entrance is not allowed for the respective lunch.

Time

Label

Presentation Title
Authors

11:30

2.7.1

HARPA: TACKLING PHYSICALLY INDUCED PERFORMANCE VARIABILITY
Speaker:
Dimitrios Soudris, ICCS, GR
Authors:
Nikolaos Zompakis¹ and Dimitrios Soudris²
¹ICCS/NTUA, GR; ²NTUA, GR
Abstract
Continuously increasing application demands on both High Performance Computing (HPC) and Embedded Systems (ES) are driving the IC manufacturing industry on an ever-lasting scaling of devices in silicon. Nevertheless, integration and miniaturization of transistors comes with an important and non-negligible trade-off: time-zero and time-dependent performance variability. Increasing guard-bands to battle variability is not scalable, since worst-case design margins are prohibitive for downscaled technology nodes. This paper discusses the FP7-612069-HARPA project of the European Commission which aims to enable next-generation embedded and high-performance heterogeneous many-cores to cost-effectively confront variations by providing Dependable-Performance: correct functionality and timing guarantees throughout the expected lifetime of a platform under thermal, power, and energy constraints. The HARPA novelty is in seeking synergies in techniques that have been considered virtually exclusively in the ES or HPC domains (worst-case guaranteed partly proactive techniques in embedded, and dynamic best-effort reactive techniques in high-performance).
Download Paper (PDF; Only available from the DATE venue WiFi)

12:00

2.7.2

DYNAMIC SOFTWARE RANDOMISATION: LESSONS LEARNED FROM AN AEROSPACE CASE STUDY
Speaker:
Leonidas Kosmidis, Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES
Authors:
Leonidas Kosmidis¹, Jaume Abella² and Francisco Cazorla³
¹Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; ²Barcelona Supercomputing Center (BSC-CNS), ES; ³Barcelona Supercomputing Center and IIIA-CSIC, ES
Abstract
Timing Validation and Verification (V&V) is an important step in real-time system design, in which a system's timing behaviour is assessed via Worst Case Execution Time (WCET) estimation and scheduling analysis. For WCET estimation, measurement-based timing analysis (MBTA) techniques are widely-used and well-established in industrial environments. However, the advent of complex processors makes it more difficult for the user to provide evidence that the software is tested under stress conditions representative of those at system operation. Measurement-Based Probabilistic Timing Analysis (MBPTA) is a variant of MBTA followed by the PROXIMA European Project that facilitates formulating this representativeness argument. MBPTA requires certain properties to be applicable, which can be obtained by selectively injecting randomisation in platform's timing behaviour via hardware or software means. In this paper, we assess the effectiveness of the PROXIMA's dynamic software randomisation (DSR) with a space industrial case study executed on a real unmodified hardware platform and an industrial operating system. We present the challenges faced in its development, in order to achieve MBPTA compliance and the lessons learned from this process. Our results, obtained using a commercial timing analysis tool, indicate that DSR does not impact the average performance of the application, while it enables the use of MBPTA. This results in tighter pWCET estimates compared to current industrial practice.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:15

2.7.3

READEX: LINKING TWO ENDS OF THE COMPUTING CONTINUUM TO IMPROVE ENERGY-EFFICIENCY IN DYNAMIC APPLICATIONS
Speaker:
Per Gunnar Kjeldsberg, Norwegian University of Science and Technology, NO
Authors:
Per Gunnar Kjeldsberg¹, Andreas Gocht², Michael Gerndt³, Riha Lubomir⁴, Joseph Schuchart⁵ and Umbreen Sabir Mian²
¹Norwegian University of Science and Technology, NO; ²Technische Universität Dresden, DE; ³Technische Universität München, DE; ⁴IT4Innovations, Ostrava, CZ; ⁵Universität Stuttgart, DE
Abstract
In both the embedded systems and High Performance Computing domains, energy-efficiency has become one of the main design criteria. Efficiently utilizing the resources provided in computing systems ranging from embedded systems to current petascale and future Exascale HPC systems will be a challenging task. Suboptimal designs can potentially cause large amounts of underutilized resources and wasted energy. In both domains, a promising potential for improving efficiency of scalable applications stems from the significant degree of dynamic behaviour, e.g., runtime alternation in application resource requirements and workloads. Manually detecting and leveraging this dynamism to improve performance and energy-efficiency is a tedious task that is commonly neglected by developers. However, using an automatic optimization approach, application dynamism can be analysed at design time and used to optimize system configurations at runtime. The European Union Horizon 2020 READEX (Runtime Exploitation of Application Dynamism for Energy-efficient eXascale computing) project will develop a tools-aided auto-tuning methodology inspired by the system scenario methodology used in embedded systems. Dynamic behaviour of HPC applications will be exploited to achieve improved energy-efficiency and performance. Driven by a consortium of European experts from academia, HPC resource providers, and industry, the READEX project aims at developing the first of its kind generic framework to split design time and runtime automatic tuning while targeting heterogeneous system at the Exascale level. This paper describes plans for the project as well as early results achieved during its first year. Furthermore, it is shown how project results will be brought back into the embedded systems domain.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:30

2.7.4

BASTION: BOARD AND SOC TEST INSTRUMENTATION FOR AGEING AND NO FAILURE FOUND
Speaker:
Matteo Sonza, Reorda, IT
Authors:
Erik Larsson¹, Matteo Sonza Reorda², Maksim Jenihhin³, Jaan Raik⁴, Hans Kerkhoff⁵, Rene Krenz-Baath⁶ and Piet Engelke⁷
¹Lund University, SE; ²Politecnico di Torino - DAUIN, IT; ³Tallinn University of Technology, EE; ⁴Tallinn university of Technology, EE; ⁵University of Twente / CTIT-TDT, NL; ⁶Hochschule Hamm-Lippstadt University of applied Sciences, DE; ⁷Infineon Technologies, DE
Abstract
This is an overview paper that motivates and describes performed work done in the European Commission funded research project BASTION, which focuses on two critical problems of modern electronics: the No-Fault-Found (NFF) and CMOS ageing. New defect classes contributing to NFF have been identified, including timing related faults (TRF) at board level and intermittent resistive faults (IRF) at IC level. BASTION has addressed the mechanisms of ageing and developed several techniques to improve the longevity of electronic products. Embedded Instrumentation, monitors, and IEEE 1687 standard for reconfigurable scan networks (RSN) are seen as an important leverage that helped mitigating the impact of the above listed problems by facilitating a low-latency, scalable online system health monitoring and error localization infrastructure as well as integration of all heterogeneous technologies into a homogeneous demonstration platform. This paper helps the reader to get a general overview of the work performed and provides a collection of references to publications where the respective research results are described in detail.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:45

2.7.5

RETHINK BIG: EUROPEAN ROADMAP FOR HARDWARE AND NETWORKING OPTIMIZATIONS FOR BIG DATA
Speaker:
Osman Unsal, Barcelona Supercomputing Center, ES
Authors:
Gina Alioto¹ and Paul Carpenter²
¹Barcelona Supercomputing Center, ES; ²BSC, ES
Abstract
This paper discusses the results of the RETHINK big Project, a 2-year Collaborative Support Action funded by the European Commission in order to write the European Roadmap for Hardware and Networking optimizations for Big Data. This industry-driven project was led by the Barcelona Supercomputing Center (BSC), and it included large industry partners, SMEs and academia. The roadmap identifies business opportunities from 89 in-depth interviews with 70 European industry stakeholders in the area of Big Data and predicts the future technologies that will disrupt the state of the art in Big Data processing in terms of hardware and networking optimizations. Moreover, it presents coordinated technology development recommendations (focused on optimizations in networking and hardware) that would be in the best interest of European Big Data companies to undertake in concert as a matter of competitive advantage.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:00

IP1-8, 2001

COMPUTING WITH NANO-CROSSBAR ARRAYS: LOGIC SYNTHESIS AND FAULT TOLERANCE
Speaker:
Mustafa Altun, Istanbul Technical University, TR
Authors:
Mustafa Altun¹, Valentina Ciriani² and Mehdi Tahoori³
¹Istanbul Technical University, TR; ²University of Milan, IT; ³Karlsruhe Institute of Technology, DE
Abstract
Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and can be fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, our project aims to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. First two work packages of the project are presented in this paper. These packages are on logic synthesis that aims to implement Boolean functions with nano-crossbar arrays with area optimization, and fault tolerance that aims to provide a full methodology in the presence of high fault densities and extreme parametric variations in nano-crossbar architectures.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:01

IP1-9, 2005

SECURECLOUD: SECURE BIG DATA PROCESSING IN UNTRUSTED CLOUDS
Speaker:
Rafael Pires, University of Neuchâtel, CH
Abstract
We present the SecureCloud EU Horizon 2020 project, whose goal is to enable new big data applications that use sensitive data in the cloud without compromising data security and privacy. For this, SecureCloud designs and develops a layered architecture that allows for (i) the secure creation and deployment of secure micro-services; (ii) the secure integration of individual micro-services to full-fledged big data applications; and (iii) the secure execution of these applications within untrusted cloud environments. To provide security guarantees, SecureCloud leverages novel security mechanisms present in recent commodity CPUs, in particular, Intel's Software Guard Extensions (SGX). SecureCloud applies this architecture to big data applications in the context of smart grids. We describe the SecureCloud approach, initial results, and considered use cases.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:02

IP1-10, 2010

WCET-AWARE PARALLELIZATION OF MODEL-BASED APPLICATIONS FOR MULTI-CORES: THE ARGO APPROACH
Speaker:
Steven Derrien, Universite de Rennes 1, FR
Authors:
Steven Derrien¹, Isabelle Puaut², Panayiotis Alefragis³, Marcus Bednara⁴, Harald Bucher⁵, Clément David⁶, Yann Debray⁶, Umut Durak⁷, Imen Fassi², Christian Ferdinand⁸, Damien Hardy², Angeliki Kritikakou², Gerard Rauwerda⁹, Simon Reder⁵, Martin Sicks⁸, Timo Stripf⁵, Kim Sunesen⁹, Timon ter Braak⁹, Nikolaos Voros³ and Jürgen Becker⁵
¹IRISA, FR; ²University of Rennes 1 / IRISA, FR; ³TWG, GR; ⁴IIS/Franhofer, DE; ⁵Karlsruhe Institute of Technology, DE; ⁶Scilab, FR; ⁷DLR, DE; ⁸Absint, FR; ⁹Recore systems, FR
Abstract
Parallel architectures are nowadays not only confined to the domain of high performance computing, they are also increasingly used in embedded time-critical systems. The ARGO H2020 project provides a programming paradigm and associated tool flow to exploit the full potential of architectures in terms of development productivity, time-to-market, exploitation of the platform computing power and guaranteed real-time performance. In this paper we give an overview of the objectives of ARGO and explore the challenges introduced by our approach.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:03

IP1-11, 2011

EXPLORING THE UNKNOWN THROUGH SUCCESSIVE GENERATIONS OF LOW POWER AND LOW RESOURCE VERSATILE AGENTS
Speaker:
Martin Andraud, Eindhoven University of Technology, NL
Authors:
Martin Andraud¹ and Marian Verhelst²
¹Eindhoven University of Technology, NL; ²Katholieke Universiteit Leuven, BE
Abstract
The Phoenix project aims to develop a new approach to explore unknown environments, based on multiple measurement campaigns carried out by extremely tiny devices, called agents, that gather data from multiple sensors. These low power and low resource agents are configured specifically for each measurement campaign to achieve the exploration goal in the smallest number of iterations. Thus, the main design challenge is to build agents as much reconfigurable as possible. This paper introduces the Phoenix project in more details and presents first developments in the agent design.
Download Paper (PDF; Only available from the DATE venue WiFi)

13:00

End of session
Lunch Break in Garden Foyer

Keynote Lecture session 3.0 in "Garden Foyer" 1350 - 1420

Lunch Break in the Garden Foyer
On all conference days (Tuesday to Thursday), a buffet lunch will be offered in the Garden Foyer, in front of the session rooms. Kindly note that this is restricted to conference delegates possessing a lunch voucher only. When entering the lunch break area, delegates will be asked to present the corresponding lunch voucher of the day. Once the lunch area is being left, re-entrance is not allowed for the respective lunch.