Date: Thursday 30 March 2017
Time: 08:30 - 10:00
Location / Room: 3C
Chair:
William Fornaciari, Politecnico di Milano, IT
Co-Chair:
Shusuke Yoshimoto, Osaka University, JP
Modeling and optimization of Internet-of-things (IoT) devices from energy sources to computing components including battery, energy harvesting system, power converter, and microprocessor
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 9.5.1 | MEASUREMENT AND VALIDATION OF ENERGY HARVESTING IOT DEVICES Speaker: Lukas Sigrist, ETH Zurich, CH Authors: Lukas Sigrist1, Andres Gomez1, Roman Lim1, Stefan Lippuner1, Matthias Leubin1 and Lothar Thiele2 1ETH Zurich, CH; 2Swiss Federal Institute of Technology Zurich, CH Abstract With the appearance of wearable devices and the IoT, energy harvesting nodes are becoming more and more important. The design and evaluation of these small standalone sensors and actuators, which harvest limited amounts of energy, requires novel tools and methods. Fast and accurate measurement systems are required to capture the rapidly changing harvesting scenarios and characterize leakage currents and energy efficiencies. The need for real-world experiments creates a demand for compact and portable equipment to perform in-situ power measurements and environmental logging. This work presents the RocketLogger, a hand-held measurement device that combines both properties: portability and accuracy. The custom analog front-end allows logging at sampling rates up to 64 kSPS. The fast range switching within 1.4 us guarantees continuous power measurements starting from 4 pW at 1 mV up to 2.75 W at 5.5 V. The software provides remote control and manages data acquisition of up to 13 Mb/sec in real-time. We extensively characterize the RocketLogger's performance, demonstrate the need for its properties in three use-cases at different stages of the system design flow, and show its advantages in measuring and validating new harvesting-driven devices for the IoT. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 9.5.2 | A METHODOLOGY FOR THE DESIGN OF DYNAMIC ACCURACY OPERATORS BY RUNTIME BACK BIAS Speaker: Daniele Jahier Pagliari, Politecnico di Torino, IT Authors: Daniele Jahier Pagliari1, Yves Durand2, David Coriat2, Anca Molnos2, Edith Beigne2, Enrico Macii1 and Massimo Poncino1 1Politecnico di Torino, IT; 2CEA-Leti, FR Abstract Mobile and IoT applications must balance increasing processing demands with limited power and cost budgets. Approximate computing achieves this goal leveraging the error tolerance features common in many emerging applications to reduce power consumption. In particular, adequate (i.e., energy/quality-configurable) hardware operators are key components in an error tolerant system. Existing implementations of these operators require significant architectural modifications, hence they are often design-specific and tend to have large overheads compared to accurate units. In this paper, we propose a methodology to design adequate datapath operators in an automatic way, which uses threshold voltage scaling as a knob to dynamically control the power/accuracy tradeoff. The method overcomes the limitations of previous solutions based on supply voltage scaling, in that it introduces lower overheads and it allows fine-grain regulation of this tradeoff. We demonstrate our approach on a state-of-the-art 28nm FDSOI technology, exploiting the strong effect of back biasing on threshold voltage. Results show a power consumption reduction of as much as 39% compared to solutions based only on supply voltage scaling, at iso-accuracy. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 9.5.3 | A SCAN-CHAIN BASED STATE RETENTION METHODOLOGY FOR IOT PROCESSORS OPERATING ON INTERMITTENT ENERGY Speaker: Pascal Alexander Hager, ETH Zürich, CH Authors: Pascal Alexander Hager1, Hamed Fatemi2, Jose Pineda2 and Luca Benini3 1ETH Zurich, CH; 2NXP Semiconductors, NL; 3Università di Bologna, IT Abstract Future IoT systems are tightly constraint by cost and size and will often be operated from an energy harvester's output. Since these batteryless systems operate on intermittent energy they have to be able to retain their state during the power outages in order to guarantee computation progress. Due to the lack of large energy buffers the state needs to be saved quickly using residual energy only. In related work, the state is retained in-place by replacing all flip-flops with state retentive flip-flops (SRFF), which are powered by auxiliary supplies for retention or incorporate non-volatile memory cells. However, these SRFFs increase the power consumption during active operation impairing the overall systems efficiency. In this paper, we present a scan-chain based state retention approach, where the state is moved to memory using only 4.5pJ/b. Since our approach does not introduce any power overhead, this energy cost pays off after an on-time of just 100us compared to state-of-the-art in-place solutions. Moreover, compared to a software mechanism, our approach requires 6.6x less energy to move the state and is 5.8x faster. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:45 | 9.5.4 | A CIRCUIT-EQUIVALENT BATTERY MODEL ACCOUNTING FOR THE DEPENDENCY ON LOAD FREQUENCY Speaker: Yukai Chen, Politecnico di Torino, IT Authors: Yukai Chen, Enrico Macii and Massimo Poncino, Politecnico di Torino, IT Abstract Circuit-equivalent battery models are considered de-facto standard for modeling and simulation of digital systems due to many practical advantages. In spite of the many variants of models proposed in the literature, none of them accounts for one important feature of the battery dynamics, namely, the dependency on the frequency of current load profile. For a given average current value, current loads with different spectral distributions may have quite different impacts on the battery discharge. This is a very well-know issue in the design of hybrid energy storage systems, where different types of storage devices are used, each with different storage efficiency for different load frequency ranges. We propose a basic modification to a state-of-the-art model that incorporates this load frequency dependency, as well as a methodology to identify the frequency-sensitive parameters of the model from publicly available data (e.g., datasheets). Results show that frequency-agnostic models can significantly overestimate the battery state-of-charge, and that this effect is far from being negligible. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | IP4-11, 184 | ADAPTIVE POWER DELIVERY SYSTEM MANAGEMENT FOR MANY-CORE PROCESSORS WITH ON/OFF-CHIP VOLTAGE REGULATORS Speaker: Haoran Li, The Hong Kong University of Science and Technology, HK Authors: Haoran Li, Jiang Xu, Zhe Wang, Peng Yang, Rafael Kioji Vivas Maeda and Zhongyuan Tian, The Hong Kong University of Science and Technology, HK Abstract The power delivery system (PDS) plays a crucial role of guaranteeing the proper functionality of many-core processors. However, as PDS is usually optimized to provide power to the target chip at its best performance level, its energy efficiency can be seriously degraded under highly dynamic workloads, making it a major source of system power losses. On-chip voltage regulators (VR), which are able to achieve fast and fine-grained power control, have been popular choices for PDS implementation and provided design opportunities for improving system energy efficiency. In this paper, we propose the adaptive Quantized Power Management (QPM) scheme to dynamically adjust the PDS with both on-chip and off-chip VRs based on run-time workloads. Experimental results on different applications show that QPM applied on a hybrid PDS with both on/off-chip voltage regulators(VR) achieves 74.1% average overall energy efficiency, 12.3% higher than the conventional PDS with single off-chip VR. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:01 | IP4-12, 322 | FLYING AND DECOUPLING CAPACITANCE OPTIMIZATION FOR AREA-CONSTRAINED ON-CHIP SWITCHED-CAPACITOR VOLTAGE REGULATORS Speaker: Xiaoyang Mi, Arizona State University, US Authors: Xiaoyang Mi1, Hesam Fathi Moghadam2 and Jae-sun Seo1 1Arizona State University, US; 2Oracle Corporation, US Abstract Switched-capacitor voltage regulators (SCVRs) are widely used in on-chip power management, due to high step-down efficiency and feasibility of integration. In this work, we present theoretical analysis and optimization methodology for flying and decoupling capacitance values for area-constrained on-chip SCVRs to achieve the highest system-level power efficiency. The proposed models for efficiency and droop voltage are validated with on-chip 2:1 SCVR implementations in both 65nm and 32nm CMOS, which show high model accuracy. The maximum and average error of the predicted optimal ratio between flying and decoupling capacitance are 5% and 1.7%, respectively. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Tuesday, March 28, 2017
Wednesday, March 29, 2017
Thursday, March 30, 2017
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