Date: Wednesday 29 March 2017
Time: 14:30 - 16:00
Location / Room: 3B
Chair:
Akash Kumar, Technische Universitaet Dresden, DE
Co-Chair:
Orlando Moreira, Intel, NL
Embedded architectures have to often provide application performance guarantees despite stringent resource constraints. The talks in this session provide solutions to managing the limited resources of such platforms and analysing the impact of resource allocation - both from the power and performance perspective.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:30 | 7.7.1 | (Best Paper Award Candidate) SCALABLE PROBABILISTIC POWER BUDGETING FOR MANY-CORES Speaker: Anuj Pathania, Karlsruhe Institute of Technology, IN Authors: Anuj Pathania1, Heba Khdr2, Muhammad Shafique3, Tulika Mitra4 and Joerg Henkel1 1Karlsruhe Institute of Technology, DE; 2Karlsruhe Institute of Technology (KIT), DE; 3Vienna University of Technology (TU Wien), AT; 4National University of Singapore, SG Abstract Many-core processors exhibit hundreds to thousands of cores, which can execute lots of multi-threaded tasks in parallel. Restrictive power dissipation capacity of a many-core prevents all its executing tasks from operating at their peak performance together. Furthermore, the ability of a task to exploit part of the power budget allocated to it depends upon its current execution phase. This mandates careful rationing of the power budget amongst the tasks for full exploitation of the many-core. Past research proposed power budgeting techniques that redistribute power budget amongst tasks based on up-to-date information about their current phases. This phase information needs to be constantly propagated throughout the system and processed, inhibiting scalability. In this work, we propose a novel probabilistic technique for power budgeting which requires no exchange of phase information yet provides guarantees on judicial use of the power budget. The proposed probabilistic technique reduces the power budgeting overheads by 97.13% in comparison to a non-probabilistic approach, while providing almost equal performance on a simulated thousand-core system. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 7.7.2 | EXPLOITING SPORADIC SERVERS TO PROVIDE BUDGET SCHEDULING FOR ARINC653 BASED REAL-TIME VIRTUALIZATION ENVIRONMENTS Speaker: Matthias Beckert, Institute of Computer and Network Engineering, TU Braunschweig, DE Authors: Matthias Beckert1, Kai Björn Gemlau1 and Rolf Ernst2 1Institut für Datentechnik und Kommunikationsnetze - TU Braunschweig, DE; 2TU Braunschweig, DE Abstract Virtualization techniques for embedded real-time systems typically employ TDMA scheduling to achieve temporal isolation among different virtualized partitions. Due to the fixed TDMA schedule, worst case response times for IRQs and tasks are significantly increased. Recent publications introduced slack based IRQ shaping to mitigate this problem. While providing better response times for IRQs, those mechanisms neither improve task timings nor provide a work conserving scheduling. In order to provide such capabilities while still providing temporal isolation, we introduce a method based on the well known sporadic server model. In combination with a proposed budget scheduler the system is able to schedule a TDMA based configuration while providing better response times and the same amount of temporal isolation. We show correctness of the approach and evaluate it in a hypervisor implementation. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | 7.7.3 | PROGRAMMING AND ANALYSING SCENARIO-AWARE DATAFLOW ON A MULTI-PROCESSOR PLATFORM Speaker: Reinier van Kampenhout, Eindhoven University of Technology, NL Authors: Reinier van Kampenhout, Sander Stuijk and Kees Goossens, Eindhoven University of Technology, NL Abstract The FSM-SADF model of computation is especially suitable for analysing real-time applications with input-dependent behaviour such as different modes, variable execution times and scalable parallelism. Although FSM-SADF specifies which scenario transitions are possible, it does not specify how and when they are decided at runtime. Multiple actors of a scenario, e.g. video stream header parsing, may have to fire before it is known which scenario the application is in. We solve this causality dilemma with a concept for executing a sequence of scenarios, and demonstrate an implementation on multiple processors with rolling static-order scheduling. We furthermore present a platform-aware analysis model that covers concept and implementation, and integrate the contributions in a toolflow. A proof-of-concept confirms the low overhead of the implementation and the exact timing analysis of our model. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | IP3-16, 570 | CHRT: A CRITICALITY- AND HETEROGENEITY-AWARE RUNTIME SYSTEM FOR TASK-PARALLEL APPLICATIONS Speaker: Myeonggyun Han, UNIST, KR Authors: Myeonggyun Han, Jinsu Park and Woongki Baek, UNIST, KR Abstract Heterogeneous multiprocessing (HMP) is an emerging technology for high-performance and energy-efficient computing. While task parallelism is widely used in various computing domains from the embedded to machine-learning computing domains, relatively little work has been done to investigate the efficient runtime support that effectively utilizes the criticality of the tasks of the target application and the heterogeneity of the underlying HMP system with full resource management. To bridge this gap, we propose a criticality- and heterogeneity-aware runtime system for task-parallel applications (CHRT). CHRT dynamically estimates the performance and power consumption of the target task-parallel application and robustly manages the full HMP system resources (i.e., core types, counts, and voltage/frequency levels) to maximize the overall efficiency. Our experimental results show that CHRT achieves significantly higher energy efficiency than the baseline runtime system that employs the breadth-first scheduler and the state-of-the-art criticality-aware runtime system. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:01 | IP3-17, 621 | MOBIXEN: PORTING XEN ON ANDROID DEVICES FOR MOBILE VIRTUALIZATION Speaker: Jianguo Yao, Shanghai Jiao Tong University, CN Authors: Yaozu Dong1, Jianguo Yao2, Haibing Guan2, Ananth. Krishna R1 and Yunhong Jiang1 1Intel, US; 2Shanghai Jiao Tong University, CN Abstract The mobile virtualization technology provides a feasible way to improve the manageability and security for embedded systems. This paper presents an architecture named MobiXen to address these challenges. In the MobiXen, both Xen's physical memory space and virtual address space are shrunk as much as possible and thus Android owns more memory resource; optimizations are developed to reduce the virtualization overhead when Android is accessing system resources; new policies are implemented to achieve low suspend/resume latency. With these work adopted, MobiXen is customized as a high efficient mobile hypervisor. Detailed implementations shows that, most of the performance degradation brought by MobiXen is less than 3\%, which is imperceptible by end users. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:02 | IP3-18, 230 | OPTIMISATION OPPORTUNITIES AND EVALUATION FOR GPGPU APPLICATIONS ON LOW-END MOBILE GPUS Speaker: Leonidas Kosmidis, Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES Authors: Matina Maria Trompouki1 and Leonidas Kosmidis2 1Universitat Politècnica de Catalunya, ES; 2Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES Abstract Previous works in the literature have shown the feasibility of general purpose computations for non-visual applications on low-end mobile graphics processors using graphics APIs. These works focused only on the functional aspects of the software, ignoring the implementation details and therefore their performance implications due to their particular micro-architecture. Since various steps in such applications can be implemented in multiple ways, we identify optimisation opportunities, explore the different options and evaluate them. We show that the implementation details can significantly affect the obtained performance with discrepancies up to 3 orders of magnitude and we demonstrate the effectiveness of our proposal on two embedded platforms, obtaining more than 16x speedup over benchmarks designed following OpenGL ES 2 best practices. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | End of session Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Tuesday, March 28, 2017
Wednesday, March 29, 2017
Thursday, March 30, 2017
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