6.8 HiPEAC: European Network on High Performance and Embedded Architecture and Compilation

VINEYARD aims to develop the technology and the ecosystem that will enable the efficient integration of the hardware acceleration in the data centres, seamlessly. The deployment of energy-efficient hardware accelerators will be used to improve significantly the performance of cloud computing applications and reduce the energy consumption in data centres.

VINEYARD is developing an integrated framework for energy-efficient data centres based on programmable hardware accelerators. It is working towards a high-level programming framework that allows end-users to seamlessly utilize these accelerators in heterogeneous computing systems by using typical data-centre cluster frameworks (i.e. Spark). VINEYARD is also developing two types of novel energy-efficient servers integrating two kinds of hardware accelerator: programmable dataflow-based accelerators and FPGA-based accelerators. The servers coupled with dataflow-based accelerators are suitable for cloud computing applications that can be represented in dataflow graphs while the latter will be used for accelerating applications that need tight communication between the processor and the hardware accelerators.

VINEYARD also foster the establishment of an ecosystem that will empower open innovation based on hardware accelerators as data-centre plugins, thereby facilitating innovative enterprises (large industries, SMEs, and creative start-ups) to develop novel solutions using VINEYARDS's leading edge developments.

Nowadays, the prevalence of computing systems in our lives is so ubiquitous that it would not be far-fetched to state that we live in a cyber-physical world dominated by computer systems. These systems demand for more and more computational performance to process large amounts of data from multiple data sources, some of them with guaranteed processing response times. In other words, systems are required to deliver their results within pre-defined (and sometimes extremely short) time bounds. Examples can be found for instance in intelligent transportation systems for fuel consumption reduction in cities or railway, or autonomous driving of vehicles.

To cope with such performance requirements, chip designers produced chips with dozens or hundreds of cores, interconnected with complex networks on chip. Unfortunately, the parallelization of the computing activities brings many challenges, among which how to provide timing guarantees, as the timing behaviour of the system running within a many-core processor depends on interactions on shared resources that are most of the time not know by the system designer.

P-SOCRATES (Parallel Software Framework for Time-Critical Many-core Systems) is an FP7 European project, which developed a novel methodology to facilitate the deployment of standardized parallel architectures for real-time applications. This methodology was implemented (based on existent models and components) to provide an integrated software development kit, the UpScale SDK, to fully exploit the huge performance opportunities brought by the most advanced many-core processors, whilst ensuring a predictable performance and maintaining (or even reducing) development costs of applications. The presentation will provide an overview of the UpScale SDK, its underlying methodology, and the results of its application on relevant industrial use-cases.

With the ever-increasing need of computational power, heterogeneous multi- and many-processor SoCs provide the best trade-off between performance, cost, and power. However, one of the biggest hurdles to exploit multicore architectures from the SW side is how to efficiently develop performance and power co-optimised parallel applications. Making the right decisions in the vast SW design space can hardly be done by the programmer in a reasonable time frame, especially, when performing a manual design process. Considering an application that has been properly partitioned into multiple concurrent tasks, and programmed in a parallel language, the process of mapping those tasks onto the processors with the optimal voltage and frequency setting is a huge challenge for a certain design goal. An automatic approach is needed that determines the optimal decision, given an optimisation constraint. A great amount of research has been conducted at ICE aiming to optimise the performance of a parallelised application. The Silexica GmbH, a VC-backed spin-off from ICE, continues on this track of producing novel compiler technology and tools for programming embedded multicore platforms, and offers the tools and knowledge to the industry.

In order to co-optimise for power, accurate power modelling has to be integrated into the existing performance driven framework. ICE's electronic system-level power estimation methodology is a more than consequent starting point. The methodology takes the available power information from a reference power trace and back-annotates it to determine the coefficients of a linear power model. Several case studies have shown power estimation errors with less than 5%.

Based on the power modelling capability, a novel power-aware SW mapping heuristic has been implemented. This algorithm is verified in several case studies and used to identify the gain of sophisticated power management techniques by providing the power-performance trade-off.

The performance/power efficiency wall poses the major challenge faced nowadays by HPC. Looking straight at the heart of the problem, the hurdle to the full exploitation of today computing technologies ultimately lies in the gap between the applications' demand and the underlying computing architecture: the closer the computing system matches the structure of the application, the most efficiently the available computing power is exploited. Consequently, enabling a deeper customization of architectures to applications is the main pathway towards computation power efficiency. In addition to mere performance and power-efficiency, it is of paramount importance to meet new nonfunctional requirements posed by emerging classes of applications. In particular, a growing number of HPC applications demand some form of time- predictability, or more generally Quality-of-Service (QoS), particularly in those scenarios where correctness depends on both performance and timing requirements and the failure to meet either of them is critical.

The MANGO project builds on these considerations and will set inherent architecture-level support for application-based customization as one of its underlying pillars. In addition, an heterogeneous platform for HPC architecture exploration will be deployed.

AEGLE is a flagship project of the European Big Data unit with the vision to improve translational medicine and facilitate personalized and integrated care services across Europe. AEGLE recognizes that data-driven services are still needed to cater for the data versatility, volume, velocity and veracity within the whole data value of healthcare analytics. A true opportunity exists to produce value out of big data in healthcare with the goal to revolutionize integrated and personalised healthcare services. The AEGLE project targets to address the aforementioned open issues by implementing a full data value chain to create new value out of rich, multi-diverse, big health data. AEGLE's ultimate mission is to realize an European business ecosystem to healthcare stakeholders, industry and researchers for creating out-of-box knowledge in order to provide advanced data services supporting new products that will improve health.

The AEGLE project targets to provide a framework for Big Data analytics for healthcar. Big Data analytics problems are becoming increasingly common in a range of human-centered sciences, e.g. biology, medicine, healthcare, drug discovery etc. Ever increasing data volumes have lead to the development of a number of new parallel processing models. However, data volumes are increasing at a faster pace than the available processing power, thus making it increasingly difficult to keep up with the processing requirements of modern Big Data analytics applications. Conventional scaling approaches of simply adding more processing nodes to the data center can reach their limitations in available space, and power efficiency is also becoming increasingly import in terms of both cost and environmental impact of computing.

Currently, computer vision is rapidly moving beyond academic research and factory automation. With the appropriate platforms and tools, the emerging possibilities are endless in terms of wearable applications, augmented reality, surveillance, ambient-assisted living, etc.

Vision, our richest sensor, allows mining big data from reality. While the number of image sensors deployed across all products in the world is a small fraction of the total number of sensors deployed, the amount of data generated by them dwarfs the amount of data generated by all other types of sensors combined. This has a cost, vision is arguably the most demanding sensor in terms of power consumption and required processing power.

Our objective in this project is to build a power-size-cost-programmabilty optimized core vision platform that can work independently and also embedded into all types of artefacts. The envisioned open hardware is being combined with carefully designed APIs that maximize inferred information per milliwatt and adapt the quality of inferred results to each particular application. This will not only mean more hours of continuous operation, it will allow to create novel applications and services that go beyond what current vision systems can do, which are either personal/mobile or "always-on" but not both at the same time.