Date: Wednesday 29 March 2017
Time: 11:00 - 12:30
Location / Room: 5A
Chair:
Eugenio Villar, University of Cantabria, ES
This session adresses industrial research and practice on architecture, design, timing analysis techniques and analogue circuit sizing. The session will be rounded off by presentations of two European projects about to start, addressing cross-layer design of reconfigurable CPS and IoT for smart wearable applications.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 6.6.1 | AN ASYNCHRONOUS NOC ROUTER IN A 14NM FINFET LIBRARY: COMPARISON TO AN INDUSTRIAL SYNCHRONOUS COUNTERPART Speaker: Wayne Burleson, Advanced Micro Devices, Inc., US Authors: Weiwei Jiang1, Davide Bertozzi2, Gabriele Miorandi2, Steven M. Nowick1, Wayne Burleson3 and Greg Sadowski3 1Columbia University, US; 2University of Ferrara, IT; 3Advanced Micro Devices, US Abstract An asynchronous high-performance low-power 5-port network-on-chip (NoC) router is introduced. The proposed router integrates low-latency input buffers using a circular FIFO design, and a novel end-to-end credit-based virtual channel (VC) flow control for a replicated switch architecture. This asynchronous router is then compared to an AMD synchronous router, in a realistic advanced 14nm FinFET library. This is the first such comparison, to the best of our knowledge, using a real synchronous router baseline already fabricated in several commercial products. Initial post-synthesis pre-layout experiments show dominating results for the asynchronous router, when compared to the synchronous router. In particular, 55% less area and 28% latency improvement are observed for the asynchronous implementation. Also, 88% and 58% savings in idle and active power, respectively, are obtained. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 11:15 | 6.6.2 | AN ADVANCED EMBEDDED ARCHITECTURE FOR CONNECTED COMPONENT ANALYSIS IN INDUSTRIAL APPLICATIONS Speaker: Menbere Tekleyohannes, University of Kaiserslautern, DE Authors: Menbere Tekleyohannes1, Mohammadsadegh Sadri1, Martin Klein2, Michael Siegrist2, Christian Weis1 and Norbert Wehn1 1University of Kaiserslautern, DE; 2Wipotec GmbH, DE Abstract In recent years, connected component analysis (CCA) has become one of the vital image/video processing algorithms due to its wide-range applicability in the field of computer vision. Numerous applications such as pattern recognition, object detection and image segmentation involve connected component analysis. In the context of camera-based inspection systems, CCA plays an important role for quality assurance. State-of-the-art hardware architectures offer high performance implementations of CCA using field programmable gate arrays (FPGAs). However, due to their high memory-demand, most of these implementations inhibit a large resource utilization. In this paper, we propose a hybrid software-hardware architecture of CCA for an industrial application using Xilinx Zynq-7000 All Programmable System on Chip (SoC). By offloading the most resource consuming part of the algorithm to the embedded CPU, we achieved high performance, while reducing the required resources on the FPGA. Our proposed architecture saves more than 30% of on-chip memory (Block RAMs) compared to state-of-the-art hardware architectures without affecting the throughput. Furthermore, due to the embedded CPU, our system provides a versatile and highly flexible feature extraction at run-time without the necessity to reconfigure the FPGA. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 11:30 | 6.6.3 | WORKLOAD DEPENDENT RELIABILITY TIMING ANALYSIS FLOW Speaker: Ajith Sivadasan, TIMA Labs, FR Authors: Ajith Sivadasan1, Armelle Notin2, Vincent Huard2, Etienne Maurin2, Florian Cacho2, Sidi Ahmed Benhassain3 and Lorena Anghel4 1TIMA Labs, FR; 2STMicroelectronics, FR; 3TIMA, FR; 4Grenoble-Alpes University, FR Abstract Silicon measurements indicate the fact that the frequency limiting paths change as per aging and as a function of workload. This paper proposes a simulation flow that leads to the identification of such paths. Gate-level models provide an accurate estimate of aging of the critical paths by taking into consideration the stress experienced by corresponding standard cells for a given workload on the digital circuit and thereby providing a more accurate estimate of circuit aging. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 11:45 | 6.6.4 | PROBABILISTIC TIMING ANALYSIS ON TIME-RANDOMIZED PLATFORMS FOR THE SPACE DOMAIN Speaker: Francisco J. Cazorla, Barcelona Supercomputing Center and Spanish National Research Council (IIIA-CSIC), ES Authors: Mikel Fernandez1, David Morales2, Leonidas Kosmidis3, Alen Bardizbanyan4, Ian Broster5, Carles Hernandez1, Eduardo Quinones1, Jaume Abella6, Francisco Cazorla7, Paulo Machado8 and Luca Fossati8 1Barcelona Supercomputing Center, ES; 2BSC, ES; 3Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; 4Chalmers University of Technology, SE; 5Rapita Systems LTD, GB; 6Barcelona Supercomputing Center (BSC-CNS), ES; 7Barcelona Supercomputing Center and IIIA-CSIC, ES; 8ESA, IT Abstract Timing Verification is a fundamental step in real-time embedded systems, with measurement-based timing analysis (MBTA) being the most common approach used to that end. We present a Space case study on a real platform that has been modified to support a probabilistic variant of MBTA called MBPTA. Our platform provides the properties required by MBPTA with the predicted WCET estimates with MBPTA being competitive to those with current MBTA practice while providing more solid evidence on their correctness for certification. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:00 | 6.6.5 | CROSS-LAYER DESIGN OF RECONFIGURABLE CYBER-PHYSICAL SYSTEMS Speaker and Author: Michael Masin, IBM Research, IL Abstract In the last few years, besides the concepts of embedded and interconnected systems, also the notion of Cyber-Physical Systems (CPS) has emerged: embedded computational collaborating devices, capable of sensing and controlling physical elements and, often, responding to humans. The continuous interaction between the physical and the computing layers makes their design and maintenance extremely complex. Uncertainty management and runtime reconfigurability, to mention the most relevant ones, are rarely tackled by available commercial and academic toolchains. In this context, the Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments (CERBERO) EU project aims at developing a design environment for CPS based of two pillars: 1) a cross-layer model-based approach to describe, optimize, and analyze the system and all its different views concurrently and 2) an advanced adaptivity support based on a multi-layer autonomous engine. In this work, we describe the necessary components and the required developments for seamless design of reusable and reconfigurable CPS and System of Systems in uncertain hybrid environments. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:15 | 6.6.6 | INSPEX: DESIGN AND INTEGRATION OF A PORTABLE/WEARABLE SMART SPATIAL EXPLORATION SYSTEM Speaker and Author: Suzanne Lesecq, CEA, LETI, Minatec Campus, FR Abstract The INSPEX H2020 project main objective is to integrate automotive-equivalent spatial exploration and obstacle detection functionalities into a portable/wearable multi-sensor, miniaturised, low power device. The INSPEX system will detect and localise in real-time static and mobile obstacles under various environmental conditions in 3D. Potential applications range from safer human navigation in reduced visibility, small robot/drone obstacle avoidance systems to navigation for the visually/mobility impaired, this latter being the primary use-case considered in the project. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | IP3-5, 948 | A GENERIC TOPOLOGY SELECTION METHOD FOR ANALOG CIRCUITS WITH EMBEDDED CIRCUIT SIZING DEMONSTRATED ON THE OTA EXAMPLE Speaker: Andreas Gerlach, Robert Bosch Centre for Power Electronics, DE Authors: Andreas Gerlach1, Thoralf Rosahl2, Frank-Thomas Eitrich2 and Jürgen Scheible1 1Robert Bosch Centre for Power Electronics, DE; 2Robert Bosch GmbH, DE Abstract We present a methodology for automatic selection and sizing of analog circuits demonstrated on the OTA circuit class. The methodology consists of two steps: a generic topology selection method supported by a "part-sizing" process and subsequent final sizing. The circuit topologies provided by a reuse library are classified in a topology tree. The appropriate topology is selected by traversing the topology tree starting at the root node. The decision at each node is gained from the result of the part-sizing, which is in fact a node-specific set of simulations. The final sizing is a simulation-based optimization. We significantly reduce the overall simulation effort compared to a classical simulation-based optimization by combining the topology selection with the part-sizing process in the selection loop. The result is an interactive user friendly system, which eases the analog designer's work significantly when compared to typical industrial practice in analog circuit design. The topology selection method with sizing is implemented as a tool into a typical analog design environment. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | End of session Lunch Break in Garden Foyer Keynote Lecture session 7.0 in "Garden Foyer" 1350 - 1420 Lunch Break in the Garden Foyer |