Date: Tuesday 28 March 2017
Time: 17:00 - 18:30
Location / Room: 3B
Chair:
Muhammad Shafique, TU Wien, AT
The session covers variable-aware solutions at the system and circuit level. Firstly, neuromorphic circuits are addressed and its relation with process variation. After that, variability is again addressed but, this time, for entire computing systems.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 4.7.1 | ROBUST NEUROMORPHIC COMPUTING IN THE PRESENCE OF PROCESS VARIATION Speaker: Mehdi Kamal, University of Tehran, IR Authors: Ali BanaGozar1, Mohammad Ali Maleki1, Mehdi Kamal1, Ali Afzali-Kusha1 and Massoud Pedram2 1University of Tehran, IR; 2University of Southern California, US Abstract In this paper, an approach for increasing the sustainability of inverter-based memristive neuromorphic circuits in the presence of process variation is presented. The approach works based on extracting the impact of process variations on the neurons characteristics during the test phase through a proposed algorithm. In this method, first, some combinations of inputs and weights (based on the neuromorphic circuit structure) are injected into the circuit and the features of the neurons are determined. Next, these features which are back-annotated, are utilized in an efficient ex-situ training approach to determine the proper weights of the neurons. The approach provides a considerable improvement in the output accuracy. To evaluate the effectiveness of the proposed approach, some approximate applications are studied using 90nm technology. The results of the study reveal that using this framework provide, on average, 17X higher output accuracy compared to the cases that the impact of the process variation is not considered at all. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | 4.7.2 | AN ON-LINE FRAMEWORK FOR IMPROVING RELIABILITY OF REAL-TIME SYSTEMS ON "BIG-LITTLE" TYPE MPSOCS Speaker: Yue Ma, University of Notre Dame, US Authors: Yue Ma1, Thidapat Chantem2, Robert Dick3, Shige Wang4 and X, Sharon Hu1 1University of Notre Dame, US; 2Virginia Polytechnic Institute and State University, US; 3University of Michigan and Stryd, US; 4General Motors R&D, US Abstract Heterogeneous MPSoCs consisting of cores with different performance/power behaviors are widely used in many power-constrained real-time systems. Both soft-error reliability and lifetime reliability are key concerns in such systems. Although existing work have investigated related problems, they either focus on one of the two reliability concerns or propose complicated scheduling algorithms that cannot adequately address run-time workload and environment variations. This paper introduces an on-line heuristic to maximize soft-error reliability while satisfying a lifetime reliability constraint for soft real-time systems executed on MPSoCs composed of high-performance cores and low-power cores. Based on the run-time cores' frequencies and utilizations, the heuristic performs workload migration between the high-performance cores and low-power cores to achieve improved soft-error reliability. Experimental results from both a hardware platform and a simulator show that the proposed algorithm reduces the probability of faults by at least 30% compared to a number of representative existing approaches while satisfying the same lifetime reliability constraints. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:00 | 4.7.3 | APPLICATION PERFORMANCE IMPROVEMENT BY EXPLOITING PROCESS VARIABILITY ON FPGA DEVICES Speaker: Konstantinos Maragos, National Technical University of Athens, GR Authors: Konstantinos Maragos1, George Lentaris1, Kostas Siozios1, Dimitrios Soudris1 and Vasilis Pavlidis2 1National Technical University of Athens, GR; 2The University of Manchester, GR Abstract Process variability is known to be increasing with technology scaling in IC fabrication, thereby degrading the overall performance of the manufactured devices. The current paper focuses on the variability effect in FPGAs and the possibility to boost the performance of each device at run-time, after fabrication, based on the individual characteristics of this device. First, we develop a sensing infrastructure involving a wide network of customized ring oscillators to measure intra-chip and inter-chip variability in 28nm FPGAs, i.e., in eight Xilinx Zynq XC7Z020T-1CSG324 devices. Second, we develop a closed-loop framework based on dynamic reconfiguration of clock tiles, I/O data sniffing, HW/SW communication, and verification with test vectors, to dynamically increase the operating frequency in Zynq while preserving its correctness. Our results show intra-chip variability in the area of 5.2% to 7.7% and inter-chip variability up to 17%. Our framework improves the performance of example FIR designs by up to 90.3% compared to the SW tool reports and shows speed difference among devices by up to 12.4%. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | End of session Exhibition Reception in Exhibition Area The Exhibition Reception will take place on Tuesday in the exhibition area, where free drinks for all conference delegates and exhibition visitors will be offered. All exhibitors are welcome to also provide drinks and snacks for the attendees. |