Date: Tuesday 28 March 2017
Time: 17:00 - 18:30
Location / Room: 3A
Chair:
Graziano Pravadelli, University of Verona, IT
Co-Chair:
Elena Ioana Vatajelu, TIMA, FR
The section presents techniques and tools to generate testcases for functional validation and to define coverage metrics for functional qualification.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 4.4.1 | DATA FLOW TESTING FOR VIRTUAL PROTOTYPES Speaker: Muhammad Hassan, University of Bremen, DE Authors: Muhammad Hassan1, Vladimir Herdt1, Hoang M. Le1, Mingsong Chen2, Daniel Grosse3 and Rolf Drechsler3 1University of Bremen, DE; 2East China Normal University, CN; 3University of Bremen/DFKI GmbH, DE Abstract Data flow testing (DFT) has been shown to be an effective testing strategy. DFT features a high fault detection rate while avoiding the intense scalability problems to achieve full path coverage. In this paper we propose to apply data flow testing for SystemC virtual prototypes (VPs). Our contribution is twofold: First, we develop a set of SystemC specific coverage criteria for data flow testing. This requires to consider the SystemC semantics of using non-preemptive thread scheduling with shared memory communication and event-based synchronization. Second, we explain how to automatically compute the data flow coverage result for a given VP using a combination of static and dynamic analysis techniques. The coverage result provides clear suggestions for the testing engineer to add new testcases in order to improve the coverage result. Our experimental results on real-world VPs demonstrate the applicability and efficacy of our analysis approach and the SystemC specific coverage criteria to improve the testsuite. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | 4.4.2 | MINIME-VALIDATOR: VALIDATING HARDWARE WITH SYNTHETIC PARALLEL TESTCASES Speaker: Alper Sen, Bogazici University, TR Authors: Alper Sen1, Etem Deniz2 and Brian Kahne3 1Bogazici University, TR; 2TUBITAK, TR; 3NXP, US Abstract Programming of multicore architectures with large number of cores is a huge burden on the programmer. Parallel patterns ease this burden by presenting the developer with a set of predefined programming patterns that implement best practices in parallel programming. Since the behavior of patterns is well-known and understood they can also lower the burden for verification. In this work, we present a toolset, MINIME-Validator, for generating synthetic parallel testcases from a newly defined Parallel Pattern Markup Language (PPML) that uses the concept of parallel patterns. Our testcases mimic the behavior of real customer applications while being much smaller and can be used to generate traffic and validate e.g. inter-processor communication architectures. Experiments show that synthetic testcases can be used for finding representative hardware communication problems. To the best of our knowledge, this is the first time synthetic testcases using parallel programming patterns are used for hardware validation. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:00 | 4.4.3 | COST-EFFECTIVE ANALYSIS OF POST-SILICON FUNCTIONAL COVERAGE EVENTS Speaker: Avi Ziv, IBM Research - Haifa, IL Authors: Farimah Farahmandi1, Ronny Morad2, Avi Ziv2, Ziv Nevo2 and Prabhat Mishra1 1University of Florida, US; 2IBM Research - Haifa, IL Abstract Post-silicon validation is a major challenge due to the combined effects of debug complexity and observability constraints. Assertions as well as a wide variety of checkers are used in pre-silicon stage to monitor certain functional scenarios. Pre-silicon checkers can be synthesized to coverage monitors in order to capture the coverage of certain events and improve the observability during post-silicon debug. Synthesizing thousands of coverage monitors can introduce unacceptable area and energy overhead. On the other hand, absence of coverage monitors would negatively impact post-silicon coverage analysis. In this paper, we propose a framework for cost-effective post-silicon coverage analysis by identifying hard-to-detect events coupled with trace-based coverage analysis. This paper makes three major contributions. We propose a method to utilize existing debug infrastructure to enable coverage analysis in the absence of synthesized coverage monitors. This analysis enables us to identify a small percentage of coverage monitors that need to be synthesized in order to provide a trade-off between observability versus design overhead. To improve the observability further, we also present an observability-aware trace signal selection algorithm that gives priority to signals associated with important coverage monitors with negligible effect on debug observability. Our experimental results demonstrate that an effective combination of coverage monitor selection and trace analysis can drastically reduce (up to 10 times) the required coverage monitors without sacrificing observability. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | IP2-8, 273 | AUTOMATIC EQUIVALENCE CHECKING FOR SYSTEMC-TLM 2.0 MODELS AGAINST THEIR FORMAL SPECIFICATIONS Speaker: Mehran Goli, University of Bremen, DE Authors: Mehran Goli, Jannis Stoppe and Rolf Drechsler, University of Bremen, DE Abstract The necessity to handle the increasing complexity of digital circuits has led to the usage of more and more abstract design paradigms. In particular, the Electronic System Level (ESL) has become an area of active research and industrial application, especially via SystemC and its Transaction Level Modeling (TLM) framework. Additionally, the usage of formal specification languages such as the Unified Modeling Language (UML) prior to the implementation (even at higher abstraction levels) is now a broadly accepted workflow. Utilizing this layered approach leaves the translation from the specification to the implementation to the designer, leaving the question unanswered how the equivalence of these should be verified. This paper proposes a novel, non-intrusive and broadly applicable approach to automatically validate the equivalence of the structural and behavioral information of a SystemC-TLM 2.0 model and its formal specification. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:31 | IP2-9, 922 | (Best Paper Award Candidate) HEAD-MOUNTED SENSORS AND WEARABLE COMPUTING FOR AUTOMATIC TUNNEL VISION ASSESSMENT Speaker: Josue Ortiz, Complutense University of Madrid, ES Authors: Yuchao Ma and Hassan Ghasemzadeh, Washington State University, US Abstract As the second leading cause of blindness worldwide, glaucoma impacts a large population of individuals over 40. Although visual acuity often remains unaffected in early stages of the disease, visual field loss, expressed by tunnel vision condition, gradually increases. Glaucoma often remains undetected until it has moved into advanced stages. In this paper, we introduce a wearable system for automatic tunnel vision detection using head-mounted sensors and machine learning techniques. We develop several tasks, including reading and observation, and estimate visual field loss by analyzing user's head movements while performing the tasks. An integrated computational module takes sensor signals as input, passes the data through several automatic data processing phases, and returns a final result by merging task-level predictions. For validation purposes, a series of experiments is conducted with 10 participants using tunnel vision simulators. Our results demonstrate that the proposed system can detect mild and moderate tunnel visions with an accuracy of 93.3% using a leave-one-subject-out analysis. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | End of session Exhibition Reception in Exhibition Area The Exhibition Reception will take place on Tuesday in the exhibition area, where free drinks for all conference delegates and exhibition visitors will be offered. All exhibitors are welcome to also provide drinks and snacks for the attendees. |