Date: Tuesday 28 March 2017
Time: 14:30 - 16:00
Location / Room: 3A
Chair:
Michael Glass, Ulm University, DE
Co-Chair:
Yuko Hara-Azumi, Tokyo Institute of Technology, JP
This session starts with a guardbanding-based approach that uses cell libraries designed and classified for different temperature ranges for improving circuit timing as well as lifetime. This is followed by several approximate computation techniques that optimize the energy consumption of the circuits. The second paper in the session compares the use of approximate arithmetic components (adders, multipliers) with truncation and rounding techniques to diminish the bit-width of the units. The third work proposes a source-to-source transformation to optimize the energy-accuracy tradeoff. This session concludes with two IP presentations on approximate errors symbolic system synthesis.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:30 | 3.4.1 | (Best Paper Award Candidate) OPTIMIZING TEMPERATURE GUARDBANDS Speaker: Hussam Amrouch, Karlsruhe Institute of Technology (KIT), DE Authors: Hussam Amrouch1, Behnam Khaleghi2 and Joerg Henkel1 1Karlsruhe Institute of Technology, DE; 2Sharif University of Technology, IR Abstract We introduce the first temperature guardbands optimization based on thermal-aware logic synthesis and thermalaware timing analysis. The optimized guardbands are obtained solely due to using our so-called thermal-aware cell libraries together with existing tool flows and not due to sacrificing timing constraints (i.e. no trade-offs). We demonstrate that temperature guardbands can be optimized at design time through thermalaware logic synthesis in which more resilient circuits against worst-case temperatures are obtained. Our static guardband optimization leads to 18% smaller guardbands on average. We also demonstrate that thermal-aware timing analysis enables designers to accurately estimate the required guardbands for a wide range of temperatures without over/under-estimations. Therefore, temperature guardbands can be optimized at operation time through employing the small, yet sufficient guardband that corresponds to the current temperature rather than employing throughout a conservative guardband that corresponds to the worst-case temperature. Our daptive guardband optimization results, on average, in a 22% higher performance along with 9.2% less energy. Neither thermal-aware logic synthesis nor thermal-aware timing analysis would be possible without our thermal-aware cell libraries. They are compatible with use of existing commercial tools. Hence, they allow designers, for the first time, to automatically consider thermal concerns within their design tool flows even if they were not designed for that purpose. Download Software: This work is publicly available at http://ces.itec.kit.edu/dependable-hardware.php Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 3.4.2 | THE HIDDEN COST OF FUNCTIONAL APPROXIMATION AGAINST CAREFUL DATA SIZING: A CASE STUDY Speaker: Benjamin Barrois, University of Rennes 1 / IRISA, FR Authors: Benjamin Barrois1, Olivier Sentieys2 and Daniel Menard3 1University of Rennes - INRIA, FR; 2INRIA, FR; 3INSA Rennes, FR Abstract Many applications are error-resilient, allowing for the introduction of approximations in the calculations, as long as a certain accuracy target is met. Traditionally, fixed-point arithmetic is used to relax accuracy, by optimizing the bit-width. This arithmetic leads to important benefits in terms of delay, power and area. Lately, several hardware approximate operators were invented, seeking the same performance benefits. However, a fair comparison between the usage of this new class of operators and classical fixed-point arithmetic with careful truncation or rounding, has never been performed. In this paper, we first compare approximate and fixed-point arithmetic operators in terms of power, area and delay, as well as in terms of induced error, using many state-of-the-art metrics and by emphasizing the issue of data sizing. To perform this analysis, we developed a design exploration framework, APXPERF, which guarantees that all operators are compared using the same operating conditions. Moreover, operators are compared in several classical real-life applications leveraging relevant metrics. In this paper, we show that considering a large set of parameters, existing approximate adders and multipliers tend to be dominated by truncated or rounded fixed-point ones. For a given accuracy level and when considering the whole computation data-path, fixed-point operators are several orders of magnitude more accurate while spending less energy to execute the application. A conclusion of this study is that the entropy of careful sizing is always lower than approximate operators, since it require significantly less bits to be processed in the data-path and stored. Approximated data therefore always contain on average a greater amount of costly erroneous, useless information. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | 3.4.3 | HIGH-LEVEL SYNTHESIS OF APPROXIMATE HARDWARE UNDER JOINT PRECISION AND VOLTAGE SCALING Speaker: Seogoo Lee, The University of Texas at Austin, US Authors: Seogoo Lee1, Lizy John2 and Andreas Gerstlauer1 1The University of Texas at Austin, US; 2UT Austin, US Abstract In recent years, approximate computing has emerged as a promising approach to trade off quality of computed outputs for energy savings. In this paper, we present an approximate high-level synthesis (AHLS) approach that outputs a quality-energy optimized register-transfer-level implementation from an accurate high-level C description. Existing AHLS work only considers switching activity for energy savings under hardware approximations. By contrast, we aim to provide a general AHLS solution that also considers voltage scaling given a reduced processing time. To maximize voltage and associated energy reductions, we include both operation-level approximations by bit rounding and more aggressive operation eliminations as approximation techniques. Optimally exploiting scaling opportunities under such approximations requires tight interaction with scheduling tasks. We address this problem by combining an optimization pass that estimates the scheduling impact of approximations with fast yet accurate quality-energy models and an efficient optimization solver to find near-optimal solutions constructively. Results show that when considering voltage scaling, up to 24.5 % higher energy savings can be achieved compared to approaches that only consider switching activity. Our heuristic solver is able to find solutions within 0.1 % of average energy savings compared to an exhaustive search, all while being up to 1,400x faster than simulation-based methods. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | IP1-13, 237 | ACCOUNTING FOR SYSTEMATIC ERRORS IN APPROXIMATE COMPUTING Speaker: Martin Bruestel, Technical University Dresden, DE Authors: Martin Bruestel1 and Akash Kumar2 1Technical University Dresden, DE; 2Technische Universitaet Dresden, DE Abstract Approximate computing is gaining more and more attention as potential solution to the problem of increasing energy demand in computing. Several recent works focus on the application of deterministic approximate computing to arithmetic computations. Circuits for addition and multiplication are simplified, trading exactness for energy and/or speed. Recent approximation techniques for adders focus on modifications of individual full adders' truth tables or shortening carry chains. While the resulting error is usually characterized with statistical measures over the range of possible input/output combinations, the actual adder is a static nonlinear system regarding arithmetic operations and signal processing. The resulting unexpected effects present a challenge for adopting approximate computing as a widespread and standard application-level optimization technique. This paper focuses on the deterministic effects of approximate multi-bit adders, which are especially evident for certain input data in an otherwise well specified systems, showing the necessity to look beyond purely statistical measures. We show which fundamental principles are violated depending on the chosen approximation scheme, and how this choice affects practical applications. This can serve as a basis for designers to make informed decisions about the use of approximate adders at the application level. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:01 | IP1-14, 467 | GAUSSIAN MIXTURE ERROR ESTIMATION FOR APPROXIMATE CIRCUITS Speaker: Amin Ghasemazar, The University of British Columbia, CA Authors: Amin Ghasemazar and Mieszko Lis, University of British Columbia, CA Abstract In application domains where perceived quality is limited by human senses, where data are inherently noisy, or where models are naturally inexact, approximate computing offers an attractive tradeoff between accuracy and energy or performance. While several approximate functional units have been proposed to date, the question of how these techniques can be systematically integrated into a design flow remains open. Ideally, units like adders or multipliers could be automatically replaced with their approximate counterparts as part of the design flow. This, however, requires accurately modelling approximation errors to avoid compromising output quality. Prior proposals have either focused on describing errors per-bit or significantly limited estimation accuracy to reduce otherwise exponential storage requirements. When multiple approximate modules are chained, these limitations become critical, and propagated error estimates can be orders of magnitude off. In this paper, we propose an approach where both input distributions and approximation errors are modelled as Gaussian mixtures. This naturally represents the multiple sources of error that arise in many approximate circuits while maintaining reasonable memory requirements. Estimation accuracy is significantly better than prior art (up to 7.2× lower Hellinger distance) and errors can be accurately propagated through a cascade of approximate operations; estimates of quality metrics like MSE and MED are within a few percent of simulation-derived values. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:02 | IP1-15, 215 | (Best Paper Award Candidate) ENHANCING SYMBOLIC SYSTEM SYNTHESIS THROUGH ASPMT WITH PARTIAL ASSIGNMENT EVALUATION Speaker: Kai Neubauer, University of Rostock, DE Authors: Kai Neubauer1, Philipp Wanko2, Torsten Schaub2 and Christian Haubelt1 1University of Rostock, DE; 2University of Potsdam, DE Abstract The design of embedded systems is becoming continuously more complex such that efficient design methods are becoming crucial for competitive results regarding design time and performance. Recently, combined Answer Set Programming (ASP) and Quantifier Free Integer Difference Logic (QF-IDL) solving has been shown to be a promising approach in system synthesis. However, this approach still has several restrictions limiting its applicability. In the paper at hand, we propose a novel ASP modulo theories (ASPmT) system synthesis approach, which (i) supports more sophisticated system models, (ii) tightly integrates the QF-IDL solving into the ASP solving, and (iii) makes use of partial assignment checking. As a result, more realistic systems are considered and an early exclusion of infeasible solutions improves the entire system synthesis. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | End of session Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Tuesday, March 28, 2017
Wednesday, March 29, 2017
Thursday, March 30, 2017
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