Date: Thursday 30 March 2017
Time: 16:00 - 17:30
Location / Room: 5A
Chair:
Nuno Horta, Instituto de Telecomunicacoes, PT
Co-Chair:
Deuk Heo, Washington State University, US
This session presents area- and energy-efficient design methodologies for high-performance analog circuits and systems. These papers include an energy-efficient asynchronous digital design method for digitally-assisted analog circuits, a design method of high-density energy storage components, and a robust communication link design for communication systems.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 16:00 | 12.6.1 | BENEFITS OF ASYNCHRONOUS CONTROL FOR ANALOG ELECTRONICS: MULTIPHASE BUCK CASE STUDY Speaker: Danil Sokolov, Newcastle University, GB Authors: Danil Sokolov1, Vladimir Dubikhin1, Victor Khomenko1, David Lloyd2, Andrey Mokhov1 and Alex Yakovlev1 1Newcastle University, GB; 2Dialog Semiconductor, GB Abstract Analog and mixed signal (AMS) electronics becomes increasingly complex and needs to be digitally enhanced by its own control circuitry. The RTL synthesis flow routinely used for digital logic is however optimized for synchronous data processing and produces inefficient control for AMS. In this paper we demonstrate the evident benefits of asynchronous circuits in the context of AMS systems, and propose an asynchronous design for analog electronics (A4A) flow for their specification, synthesis, and formal verification. A library of specialized analog-to-asynchronous (A2A) components is developed for interfacing analog signals to asynchronous control. A4A flow is automated in the Workcraft framework and evaluated using a multiphase buck converter case study. The simulation results show improved response time, voltage ripple, and peak current of the buck when controlled asynchronously. These benefits lead to the higher efficiency of power conversion, and can be traded off for the cost of analog components. A4A flow, A2A interfaces, and Workcraft tools are used for development of power converters at Dialog Semiconductor. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:30 | 12.6.2 | HIGH-DENSITY MOM CAPACITOR ARRAY WITH NOVEL MORTISE-TENON STRUCTURE FOR LOW-POWER SAR ADC Speaker: Pang-Yen Chou, Technical University of Munich, DE Authors: Nai-Chen Chen1, Pang-Yen Chou2, Helmut Graeb3 and Mark Po-Hung Lin1 1National Chung Cheng University, TW; 2Technische Universität München, DE; 3TU Muenchen, DE Abstract The design of capacitor structures have great impact on capacitance density, parasitic capacitance, routability, and matching quality of capacitor network in a SAR ADC, which may affect power, performance, and area of the whole data converter. Most of the recent studies focused on common-centroid placement and routing optimization of the capacitor network. Only few of them investigated the structures of highly integrated capacitors. In this paper, a novel mortise-tenon metal-oxide-metal capacitor structure is proposed, which has the advantages of high capacitance density and small parasitic capacitance. Based on the proposed structure, an integer-linear-programming based capacitor sizing and routing parasitic matching method is further introduced. Experimental results show that the proposed structure and method can achieve the best capacitance density and matching quality of the capacitor network in a SAR ADC. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:00 | 12.6.3 | ADAPTIVE INTERFERENCE REJECTION IN HUMAN BODY COMMUNICATION USING VARIABLE DUTY CYCLE INTEGRATING DDR RECEIVER Speaker: Shreyas Sen, Purdue University, US Authors: Shovan Maity1, Debayan Das1 and Shreyas Sen2 1Purdue University, US; 2ECE, Purdue University, US Abstract Connected smart wearable devices are becoming increasingly popular with the advent of cheap, miniaturized, ultra-low-power computing and communication. Human Body Communication (HBC) is emerging as an alternative to Wireless Body Area Network (WBAN) for communication among these devices, as it provides higher energy-efficiency and security. One of the biggest bottleneck of HBC is the interference picked up due to the human body antenna effect, with Signal to Interference Ratio often worse than -20dB. An interference robust integrating dual data rate (DDR) receiver is introduced which can adapt itself to changin interference conditions and provide high interference rejection by Pulse Width Modulation of integration clock, thus dynamically changing its duty cycle. The theory, architecture of the receiver is developed along with the adaptation algorithm to train the receiver to find the optimum duty cycle of operation.System-level simulations show >20 dB of rejection even in presence of variable interference frequencies. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | End of session | |