Date: Thursday 30 March 2017
Time: 16:00 - 17:30
Location / Room: 3A
Chair:
Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE
Co-Chair:
Michael Huebner, Ruhr-University Bochum, DE
The first paper presents a predictive approach to measure the impact of platform changes on the application perfomance. The second paper introduces a unifying approach for expressing multiple models of computations. The final paper compares two alternative implementations to realize faithfully the logical execution time model of computation.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 16:00 | 12.4.1 | (Best Paper Award Candidate) SAMPLING-BASED BINARY-LEVEL CROSS-PLATFORM PERFORMANCE ESTIMATION Speaker: Xinnian Zheng, University of Texas at Austin, US Authors: Xinnian Zheng, Haris Vikalo, Shuang Song, Lizy K. John and Andreas Gerstlauer, The University of Texas at Austin, US Abstract Fast and accurate performance estimation is a key challenge in modern system design. Recently, machine learning-based approaches have emerged that allow predicting the performance of an application on a target platform from executions on a different host. However, existing approaches rely on expensive instrumentation that requires source code to be available. We propose a novel sampling-based, binary- level cross-platform prediction method that accurately predicts performance of a workload on a target by relying on various performance statistics sampled on a host using built-in hardware counters. In our proposed framework, samples acquired from the host and target do not satisfy straightforward one-to-one correspondence that characterizes prior instrumentation-based approaches. The resulting alignment problem is NP-hard; to solve it efficiently, we develop a stochastic dynamic coupling (SDC) algorithm which, under mild assumptions, with high probability closely approximates optimal alignment. The prediction model constructed using SDC-aligned samples achieves on average 96.5% accuracy for 45 benchmarks at speeds of over 3 GIPS. At similar accuracies, this is up to 6× faster than instrumentation- based prediction, and approximately twice the speed of executing the same applications natively on our ARM target. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:30 | 12.4.2 | A LAYERED FORMAL FRAMEWORK FOR MODELING OF CYBER-PHYSICAL SYSTEMS Speaker: George Ungureanu, KTH Royal Institute of Technology, SE Authors: George Ungureanu and Ingo Sander, KTH Royal Institute of Technology, SE Abstract Designing cyber-physical systems is highly challenging due to its manifold interdependent aspects such as composition, timing, synchronization and behavior. Several formal models exist for description and analysis of these aspects, but they focus mainly on a single or only a few system properties. We propose a formal composable framework which tackles these concerns in isolation, while capturing interaction between them as a single, layered model. This yields a holistic, fine-grained, hierarchical and structured view of a cyber-physical system. We demonstrate the various benefits for modeling, analysis and synthesis through a typical example. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:00 | 12.4.3 | EFFICIENT SYNCHRONIZATION METHODS FOR LET-BASED APPLICATIONS ON A MULTI-PROCESSOR SYSTEM ON CHIP Speaker: Gabriela Breaban, Technical University of Eindhoven, NL Authors: Gabriela Breaban, Sander Stuijk and Kees Goossens, Technical University of Eindhoven, NL Abstract Distributed control applications cover a wide range of areas such as automotive, avionics, and automation. The Logical Execution Time (LET) Model of Computation (MoC) was proposed as a formal method to describe the functional and timing behavior of such applications. However, modern Multi-Processor Systems on Chip (MPSOC) do not have a shared notion of time between processors, due to their use of Globally Asynchronous Locally Synchronous (GALS) architecture. In this paper we propose two methods (based on FIFO channels and barriers) to implement time and data synchronization on a MPSOC. While a barrier synchronizes the execution flows of tasks at predefined points in their executions, a FIFO is an asynchronous data communication method between two tasks. First, they are used to implement LET applications. Next, we show how dataflow applications and mixed LET-dataflow applications are supported too. We implemented both methods on a MPSOC prototyped on a FPGA, and show that the data synchronization outperforms the related work by 67% in terms of software overhead. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | End of session | |