W08 First Workshop on Resource Awareness and Application Autotuning in Adaptive and Heterogeneous Computing

Chair:
Cristina Silvano, Politecnico di Milano, IT

End of Dennard scaling and increasing performance to cost ratios on multicore architectures have recently stimulated a new era of increasingly heterogeneous compute architectures and large diversification of integrated circuits has dawned. During this talk, we will elaborate on our ongoing efforts within the Xilinx research organization to shed light on the universal question what applications work on which architectures best, and benchmark and characterize a wide spectrum of applications and compute architectures including FPGAs, GPUs, Xeons and Xeon Phis.

Resource sharing and interferences of multiple threads of one, but even worse between multiple application programs running concurrently on a Multi-Processor System-on-a-Chip (MPSoC) today make it very hard to provide any timing or throughput-critical applications with time bounds.
Additional interferences result from the interaction of OS functions such as thread multiplexing and scheduling as well as complex resource
(e.g., cache) reservation protocols used heavily today. Finally, dynamic power and temperature management on a chip might also throttle down processor speed at arbitrary times leading to additional varations and jitter in execution time. This may be intolerable for many safety-critical applications such as medical imaging or automotive driver assistance systems.

Static solutions to provide the required isolation by allocating distinct resources to safety- or performance-critical applications may not be feasible for reasons of cost and due to the lack of efficiency and unflexibility.

In this invited talk, we first review and present novel definitions of predictability of execution qualities. Subsequently, we distinguish two techniques for improving predictability called restriction and isolation and present new definitions. Then, new techniques for adaptive isolation of resources including processor, I/O, memory as well as communication resources on demand on an MPSoC are introduced based on the paradigm of Invasive Computing.
In Invasive Computing, a programmer may specify bounds on the execution quality of a program or even segment of a program followed by an invade command that returns a constellation of exclusive resources called a claim that is subsequently used in a by-default non-shared way until being released
again by the invader. Through this principle, it becomes possible to isolate applications automatically and in an on-demand manner. In invasive computing, isolation is supported on all levels of hardware and software including the OS. Together with restriction (of input uncertainties), the level of on-demand predictability of program execution qualities may be fundamentally increased.

For a broad class of streaming applications, and a concrete demonstration based on a complex object detection application algorithm chain taken from robot vision, we show how jitter-minimized implementations become possible, even for statically unknown arrivals of other concurrent applications.

Chair:
Walter Stechele, TUM, DE

Numeric simulations and scientific computing cause an increasing demand for high performance computing resources. However, limitations due to energy consumption and limited application scalability require significant research efforts to build the next generation of even larger, yet more efficient supercomputers.
This talk will show the concepts and achievements of the EU funded DEEP-ER, and Mont-Blanc projects in researching and prototyping new computer architectures suited for future scientific computing applications and also explain the challenges when trying to tune application performance and energy efficiency at scale.

Chair:
Stephan Wong, TU Delft, NL

The variety of concerns developers may have to face when developing and compiling their applications overloads the development and deployment phases. When targeting contemporary systems (e.g., including heterogeneous many/multicore architectures) developers need to focus on specific mapping decisions and optimizations, specification of runtime adaptivity strategies, and features related to the tools being used. Monitoring, adaptivity, and tuning are three fundamental features developers may need to consider in order to achieve more efficient software and hardware/software solutions. One of the challenges is related to the way to express these features when considering General Programming Languages (GPLs), such as C and Java. In this talk we present our Domain-Specific Language (DSL) approach and the challenges we face to make the approach highly useful to developers. Our approach is based on LARA, an aspect-oriented programming (AOP) language, specifically designed for allowing developers to program code instrumentation strategies, to control the application of code transformations and compiler optimizations, and to effectively control different tools in a toolchain. LARA provides a separation of concerns, including non-functional requirements and strategies, while allowing to exploit the benefits of an automatic approach for various domain-specific and target component-specific compilation/synthesis tools. The experiments of using LARA in the context of different aspects of programming and compilation have revealed its cross-cutting and cross-layer benefits. In this talk, we will briefly introduce the LARA language, its current status and supporting tools, as well as some of the plans related to the extensions to LARA in the context of the H2020 ANTAREX project.

Capabilities of self-awareness have been shown to facilitate the sensible management of a system's resources in the presence of faults and when environmental conditions and demands change. This is not surprising since a detailed knowledge of the system's own state, its shortcomings, its performance as well as the environment's expectations is a precondition to allocate the available resource where they are most useful.

The talk will demonstrate this principle by way of the Cyber-physical SoC (CPSoC), which is a platform full of sensors to monitor delays, power consumption, temperature, and aging phenomena. This information is used to continuously adjust resource usage resulting in minimal power consumption and wear out for a given performance target.

Chair:
Jeronimo Castrillon, TU Dresden, Germany, DE

Speakers from morning & afternoon sessions are invited as panelists.

Chair: Michael Hübner