W07 International Workshop on Emerging Memory Solutions

Chair:
Christian Weis, University of Kaiserslautern, DE

Abstract:
Energy and power costs are the primary reasons that our system-wide execution throughput (OPS) is no better than it currently is … while one could staple together 100 Oak Ridge Titans to create an exascale system, not many could afford to pay the resulting electric bill. And yet, a significant amount of research is still focused on increasing processor performance, rather than decreasing power and energy-to-solution. Modern high-performance systems are not throughput-bound; they are power-bound. Processing is so cheap it is effectively free; shaving power and energy costs at every opportunity, and at every level of the system, is the trick. Similarly, memory and communication are the primary reasons that our time-to-solution is no better than it currently is … the memory system is slow; the communication overhead is high; and yet a significant amount of research is still focused on increasing processor performance, rather than decreasing (the cost of) data movement. Modern high-performance systems are not compute-bound; they are data-bound. ALUs are so cheap that some propose to put them out in the memory … processing is free; getting the right data to the right place, cheaply, is the trick.  This talk will discuss recent technologies that our group has helped to develop in high-performance systems, including flash-based main memories and Micron's Hybrid Memory Cube, arguing that the design of exascale systems is almost entirely a memory-systems issue.

Bio:
Bruce Jacob is a Keystone Professor of Electrical and Computer Engineering and former Director of Computer Engineering at the University of Maryland in College Park. He received the AB degree in mathematics from Harvard University in 1988 and the MS and PhD degrees in CSE from the University of Michigan in Ann Arbor in 1995 and 1997, respectively. He holds several patents in the design of circuits for electric guitars and started a company around them. He also worked for two successful startup companies in the Boston area: Boston Technology and Priority Call Management. At Priority Call Management he was the initial system architect and chief engineer. He is a recipient of a US National Science Foundation CAREER award for his work on DRAM, and he is the lead author of an absurdly large book on the topic of memory systems. His research interests include system architectures, memory systems, operating systems, and electric guitars.

Chair:
Pascal VIVET, CEA-Leti, FR

Chair:
Rob Aitken, ARM, US

Abstract:
To continue reducing voltage in scaled technologies, both circuit and architecture-level resiliency techniques are needed to tolerate process-induced defects, variation, and aging in SRAM cells. Many different resiliency schemes have been proposed and evaluated, but most prior results focus on voltage reduction instead of energy reduction. At the circuit level, device cell architectures and assist techniques have been shown to lower Vmin for SRAM, while at the architecture level, redundancy and cache disable techniques have been used to improve resiliency at low voltages. This paper presents a unified study of error tolerance for both circuit and architecture techniques and estimates their area and energy overheads.  Optimal techniques are selected by evaluating both the error-correcting abilities at low supplies and the overheads of each technique in a 28nm.  The results can be applied to many of the emerging memory technologies.

Bio:
Borivoje Nikolić is the National Semiconductor Distinguished Professor of Engineering at the University of California, Berkeley.  He received the Dipl.Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Serbia, in 1992 and 1994,  respectively, and the Ph.D. degree from the University of California at Davis in 1999. His research activities include digital, analog and RF integrated circuit design and VLSI implementation of communications and signal processing algorithms. He is co-author of the book Digital Integrated Circuits: A Design Perspective, 2nd ed, Prentice-Hall, 2003. Dr. Nikolić received many awards in his career, including the NSF  CAREER award in 2003, and the best paper awards at the IEEE International Solid- State Circuits Conference, Symposium on VLSI Circuits, IEEE International SOI Conference, European Solid-State Circuits Research Conference, European Solid-State Device Research Conference, S3S conference and the ACM/IEEE International Symposium of Low- Power Electronics.

Moderator:
Rob Aitken, ARM, US

Panelists:
Ahmed Hemani, KTH, SE
Ivan Ivanov, Micron, DE
Ian O'Connor, ECL, FR
Yervant Zorian, Synopsys, US
Jan Van Houdt, IMEC, BE

Current memory systems consist of SRAMs, DRAMs and Flash memories/HDDs. The landscape of emerging memory technologies is changing quickly and memories differentiate in their availability, maturity, performance, power and endurance. Thus, this panel will highlight the cases where these new emerging memories potentially fit and where it is sensible to use them.

Chair:
Bastien Giraud, CEA-Leti, FR

Abstract:
Next-generation information technologies will process unprecedented amounts of loosely-structured data, including streaming video and audio, natural languages, real-time sensor readings, and contextual environments. These newly available data far exceed the processing capacity of existing computing architectures.
The N3XT (Nano-Engineered Computing Systems Technology) approach overcomes these challenges through recent advances across the computing stack: (a) one-dimensional carbon nanotubes and two-dimensional layered nanomaterials for high performance and energy efficiency, (b) high-density non-volatile resistive and magnetic memories, (c) Ultra-dense (e.g., monolithic) three-dimensional integration of logic and memory for fine-grained connectivity, (d) new architectures and runtimes for computation immersed in memory, and (e) new materials technologies and their integration for efficient heat removal.
Compared to conventional approaches, N3XT architectures promise to improve the energy efficiency of abundant-data applications significantly, in the range of three orders of magnitude, thereby enabling new frontiers of applications for both mobile devices and the cloud.

Bio:
Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Before joining Stanford, he was a Principal Engineer at Intel.
Prof. Mitra's research interests include robust systems, VLSI design, CAD, validation and test, emerging nanotechnologies, and emerging neuroscience applications.  His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer, and it was featured on the cover of NATURE. The US NSF presented this work as a Research Highlight to the US Congress, and it also was highlighted as "an important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide.
Prof. Mitra's honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, the ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation, "a test of time honor" for an outstanding technical contribution, the Semiconductor Research Corporation's Technical Excellence Award, and the Intel Achievement Award, Intel's highest corporate honor.  He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology.
Prof. Mitra has served on numerous conference committees and journal editorial boards. He served on DARPA's Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.

Chair:
Gregory Di Pendina, CNRS-Spintec, FR

Chair:
Matthias Jung, University of Kaiserslautern, DE

Abstract:
Computing systems as well as embedded systems have been continuously improved performance and power efficiency. In order to achieve this improvement, the systems have required high bandwidth memories, especially DRAM. One of good emerging solutions of high bandwidth memory is the High Bandwidth Memory (HBM), a JEDEC standard product, which can respond to next generation memory subsystem requirements.

Abstract:
Processing in Memory enables optimal bandwidth and latency thanks to the proximity with data. Significant performance improvements of data-centric applications can be measured when hundreds of co-processors are distributed in DRAM. At the same time, to facilitate integration and adoption, hardware and software should be open and compatible with legacy, including DDR/DIMM.

Chair:
Kaya Can Akyel, CEA-Leti, FR

Authors:

F.Oboril¹, R.Bishnoi¹, M.Ebrahimi¹, and M.Tahoori¹ , G. Di Pendina², K.Jabeur², G.Prenat^2
1Karlsruhe Institute of Technology, Germany
²Univ. Grenoble Alpes, CNRS, CEA, INAC-SPINTEC, Grenoble, France

Authors:

Yohei Umeki¹, Koji Yanagida¹, Hiroaki Kurotsu¹, Hiroto Kitahara¹, Haruki Mori¹, Shintaro Izumi¹, Masahiko Yoshimoto¹,Hiroshi Kawaguchi¹, Shusuke Yoshimoto², Koji Tsunoda³, Toshihiro Sugii³

¹ Graduate School of System Informatics Kobe University, Japan
² The Institute of Scientific and Industrial Research, Osaka University, Japan
³ Low-Power Electronics Association and Project (LEAP), Japan

Authors:

Ajay Kapoor, Nur Engin, NXP Semiconductors, NL

Authors:

Erfan Azarkhish¹, Davide Rossi¹, Igor Loi¹, Luca Benini^1,2

¹ DEI, University of Bologna, Bologna, Italy
² ITET, Swiss Federal Institute of Technology, Zurich, Switzerland

Authors:

Rou-Li Melody Wang, Yun-Chao Yu, and Jin-Fu

Department of Electrical Engineering National Central University , Taiwan

Chair:
Kaya Can Akyel, CEA-Leti, FR

Author:

Said Hamdioui, Computer Engineering, Delft University of Technology, NL

Authors:

Yong-Xiao Chen and Jin-Fu Li, Advanced Reliable Systems (ARES) Lab., Department of Electrical Engineering, National Central University, Taiwan

Authors:

Frank Vater and Mario Schoelzel, IHP GmbH, Germany

Authors:

Joseph Nguyen^1,2, D. Turgis¹, D. Bonciani¹, B. Lhomme¹, Y. Carminati¹, O. Callen¹, G. Guirleo¹, L. Ciampolini¹, G. Ghibaudo²

¹ STMicroelectronics, Crolles, France
²IMEP-LAHC, Grenoble, France

Authors:

Oskar Andersson, Babak Mohammadi, and Joachim Neves Rodrigues, Department of Electrical and Information Technology, Lund University, Sweden

Authors:

Nasim Farahini¹, Matthias Jung^2, Pei Liu¹, Smah Jafri¹, Christian Weis², Ahmed Hemani¹, Norbert Wehn²

¹KTH, Sweden
²University of Kaisertslautern, Germany

Authors:

Kaya Can Akyel, Fabien Clermidy, Jean-Francois Nodin, Luca Perniola

CEA-Leti, Grenoble, France

Authors:

Rotem Ben-Hur and Shahar Kvatinsky, Israel Institute of Technology, Israel

Chair:
Christian Weis, University of Kaiserslautern, DE

Co-Chair:
Bastien Giraud, CEA-Leti, FR