W05 ERMAVSS: Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems

Chair:
Adrian Evans, iRoC Technologies, FR

During this session, the workshop organizers will welcome the participants and give a very brief overview of the MorV and Clereco FP7 projects.

Chair:
Dimitris Gizopoulos, University of Athens, Department of Informatics & Telecommunications, GR

In this session two talks will be given by leaders in academia and industry, highlighting leading cross-layer solutions as well as the great challenges faced by industry.

Summary

Resilience to hardware failures is essential for a large class of future computing systems that are constrained by the so-called power wall: from embedded systems to supercomputers. To overcome this major challenge, we advocate and examine a cross-layer resilience approach. Two major components of this approach are: 1. System- and software-level effects of circuit-level faults are considered from early stages of system design; and, 2. resilience techniques are implemented across multiple layers of the system stack - from circuit and architecture levels to runtime and applications - such that they work together to achieve required degrees of resilience in a highly energy-efficient manner. Illustrative examples to demonstrate key aspects of cross-layer resilience will be discussed.

Biography

Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Before joining Stanford, he was a Principal Engineer at Intel.

Prof. Mitra's research interests include robust systems, VLSI design, CAD, validation and test, emerging nanotechnologies, and emerging neuroscience applications. His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. His work on carbon nanotubes, jointly with his students and collaborators, resulted in the demonstration of the first carbon nanotube computer, and it was featured on the cover of NATURE. The NSF presented this work as a Research Highlight to the US Congress, and it also was highlighted as "an important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide.

Prof. Mitra's honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation, "a test of time honor" for an outstanding technical contribution, the Semiconductor Research Corporation's Technical Excellence Award, and the Intel Achievement Award, Intel's highest corporate honor. He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology.

Prof. Mitra has served on numerous conference committees and journal editorial boards. He served on DARPA's Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.

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Summary

In this talk, Yongsheng Sun, will introduce HiSilicon (海思) and describe their cutting edge products. HiSilicon is one of the largest fabless companies and currently ships chips in the most advanced process technologies. Due to their success and huge number of products being shipped, reliability is a top concern. Sarinda Wang will describe the key challenges when designing highly reliable, silicon intenstive products. Specific issues will also be discussed to sensitisize the audience to the real-world reliability problems faced when shipping products in the most advanced technologies.

About the Speaker

Yongsheng Sun received the B.S and M.S degree in Microelectronics from the University of Electronic Science and Technology of China in 2003 and 2006, respectively. In 2006, he joined Hisilicon Technologies Co., LTD. as a quality and reliability engineer, responsible for supplier's quality and reliability management. His current work is focus on Design for Reliability since 2011.

Chair:
Domenik Helms, OFFIS, DE

The poster sessions will be held during the coffee breaks in the morning (10:30..11:00) and from (14:30..15:00). During the workshop, each poster presenter will be give 1-2 minutes on the podium to quickly describe their work and entice participants to drop by and view their poster.

Chair:
Praveen Raghavan, IMEC, BE

During this sesion, participants are invited to demonstrate tools which help implement advance reliability flows.

Chair:
Alberto Bosio, LIRMM - University of Montpellier 2, FR

In this session, we will hear the perspectives of a major EDA vendor regarding the challenges in providing tools for meeting the reliability targets for automotive ICs.

Summary

Recent years, to enhance automotive functionalities for more driving enjoyment and hazard prevention, more and more electronic devices are used to monitor and control automotive operation. To ensure the safety of drivers and passengers, these electronic devices need higher reliability. In this talk, we will present what Mentor Graphics are doing to prepare for these reliability and safety challenges in pre-silicon, post-silicon and system operations.

About the Speaker

Wu-Tung Cheng is a Chief Scientist and Advanced Test Research Director in Mentor Graphics. He is an IEEE fellow since year 2000. He has over 150 publications and 50 patents in semiconductor manufacture test and diagnosis area. In 2006, he received ITC best paper award. In 2008, he received ITC honorable mention award. In 2014, he received ATS best paper award. He received his Ph.D. degree in Computer Science from the University of Illinois at Urbana-Champaign in 1985.

Chair:
Stefano Di Carlo, Politecnico di Torino, IT

Robert C. Aitken is an ARM Fellow and technology lead for ARM Research. His areas of responsibility include technology roadmapping, library architecture for advanced process nodes, and low power design. His research interests include design for variability, resilient computing, and memory robustness. His group has participated in numerous chip tape-outs, including 8 at or below the 16nm node. He has published over 70 technical papers, on a wide range of topics.  Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP.  He has given tutorials and short courses on several subjects at conferences and universities worldwide. He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and serves on a number of conference and workshop committees.

Chair:
Praveen Raghavan, IMEC, BE

Summary

As FET devices scale toward ~10 nm gate lengths, the discreteness of matter and the particular arrangement of individual atoms in each device result in increased time-zero variability. Moreover, degradation mechanisms, such as TDDB and BTI, can be traced to as-fabricated and generated defects in the gate oxide. Since literally only a handful of defects will be present in each deeply scaled device, while the behavior of these defects is typically stochastic, voltage and temperature dependent, and widely distributed in time, each device will be behaving differently during operation, resulting in additional, time-dependent variability. We will argue that reliability and time-dependent variability of future deeply scaled devices can be understood from the perspective of individual defects. We will discuss the basic physical properties of individual defects. Finally, we will show how these properties can be described statistically, combined with actual workloads and propagated to higher design abstraction levels to project device and circuit lifetime distributions.

About the Speaker

Ben Kaczer is a Principal Scientist at imec, Belgium.  He received the M.S. degree in Physical Electronics from Charles University, Prague, in 1992 and the M.S. and Ph.D. degrees in Physics from The Ohio State University, in 1996 and 1998, respectively.   In 1998 he joined the reliability group of imec.  He has co-authored more than 350 journal and conference papers and 2 patents, presented a number of invited papers and tutorials, and received 5 IEEE IRPS Best and Outstanding Paper Awards, 2 IEEE IPFA Best Paper Awards, and the 2011 IEEE EDS Paul Rappaport Award. He has served or is serving at various functions at the IEDM, IRPS, SISC, INFOS, and WoDiM conferences.  He is currently serving on the IEEE T. Electron Dev. Editorial Board.

Overview

In the analog circuit design domain Spice simulators are the most commonly used tools for design exploration and verification.
Consequentially an integration of add-on models for aging effects like BTI and HCI using one of several available interfaces is
considered a straightforward enhancement allowing to address reliability analysis and verification. This talk will give an outline of all the not-so-straightforward challenges arising from the integration and deployment of complex aging models in the harsh environmental conditions of state-of-the-art EDA tool ecosystems.

About the Speaker

Peter Rotter was born in Germany in 1965. He received the diploma degree in physics from the University of Regensburg in Germany in 1994, followed by a Ph.D. degree from the same institute in 1997.

In 1998 he joined the central CAD department of the Infineon Technologies AG. In the section responsible for Infineon's Full Custom Design Flow development he worked over the years on various analog topics, like Spice simulator integration, PDK interfaces, post-layout simulation, analog model validation, statistical simulation, design for yield, design for reliability, general analog automation and analog sign-off methodology.

He current holds the position of a Senior Specialist Analog Sign-Off Methodology.

The research interests of Peter Rotter include analog and reliability verification, analog design automation and sign-off methodologies.

He has participated in various EU and national funded projects like Verona, Syena, Rely, Morv and Resist with a continuously strong interest in strengthening the collaboration of industry and academia.

Summary

Traditionally, aging of ICs was investigated by reliability departments and resulted in an overall guardband factor which needed to be considered during IC design. This approach is increasingly less appropriate. Transistor-level aging models, however, are not suitable for analyzing large circuits. Therefore, gate level timing models incorporating aging have been developed. We will show aging information can be abstracted further from gate to RT level - without loss of accuracy. We will also discuss how such RT level timing models can be employed to monitor the aging of digital circuits during their operation.

About the Speaker

Ulf Schlichtmann spent about 10 years in the semiconductor industry (Siemens, Infineon), in various engineering, management and executive positions. Among other assignments, he was responsible for Infineon's design libraries worldwide, managing about 125 engineers in Munich, Sophia Antipolis, San Jose and Singapore. In 2003, he joined TUM as head of the Institute for Electronic Design Automation. From 2007-2013 he served as Dean and Vice Dean of TUM's Department of Electrical and Computer Engineering.
His research focuses on algorithms for the efficient design of electronic circuits and systems. Abstraction levels from the transistor up to the system level are addressed. In recent years, he has put emphasis especially on the analysis and optimization of circuits and systems for reliability and resilience, with cross-layer techniques increasingly gaining in importance.

Panelists:
Ronald Newhart, IBM, US
Riccardo Mariani, YOGITECH SpA, IT
Tiberiu Seceleanu, ABB, SE

Permanent failures (EM, DB), Aging Failures (HCI, xBTI) and intermittent failures (radiation effects) are all serious threats to the reliable operation of integrated circuits. Which class of failures poses the most serious threat to today's large integrated circuits when they are deployed in the field? Pick one and defend your position. Please bring as much quantitative data as possible to defend your position.

Chair:
Dimitris Gizopoulos, University of Athens, Department of Informatics & Telecommunications, GR

Final remarks to thank the speakers, organizers and participants.

Discussion of plans for future sessions of the workshop.