M06 Design solutions: Modern clocking strategies

Chair:
Luciano Lavagno, Politecnico di Torino, IT

The session includes two lectures. The first one will cover the basics of clock synthesis and present techniques and design styles for high-performance, variation tolerant clock structures. The second lecture will overview the state-of-the-art of asynchronous timing.

One of the main challenges for clock synthesis is dealing with chip variability. With the decreasing dimensions and lower voltages used by new generations of CMOS technology, global and local variations are becoming more and more important. Clock synthesis needs to take variation tolerance into account, to mitigate the impact of these variations.

Mainstream methods for clock tree synthesis typically work by building an initial clock structure in a bottom-up fashion, and then optimizing this structure to improve insertion delay, skew, power and area. These methods can consider variation tolerance by including techniques such as multi-corner optimization, common path sharing and balancing of cell and wire delays. For the global distribution of high-frequency clocks, a different approach is commonly used, which is based on using clock structures that are robust by construction, such as H-trees and clock meshes. Multisource clock synthesis combines these approaches, to support a range of clock structures that provide good trade-offs between robustness, power and area.

In this lecture we will first explain the basics of clock synthesis and timing closure for synchronous circuits, and then describe in more detail techniques and design styles for high-performance, variation tolerant clock structures.

Can we coordinate circuits in time without clock? The answer is yes, if we use asynchronous circuits. These circuits, also called self-timed circuits, do not rely on a global clock signal and operate using local synchronization mechanisms such as handshakes. This makes them very different from widely adopted synchronous circuits and promises many benefits, such as inherent resilience to process, voltage, temperature and aging variations, average rather than worst-case operation in time and power domains, and better modularity and compositionality. For example, asynchronous timing enables robust operation at near-threshold or sub-threshold voltages (NTV and STV), where the optimum point for energy-per-operation lies for many types of logic and memory. This capability allows asynchronous timing to fit ideally for systems powered by energy harvesting, e.g. Internet-of-Things nodes. Despite these benefits, asynchronous timing is not yet widely adopted by industry, mainly because of the difficulties of integrating it into the standard EDA tool flows.

In this lecture we will provide a brief overview of the state-of-the-art of asynchronous timing. We will focus on its two main design paradigms, bundled data and delay-insensitive circuits, and compare their gains and penalties. We will demonstrate existing asynchronous tool support for both paradigms. We will also highlight recent success stories, in particular, industrially adopted design flow for "little digital" hardware components - asynchronous circuits providing flexible timing for analog/mixed-signal circuits such a power converters and AD converters. Finally, we will discuss how these tools can be used for the design of elastic data-flow pipelines, as well as fully self-timed SRAMs, which allows creating systems where processors and memory can seamlessly operate at NVT/SVT. We will conclude by posing future research and development challenges that are currently on the agenda of the asynchronous community.

Chair:
Luciano Lavagno, Politecnico di Torino, IT

The session includes two lectures. The first one will cover synchronization schemes for clock domain crossing. The second lecture will present various advanced techniques for adaptive clocking.

Multiple-clock system-on-chip (SOC) designs require synchronization when transferring signals and data among clock domains and when receiving asynchronous inputs. Such synchronizations are often susceptible to metastability effects that may propagate into the receiving circuit and may cause malfunctions. To mitigate the nondeterministic effects associated with metastability, latches and flip-flops are often used to synchronize the data. Common structures for this purpose include pipelined flip-flops and FIFOs. There is, however, a probability that these circuits will not resolve from a metastable state within the allowed time. The probabilities are becoming a concern as technology nodes get smaller and as the intrinsic parameters of the devices become increasingly variable and problematic; scaling does not help us, anymore!

For multiple-clock SOC designs it is important to understand how synchronizer circuits may fail, and to be able to design reliability as measured by a particular allowable probability of failure, or level of failures in time (FIT). This lecture will present some common synchronization structures, where they may be used and how to evaluate their reliability for both an individual synchronizer and for a system with many synchronizers. Parameters that govern synchronizer reliability are contained in the process transistor-model and in the application of the synchronizer. These two different sources of parameters often involve two different designers and who may work in two different companies. Methods to unite these sources will be discussed.

Some of the latest research in this area will be presented along with models, examples of "good" synchronizer circuits and a discussion of why data flip-flops make terrible synchronizing devices.

Clock frequency is one of the most important parameters in system design and typically is a pre-defined target before synthesis. The time uncertainties in nanoelectronics circuits due to process, voltage, temperature and aging (PVTA) variations demand safe guardband margins that result in conservative clock frequencies. These margins imply a high cost in energy and performance.

In the last few years, several techniques for adaptive clocking have emerged with the aim of dynamically adapting the frequency of the clock to the dynamic variations (VTA) of the system. These techniques may contribute to reduce energy consumption up to 40%. Among all the sources of variations, the most challenging problem is the safe adaptation to voltage droops. This lecture will review some of the most recent advances in adaptive clocking.

Few companies have proposed different schemes based on anticipating voltage droops and quickly adapting the clock frequency to the delays of the system while the droop is active. Various approaches around this idea will be presented and discussed. Techniques based on resilient circuits proposed by ARM and Intel will be also covered. These techniques are based on pushing clock frequency to the limits in a way that timing errors may be detected and corrected at runtime. These techniques require sophisticated mechanisms for error detection/correction not always available in conventional systems.

Finally, a technique based on substituting the PLL by a ring oscillator will be presented. The design and power/performance benefits of this technique will be analyzed.