Date: Thursday 17 March 2016
Time: 08:30 - 10:00
Location / Room: Konferenz 1
Chair:
Geoff Merrett, University of Southampton, GB
Co-Chair:
Stephan Diestelhorst, ARM, US
This session presents various inrustrial relevant experiences on automotive electronics, industrial automation, sensor fusions, energy efficient design, and reliability in advanced process nodes.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 9.3.1 | CHALLENGES OF USING ON-CHIP PERFORMANCE MONITORS FOR PROCESS AND ENVIRONMENTAL VARIATION COMPENSATION Speaker: Mahroo Zandrahimi, Delft University of Technology, NL Authors: Mahroo Zandrahimi1, Zaid Al-Ars1, Philippe Debaud2 and Armand Castillejo2 1Delft University of Technology, NL; 2STMicroelectronics, FR Abstract Circuit monitoring techniques have been adopted widely to compensate for process, voltage, and temperature variations as well as power optimization of integrated circuits. For cost and complexity reasons, these techniques are usually implemented by means of performance monitors allowing fast performance evaluation during production. In this paper, we demonstrate the limitations of performance monitoring methodologies in terms of accuracy and effectiveness. Silicon measurements of a nanometric FD-SOI device show that the required design margin is above 10% of the clock cycle, which leads to unacceptable waste of power. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 08:45 | 9.3.2 | STUDY OF WORKLOAD IMPACT ON BTI HCI INDUCED AGING OF DIGITAL CIRCUITS Speaker: Ajith Sivadasan, ST Microelectronics and TIMA, FR Authors: Ajith Sivadasan1, Florian Cacho2, Sidi-Ahmed Benhassain1, Vincent Huard2 and Lorena Anghel3 1ST Microelectronics and TIMA, FR; 2STMicroelectronics, FR; 3TIMA, FR Abstract Workload characterization of digital circuits using industry standard benchmarks gives an insight into the performance and energy characteristics of processor designs. Aging studies of digital circuits due to BTI, HCI is gaining importance since a higher impact on the performance of circuits can be observed as we scale down gate dimensions. For embedded system applications, the workload may very well dictate the lifetime of a system. This article aims to study the influence of different workloads on the degradation of critical path which determines the reliability of a system. A top-down circuit activity and probability analysis is carried out leading to an accurate estimation of aging due to HCI and BTI of critical path elements at the design stage. A dedicated simulation flow has been set up, from RTL simulation down to gate level cell timing analysis mapped onto 28nm FDSOI technology from STMicroelectronics. The objective is to correlate path delay timing with aging of critical path cells. Simulation results indicate that the higher complexity of an execution program may not necessarily lead to a higher rate of degradation of the critical path considering that aging is primarily driven by the workload dependent activity and the probability of critical path combinational logic elements. Keywords— Workload, Aging, Critical Path, Reliability Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 9.3.3 | FAST PROTOTYPING PLATFORM FOR NAVIGATION SYSTEMS WITH SENSORS FUSION Speaker: Karim Ben Chehida, CEA LIST, FR Authors: Charly Bechara1, Karim Ben Chehida1, Mickael Guibert1, Renaud Schmit1, Maria Lepecq1, Laurent Soulier1, Thomas Dombek1 and Yann Leclerc2 1CEA LIST, FR; 2M3Systems, FR Abstract With the increase demand for robust and precise navigation systems, sensor fusion algorithms have become the only solution exploited that meet the requirements of these systems. However, these algorithms are computation-intensive and require hybrid processing resources. In this paper, we present a unified fast prototyping platform for navigation systems with sensors fusion. The platform is designed based on representative sensor and navigation algorithms requirements analysis and consists of a complete hardware/software framework, as well as FPGA hardware accelerators for the identified compute intensive parts (vision and GNSS). For instance, the hardware point of interest tracker used in vision-based localization algorithms accelerates the performance by 10 with respect to the software implementation. The prototyping platform can be used by algorithms designers to implement and test rapidly their sensor fusion algorithms. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:15 | 9.3.4 | PRECISION TIMED INDUSTRIAL AUTOMATION SYSTEMS Speaker: Partha Roop, University of Auckland, NZ Authors: Matthew Kuo, Sidharta Andalam and Partha Roop, University of Auckland, NZ Abstract For Programmable Logic Controllers (PLCs) that implement safety-critical industrial automation systems, timing correctness is as important as its functional correctness. Modern PLCs employ run-time environments and/or general purpose processors designed by ARM, Intel and Freescale to implement real-time systems. However, general purpose processors are designed to improve the average case performance and ignore the worst case performance. This makes it nearly impossible to guarantee the timing correctness of safety-critical applications. In this paper, we apply the recently developed PRET philosophy to propose Precision Timed Industrial Automation (PTIA) Systems for the design of precision timed industrial automation systems. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 9.3.5 | AUTOSAR-BASED COMMUNICATION COPROCESSOR FOR AUTOMOTIVE ECUS Speaker: Ahmed Hamed, Mentor Graphics Corporation, EG Authors: Ahmed Hamed1, Mona Safar2, M. Watheq El-Kharashi2 and Ashraf Salem1 1Mentor Graphics Corporation, EG; 2Ain Shams University, EG Abstract In this paper, we present a novel approach to enhance the performance of the AUTOSAR-based Electronic Control Units. The execution time consumed by main functions, called from the application used in an Engine Control Management AUTOSAR-based Electronic Control Unit, has been analyzed. The analysis shows that the operations done by the AUTOSAR communication module are the most Electronic Control Unit time-consuming operations. Our approach modifies the design model of the AUTOSAR Layered Software Architecture by adding the communication coprocessor component. This model-based hardware/software codesign expedites the AUTOSAR communication operations while keeping the interfaces with the upper and lower layers unchanged. The coprocessor covers two communication-based operations. It consists of six building blocks. It communicates with the original Electronic Control Unit through the External Peripheral Interface module, which is a high speed parallel bus for external peripherals. The implemented coprocessor achieves up to 140x speedup over the software communication module solution. This gives a room to extend the automotive applications and increase the amount of the exchanged information by these applications without affecting the performance. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:45 | 9.3.6 | MANTISSA-MASKING FOR ENERGY-EFFICIENT FLOATING-POINT LTE UPLINK MIMO BASEBAND PROCESSING Speaker: Tomas Henriksson, Huawei Sweden, SE Authors: Daniel Guenther1, Tomas Henriksson2, Rainer Leupers1 and Gerd Ascheid1 1RWTH Aachen University, DE; 2Huawei, Sweden, SE Abstract The increasingly diverse wireless communication ecosystem has given rise to flexible, programmable platforms for wireless baseband processing. This industry case study presents advance development results of a fully programmable, flexible floating-point DSP architecture for uplink (UL) multiple-input, multiple-output (MIMO) baseband processing with runtime-adaptive precision. By tuning the floating-point precision to the application needs, energy consumption can be reduced by up to 23 % per task. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area |