Date: Wednesday 16 March 2016
Time: 08:30 - 10:00
Location / Room: Konferenz 4
Chair:
Gunar Schirner, Northeastern University, US
Co-Chair:
Christian Haubelt, University of Rostock, DE
SystemC has become an important tool to enable system-level modeling and simulation for early concept validation, design space exploration and virtual prototyping. However, the predominant single-threaded discrete event kernels used for its simulation limit efficiency and applicability in modeling of large systems. This session features two research papers that explore different techniques for speeding up simulation by means of parallelizing the kernel and by exploiting properties of the time-decoupled modeling approach. The third paper investigates a new modeling technique and SystemC extension to enable fast and accurate simulation of analog/mixed signal systems.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 5.6.1 | A NEW PARALLEL SYSTEMC KERNEL LEVERAGING MANYCORE ARCHITECTURES Speaker: Nicolas Ventroux, CEA LIST, FR Authors: Nicolas Ventroux and Tanguy Sassolas, CEA LIST, FR Abstract The complexity of system-level modeling is continuously increasing. Electronic System Level (ESL) design requires fast simulation techniques to control future SoC development cost and time-to-market. However, SystemC simulations are sequential and then limited by single-thread performance. In this paper, we present a new parallel SystemC kernel that efficiently leverages the multiple cores of a host machine, reaching high simulation performance without relaxing accuracy. It supports atomic parallel evaluation of SystemC processes and repeatable execution for HW/SW debugging. This new kernel is fully compliant with existing standards and easy to integrate in any existing SystemC model. Evaluations show a maximum acceleration of 34x compared to Accellera SystemC on a 64-core AMD Opteron machine. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 5.6.2 | SYSTEMC-LINK: PARALLEL SYSTEMC SIMULATION USING TIME-DECOUPLED SEGMENTS Speaker: Jan Henrik Weinstock, RWTH Aachen University, DE Authors: Jan Henrik Weinstock1, Rainer Leupers1, Gerd Ascheid1, Dietmar Petras2 and Andreas Hoffmann2 1RWTH Aachen University, DE; 2Synopsys GmbH, DE Abstract Virtual platforms have become essential tools in the design process of modern embedded systems. Their accessibility and early availability make them ideal tools for design space exploration and debugging of target specific software. However, due to increasing platform complexity and the need to simulate more and more processors simultaneously, performance of virtual platforms degrades rapidly. This work presents SystemC-Link, a segment based parallel simulation framework for SystemC simulators. It achieves high simulation performance by using a parallel and time-decoupled simulation approach. Furthermore, it offers a virtual sequential environment for each simulation segment. This enables use of legacy models by allowing operation on global state without risking race conditions during parallel simulation. The approach is evaluated in a variety of scenarios, including a contemporary multi-core platform based on the OpenRISC architecture running Linux. For this benchmark, a 3.2x higher simulation performance was achieved with SystemC-Link compared to standard SystemC on a regular workstation PC. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 5.6.3 | ORTHOGONAL SIGNAL MODELING AND OPERATIONAL COMPUTATION OF AMS CIRCUITS FOR FAST AND ACCURATE SYSTEM SIMULATION Speaker: Leandro Gil, University of Stuttgart, DE Authors: Leandro Gil and Martin Radetzki, University of Stuttgart, DE Abstract We present a general mathematical model of signals for efficient and accurate simulation of analog and mixed signal (AMS) systems. It relies on signal coding and parameterization and allows heterogeneous system specification at different abstraction levels, as well as, the operational computation of continuous time systems' dynamical behavior. In particular, we derive a matrix for operational subdivision of continuous signals and use it to capture accurately the interaction between continuous and discrete time systems. A key advantage of this signal representation is that continuous signal monitoring and analysis can be performed more efficiently, speeding up system verification. We implemented the proposed modeling approach in SystemC AMS 2.0 to exploit the dynamic reactive behavior of TDF MoC for accurate synchronization between the digital and analog system parts. With the example of a PLL system we evaluate the capabilities of our implementation to cope with heterogeneous designs at different design abstraction levels. The experimental results show a significant simulation speedup for high accurate models. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | IP2-10, 609 | EFFICIENT MONITORING OF LOOSE-ORDERING PROPERTIES FOR SYSTEMC TLM Speaker: Yuliia Romenska, Univ. Grenoble Alpes, VERIMAG, FR Authors: Yuliia Romenska1 and Florence Maraninchi2 1Univ. Grenoble Alpes, VERIMAG, FR; 2Grenoble INP & Verimag, FR Abstract SystemC Transaction-level modeling (TLM) provides high-level component-based models for SoCs, for which Assertion-Based-Verification (ABV) allows property checking early in the design cycle. We introduce the notion of loose-ordering to specify when components interact with each other and we propose a set of patterns to capture this notion in assertions. This new notion can already be expressed in languages like PSL, for which there exist tools to generate ABV monitors. But the definition of dedicated patterns makes it easier to write the properties. Moreover we define a direct translation of these patterns into SystemC monitors, and we show that it avoids the combinatorial explosion that would occur during a prior translation into PSL. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area |