Date: Wednesday 16 March 2016
Time: 08:30 - 10:00
Location / Room: Konferenz 3
Chair:
Yiyu Shi, University of Notre Dame, US
Co-Chair:
Sébastien Le Beux, Ecole Centrale de Lyon, FR
The approximate nature of neuromorphic / machine learning approaches is explored from several perspectives. Two works focus on modeling techniques and tools for such architectures, while the third leverages approximate metrics of classification difficulty to trade between accuracy and classification cost.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 5.5.1 | MNSIM: SIMULATION PLATFORM FOR MEMRISTOR-BASED NEUROMORPHIC COMPUTING SYSTEM Speaker: Lixue Xia, Tsinghua University, CN Authors: Lixue Xia1, Boxun Li1, Tianqi Tang1, Peng Gu2, Xiling Yin1, Wenqin Huangfu1, Pai-Yu Chen3, Shimeng Yu3, Yu Cao3, Yu Wang1, Yuan Xie2 and Huazhong Yang1 1Tsinghua University, CN; 2UC Santa Barbara, US; 3Arizona State University, US Abstract Memristor-based neuromorphic computing system provides a promising solution to significantly boost the power efficiency of computing system. Memristor-based neuromorphic computing system has a wide range of design choices, such as the various memristor crossbar cell designs and different parallelism degrees of peripheral circuits. However,a memristor-based neuromorphic computing system simulator, which is able to model the system and realize an early-stage design space exploration, is still missing. In this paper, we develop a memristor- based neuromorphic system simulation platform (MNSIM). MNSIM proposes a general hierarchical structure for memristor-based neuro- mophic computing system, and provides flexible interface for users to customize the design. MNSIM also provides a detailed reference design for large-scale applications. MNSIM embeds estimation models of area, power, and latency to simulate the performance of system. To estimate the computing accuracy of memristor crossbar, MNSIM proposes a behavior-level model between computing error rate and crossbar design parameters considering the influence of interconnect lines and non- ideal device factors. The error rate between our accuracy model and SPICE simulation result is less than 1%. Experimental results show that MNSIM achieves more than 7000 times speed-up compared with SPICE and obtains reasonable accuracy (more than 90%). MNSIM can further estimate the trade-off between computing accuracy, energy, latency, and area among different designs for optimization. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 5.5.2 | CONDITIONAL DEEP LEARNING FOR ENERGY-EFFICIENT AND ENHANCED PATTERN RECOGNITION Speaker: Priyadarshini Panda, Purdue University, US Authors: Priyadarshini Panda, Abhronil Sengupta and Kaushik Roy, Purdue University, US Abstract Deep learning neural networks have emerged as one of the most powerful classification tools for vision related applications. However, the computational and energy requirements associated with such deep nets can be quite high, and hence their energy-efficient implementation is of great interest. Although traditionally the entire network is utilized for the recognition of all inputs, we observe that the classification difficulty varies widely across inputs in real-world datasets; only a small fraction of inputs require the full computational effort of a network, while a large majority can be classified correctly with very low effort. In this paper, we propose Conditional Deep Learning (CDL) where the convolutional layer features are used to identify the variability in the difficulty of input instances and conditionally activate the deeper layers of the network. We achieve this by cascading a linear network of output neurons for each convolutional layer and monitoring the output of the linear network to decide whether classification can be terminated at the current stage or not. The proposed methodology thus enables the network to dynamically adjust the computational effort depending upon the difficulty of the input data while maintaining competitive classification accuracy. We evaluate our approach on the MNIST dataset. Our experiments demonstrate that our proposed CDL yields 1.91x reduction in average number of operations per input, which translates to 1.84x improvement in energy. In addition, our results show an improvement in classification accuracy from 97.5% to 98.9% as compared to the original network. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 5.5.3 | PROBABILISTIC ERROR MODELS FOR MACHINE LEARNING KERNELS IMPLEMENTED ON STOCHASTIC NANOSCALE FABRICS Speaker: Sai Zhang, University of Illinois at Urbana-Champaign, US Authors: Sai Zhang and Naresh Shanbhag, University of Illinois at Urbana-Champaign, US Abstract Presented in this paper are probabilistic error models for machine learning kernels implemented on low-SNR circuit fabrics where errors arise due to voltage overscaling (VOS), process variations, or defects. Four different variants of the additive error model are proposed that describe the error probability mass function (PMF): additive over Reals Error Model with independent Bernoulli RVs (REM-i), additive over Reals Error Model with joint Bernoulli RVs (REM-j), additive over Galois field Error Model with independent Bernoulli RVs (GEM-i), and additive over Galois field Error Model with joint Bernoulli RVs (GEM-j). Analytical expressions for the error PMF, mean and variance are derived. Kernel level model validation is accomplished by comparing the Jensen-Shannon divergence D_{JS} between the modeled PMF and the PMFs obtained via HDL simulations in a commercial 45nm CMOS process of MAC units used in a 2nd order polynomial support vector machine (SVM) to classify data from the UCI machine learning repository. Results indicate that at the MAC unit level, D_{JS} for the GEM-j models are 1-to-2-orders-of-magnitude lower (better) than the REM models for VOS and process variation errors. However, when considering errors due to defects, D_{JS} for REM-j is between 1-to-2-orders-of-magnitude lower than the others. Performance prediction of the SVM using these models indicate that when compared with Monte Carlo with HDL generated error statistics, probability of detection p_{det} estimated using GEM-j is within 3% for VOS error when the error rate <= 80%, and within 5% for process variation error when supply voltage V_{dd} is between 0.3V and 0.7V. In addition, p_{det} using REM-j is within 2% for defect errors when the defect rate (the percentage of circuit nets subject to stuck-at-faults) p_{saf} is between 10^{-3} and 0.2. . Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | IP2-9, 173 | EFFICIENT GLOBAL OPTIMIZATION OF MEMS BASED ON SURROGATE MODEL ASSISTED EVOLUTIONARY ALGORITHM Speaker: Bo Liu, Glyndwr University, GB Authors: Bo Liu1 and Anna Nikolaeva2 1Glyndwr University, GB; 2Bauman Moscow State Technical University, RU Abstract Optimization plays a key role in MEMS design. However, most MEMS design optimization (exploration) methods either depend on ad-hoc analytical / behavioural models or time consuming numerical simulations. Surrogate modeling techniques have been introduced to integrate generality and efficiency, but the number of design variables which can be handled by most existing efficient MEMS design optimization methods is often less than 5. To address the above challenges, a new method, called Adaptive Gaussian Process-Assisted Differential Evolution for MEMS Design Optimization (AGDEMO) is proposed. The key idea is the proposed ON-LINE adaptive surrogate model assisted optimization framework. In particular, AGDEMO performs global optimization of MEMS using numerical simulation and the differential evolution (DE) algorithm, and a Gaussian process surrogate model is constructed ON-LINE to predict the results of expensive numerical simulations. AGDEMO is tested by two actuators (both with 9 design variables). Comparisons with state-of-the-art methods verify advantages of AGDEMO in terms of efficiency, optimization capacity and scalability. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area |