Date: Thursday 17 March 2016
Time: 16:00 - 17:30
Location / Room: Konferenz 6
Organiser:
Michael Niemier, University of Notre Dame, South Bend, US
Chair:
Sri Parameswaran, The University of New South Wales, AU
Like performance, power, and reliability, security is becoming a critical design consideration. As a representative example, hardware security threats in the integrated circuit (IC) supply chain, including hardware counterfeiting, IP piracy, and reverse engineering cost the US economy more than $200 billion annually. Problems are further exacerbated by the rapid growth in the "Internet of Things" (IoT). This session will highlight how emerging transistor technologies can enhance existing hardware security primitives, and also lead to new hardware security primitives. We begin by addressing security threats that are enabled by insecure hardware. A special emphasis will be placed on the need for standards to address hardware security across all aspects of the supply chain. We then highlight how emerging transistor technologies could impact encryption engines. We consider not only how new devices could lead to more sophisticated/robust encryption ciphers in resource constrained environments, but also how new devices may make said ciphers more resilient to attacks such as differential power analysis (DPA). We conclude with a discussion of how unique I-V characteristics offered by beyond CMOS transistors can enable new hardware security primitives that could facilitate IC supply chain protection, help prevent/stop sidechannel attacks, etc.. Presently, most emerging technologies being studied in the context of hardware security are related to designing physically unclonable functions (PUFs) and random number generators (RNGs). However, most PUF and RNG designs leverage larger device-to-device variations in emerging technologies. Ironically, said variations often represent shortcomings when viewed through the lens of an original device target - i.e., reliable digital logic or memory. In contrast, we will discuss emerging transistor technologies for hardware security related applications that are not RNGs or PUFs, and do not inherently rely on device variations as a means to an end. This session will provide important insight into the following questions: Can new devices lead to more efficient hardware primitives than CMOS in countering hardware attacks? What properties should an emerging technology-based hardware infrastructure provide to better support software level protection schemes? Can such properties be reliably demonstrated by a given device? This session is especially timely as the 2015 International Technology Roadmap for Semiconductors (ITRS) chapter on Emerging Research Devices (ERD) will include the first section on how new devices might be employed to enhance hardware security. As such, the time has come to engage the design automation community in this new and important research vector.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 16:00 | 12.2.1 | MITIGATING HARDWARE THREATS TO ENABLE THE INTERNET OF SECURE THINGS Speaker: Yaw Obeng, National Institute of Standards and Technology, US Authors: Yaw Obeng1, Colm Nolan2 and David Brown3 1National Institute of Standards and Technology, US; 2IBM, IE; 3Intel Corporation, US Abstract This paper examines the current issues pertaining to the hardware security and how they could affect the overall security of applications such as the internet of things. Specifically, we review the ongoing industry-led activities aimed at mitigating the hardware threats through supply chain assurance. The impact of emerging technologies on hardware- based needs, and the need for technical standards are discussed from brand owners' perspectives. The paper is illustrated with the ongoing work of the International Technology Roadmap for Semiconductors (ITRS) Emerging Research Devices (ERD) hardware security working group, the counterfeit risk mitigation efforts from iNEMI, and the High-Density Package User Group (HDPUG), as well as published standards from SEMI and the Open Group. All these efforts are aimed at mitigating counterfeits in the electronics supply chain through product traceability and authentication. Finally, we will discuss how existing and emerging technologies can be used for product authentication throughout the supply chain. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:30 | 12.2.2 | LEVERAGE EMERGING TECHNOLOGIES FOR DPA-RESILIENT BLOCK CIPHER DESIGN Speaker: Michael Niemier, University of Notre Dame, US Authors: Yu Bi1, Kaveh Shamsi1, Jiann-Shiun Yuan1, Francois-Xavier Standaert2 and Yier Jin1 1University of Central Florida, US; 2Université Catholique de Louvain, BE Abstract Emerging devices have been designed and fabricated to extend Moore's Law. While the benefits over traditional metrics such as power, energy, delay, and area certainly apply to emerging device technologies, new devices may offer additional benefits in addition to improvements in the aforementioned metrics. In this sense, we consider how new transistor technologies could also have a positive impact on hardware security. More specifically, we consider how tunneling FETs (TFET) and silicon nanowire FETs (SiNW FETs) could offer superior protection to integrated circuits and embedded systems that are subject to hardware-level attacks -- e.g., differential power analysis (DPA). Experimental results on SiNW FET and TFET CML gates are presented. In addition, simulation results of utilizing TFET CML on a light-weight cryptographic circuit, KATAN32, show that TFET-based current mode logic (CML) can both improve DPA resilience and preserve low power consumption in the target design. Compared to the CMOS-based CML designs, the TFET CML circuit consumes 15 times less power while achieving a similar level of DPA resistance. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:00 | 12.2.3 | USING EMERGING TECHNOLOGIES FOR HARDWARE SECURITY BEYOND PUFS Speaker: X. Sharon Hu, University of Notre Dame, US Authors: An Chen1, X. Sharon Hu2, Yier Jin3, Michael Niemier2 and Xunzhao Yin2 1ITRS ERD working group chair, US; 2University of Notre Dame, US; 3University of Central Florida, US Abstract We discuss how the unique I-V characteristics offered by emerging, post-CMOS transistors can be used to enhance hardware security. Different from most existing work that exploits emerging technologies for hardware security, we (i) focus on transistor characteristics that either do not exist in, or are difficult to duplicate with MOSFETs, and (ii) aim to move beyond hardware implementations of physically unclonable functions (PUFs) and random number generators (RNGs). Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | End of session | |