Date: Thursday 17 March 2016
Time: 11:00 - 12:30
Location / Room: Konferenz 2
Chair:
Ibhraim Elfadel, Masdar Institute of Technology, AE
Co-Chair:
L. Miguel Silveira, INESC-ID, IST, U Lisboa, PT
Stochastic methods are continuing to play a fundamental role in circuit analysis and synthesis in order to handle both the growing complexity of integrated circuits as well as the effects of process variations. The first paper combines a Markov Chain Monte Carlo method with a Floating Random Walk method in order to speed up capacitance extraction and handle circuits containing IP protected substructures. The second paper builds a parameterized surrogate model of node voltages in power grids which can be used for efficient evaluation of multiple variation settings. The third paper uses an iterative variation-aware circuit synthesis flow to improve performance and energy efficiency.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 10.4.1 | (Best Paper Award Candidate) UTILIZING MACROMODELS IN FLOATING RANDOM WALK BASED CAPACITANCE EXTRACTION Speaker: Wenjian Yu, Tsinghua University, CN Authors: Wenjian Yu1, Bolong Zhang1, Chao Zhang1, Haiquan Wang1 and Luca Daniel2 1Tsinghua University, CN; 2Massachusetts Institute of Technology (MIT), US Abstract This paper presents techniques that use macromodels in order to extend and improve the floating random walk (FRW) method for capacitance extraction. A macromodel is built for each sub-structure for which it is necessary or convenient to hide its geometry details during capacitance extraction. Then, a macromodel-aware random walk scheme connects the Markov-chain random walk inside the macromodels and the FRW outside through scalable blank patch regions. This method can be used for instance to extract capacitances for structure with encrypted sub-structures, and extend the FRW method's capability for structure with complex geometry or repeated layout patterns. Numerical results validate the merits of the proposed method with structures including encrypted FinFET layout, complex geometry features, and cyclic layout patterns. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 11:30 | 10.4.2 | VARIABILITY AND STATISTICAL ANALYSIS FLOW FOR DYNAMIC LINEAR SYSTEMS WITH LARGE NUMBER OF INPUTS Speaker: L. Miguel Silveira, INESC-ID, Instituto Superior Técnico, PT Authors: António Lucas Martins1, Jorge Fernandez Villena2 and L. Miguel Silveira1 1INESC-ID, Instituto Superior Técnico, PT; 2Cadence Design Systems, DE Abstract Fast analysis of the dynamics of large linear systems with large number of inputs, such as power grid (PG) nets, is a required component of system verification platforms. Such analysis, exhibiting a considerable memory footprint and requiring intensive computations and advanced numerical techniques, has been the framework of recent approaches. However analyzing the effect of design variability, which can have a critical impact on the power distribution across the chip, especially when considering its dynamic performance, poses a unmet challenge. Existing approaches collect information about the voltage and current fluctuations in key nodes that may lead to erroneous behavior or relevant performance changes. This is achieved through repetitive extraction and/or simulation of the large linear RC network for a very broad number of parameter settings. Unfortunately network size and the plethora of different settings that requires investigation implies that such an approach can be exceedingly time consuming, even if parallel architectures are used. In order to address such a challenge, this paper introduces an alternative analysis flow that builds a parameterized model of the time domain node voltages on the fly, using the nominal time domain simulation as starting point. Once such model is generated, the effect of variability in the time response can be efficiently evaluated for multiple settings, allowing collection of relevant variation and statistic information of the impact of a large number of parameters in the current design. The performance of the methodology is evaluated on an set of standard PG extracted netlists, showing large improvements in terms of speed with modest memory requirements while maintaining an acceptable degree of accuracy. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:00 | 10.4.3 | VARIATION-AWARE NEAR THRESHOLD CIRCUIT SYNTHESIS Speaker: Mohammad Saber Golanbari, Karlsruhe Institute of Technology (KIT), DE Authors: Mohammad Saber Golanbari, Saman Kiamehr, Mojtaba Ebrahimi and Mehdi Tahoori, Karlsruhe Institute of Technology (KIT), DE Abstract Near-Threshold Computing (NTC) is shown to be a promising approach for improving the energy efficiency of VLSI circuits. Nevertheless, by reducing the supply voltage the delay impact of process variation significantly increases, leading to up to 20x performance variation compared to the nominal voltage. As a result, it is wasteful of energy and performance to deal with such variation by increasing the timing margins, which is common in nominal voltage. Therefore, considering the impact of process variation during the near-threshold circuit design phase is of decisive importance. In this paper, we propose a variation-aware synthesis flow for NTC to address this problem. The objective is to improve the performance and energy efficiency of a circuit during design time by considering statistical variation information. This is done by providing variation information to the synthesis tool, evaluating the performance of the synthesized circuit by Statistical Static Timing Analysis (SSTA), and adjusting the timing constraints accordingly in an iterative manner. Simulation results for a set of benchmark circuits show that our proposed flow reduces the variation by 86.6% and improves the performance and energy by 24.9% and 7.4%, respectively, at the expense of 4.8% area overhead. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | End of session Lunch Break in Großer Saal + Saal 1 Keynote Lecture in "Saal 2" 13:30 - 14:00 |