Chair:
Lukas Sekanina, Brno University of Technology, CZ

Chair:
Andy M. Tyrrell, University of York, GB

Organiser:
Marilyn Wolf, Georgia Institute of Technology, US

Application areas: industrial, home, medical, energy, automotive, sensors/actuators, industrial control systems. Key characteristics of IoT system architectures for these applications: edge/cloud system architectures, heterogeneous networking, energy management. Design automation challenges for IoT systems, covering energy management, networking, security, and IoT system design.

Organiser:
Dimitrios Serpanos, Qatar Computing Research Institute, QA

the characteristics of the types of networks used for IoT: sensor networks, industrial networks, automotive networks, etc. Threat models for IoT, device hardening methods, network hardening methods. Integrated approaches for IoT security and fault tolerance

Organiser:
Saibal Mukhopadhyay, Georgia Institute of Technology, US

Energy harvesting. Ultra low power digital comptuation using adaptive circuits. Low-power neuromorphic computing. Low-power mixed signal computation and image sensors. Low power and security.

Organiser:
Marilyn Wolf, Georgia Institute of Technology, US

IoT systems as key-value streams. Allocation of computation and networking in IoT networks. Run-time management of IoT networks.

Chair:
Luciano Lavagno, Politecnico di Torino, IT

The session includes two lectures. The first one will cover the basics of clock synthesis and present techniques and design styles for high-performance, variation tolerant clock structures. The second lecture will overview the state-of-the-art of asynchronous timing.

One of the main challenges for clock synthesis is dealing with chip variability. With the decreasing dimensions and lower voltages used by new generations of CMOS technology, global and local variations are becoming more and more important. Clock synthesis needs to take variation tolerance into account, to mitigate the impact of these variations.

Mainstream methods for clock tree synthesis typically work by building an initial clock structure in a bottom-up fashion, and then optimizing this structure to improve insertion delay, skew, power and area. These methods can consider variation tolerance by including techniques such as multi-corner optimization, common path sharing and balancing of cell and wire delays. For the global distribution of high-frequency clocks, a different approach is commonly used, which is based on using clock structures that are robust by construction, such as H-trees and clock meshes. Multisource clock synthesis combines these approaches, to support a range of clock structures that provide good trade-offs between robustness, power and area.

In this lecture we will first explain the basics of clock synthesis and timing closure for synchronous circuits, and then describe in more detail techniques and design styles for high-performance, variation tolerant clock structures.

Can we coordinate circuits in time without clock? The answer is yes, if we use asynchronous circuits. These circuits, also called self-timed circuits, do not rely on a global clock signal and operate using local synchronization mechanisms such as handshakes. This makes them very different from widely adopted synchronous circuits and promises many benefits, such as inherent resilience to process, voltage, temperature and aging variations, average rather than worst-case operation in time and power domains, and better modularity and compositionality. For example, asynchronous timing enables robust operation at near-threshold or sub-threshold voltages (NTV and STV), where the optimum point for energy-per-operation lies for many types of logic and memory. This capability allows asynchronous timing to fit ideally for systems powered by energy harvesting, e.g. Internet-of-Things nodes. Despite these benefits, asynchronous timing is not yet widely adopted by industry, mainly because of the difficulties of integrating it into the standard EDA tool flows.

In this lecture we will provide a brief overview of the state-of-the-art of asynchronous timing. We will focus on its two main design paradigms, bundled data and delay-insensitive circuits, and compare their gains and penalties. We will demonstrate existing asynchronous tool support for both paradigms. We will also highlight recent success stories, in particular, industrially adopted design flow for "little digital" hardware components - asynchronous circuits providing flexible timing for analog/mixed-signal circuits such a power converters and AD converters. Finally, we will discuss how these tools can be used for the design of elastic data-flow pipelines, as well as fully self-timed SRAMs, which allows creating systems where processors and memory can seamlessly operate at NVT/SVT. We will conclude by posing future research and development challenges that are currently on the agenda of the asynchronous community.

Chair:
Luciano Lavagno, Politecnico di Torino, IT

The session includes two lectures. The first one will cover synchronization schemes for clock domain crossing. The second lecture will present various advanced techniques for adaptive clocking.

Multiple-clock system-on-chip (SOC) designs require synchronization when transferring signals and data among clock domains and when receiving asynchronous inputs. Such synchronizations are often susceptible to metastability effects that may propagate into the receiving circuit and may cause malfunctions. To mitigate the nondeterministic effects associated with metastability, latches and flip-flops are often used to synchronize the data. Common structures for this purpose include pipelined flip-flops and FIFOs. There is, however, a probability that these circuits will not resolve from a metastable state within the allowed time. The probabilities are becoming a concern as technology nodes get smaller and as the intrinsic parameters of the devices become increasingly variable and problematic; scaling does not help us, anymore!

For multiple-clock SOC designs it is important to understand how synchronizer circuits may fail, and to be able to design reliability as measured by a particular allowable probability of failure, or level of failures in time (FIT). This lecture will present some common synchronization structures, where they may be used and how to evaluate their reliability for both an individual synchronizer and for a system with many synchronizers. Parameters that govern synchronizer reliability are contained in the process transistor-model and in the application of the synchronizer. These two different sources of parameters often involve two different designers and who may work in two different companies. Methods to unite these sources will be discussed.

Some of the latest research in this area will be presented along with models, examples of "good" synchronizer circuits and a discussion of why data flip-flops make terrible synchronizing devices.

Clock frequency is one of the most important parameters in system design and typically is a pre-defined target before synthesis. The time uncertainties in nanoelectronics circuits due to process, voltage, temperature and aging (PVTA) variations demand safe guardband margins that result in conservative clock frequencies. These margins imply a high cost in energy and performance.

In the last few years, several techniques for adaptive clocking have emerged with the aim of dynamically adapting the frequency of the clock to the dynamic variations (VTA) of the system. These techniques may contribute to reduce energy consumption up to 40%. Among all the sources of variations, the most challenging problem is the safe adaptation to voltage droops. This lecture will review some of the most recent advances in adaptive clocking.

Few companies have proposed different schemes based on anticipating voltage droops and quickly adapting the clock frequency to the delays of the system while the droop is active. Various approaches around this idea will be presented and discussed. Techniques based on resilient circuits proposed by ARM and Intel will be also covered. These techniques are based on pushing clock frequency to the limits in a way that timing errors may be detected and corrected at runtime. These techniques require sophisticated mechanisms for error detection/correction not always available in conventional systems.

Finally, a technique based on substituting the PLL by a ring oscillator will be presented. The design and power/performance benefits of this technique will be analyzed.

Chair:
Enrico Macii, Politecnico di Torino, IT

The first session of this Tutorial includes two lectures. The first one provides an introduction to the IoT systems and the most promising application fields, highlighting the energy-related issues. The second one lists and analyses the general methodologies that can be applied to tackle energy challenges for IoT devices.

Internet of Things applications are becoming a reality in a multitude of fields,e.g., from consumer applications to environmental monitoring, from energy distribution to the so-called "smart factory". Pervasive intelligent and connected systems introduce new functionalities and services, but system design is severely constrained in terms of cost, required security and energy. This lecture describes some IoT applications focusing on the energy aspects, illustrating where most of the power is used and highlighting the main challenges that need to be tackled by the circuit and system designers.

This lecture describes state-of-the-art solutions for energy evaluation and optimization addressing computation, communication and power delivery for the devices involved in IoT applications.

Chair:
Massimo Poncino, Politecnico di Torino, IT

The second session of the Tutorial adopts a more practical approach. The first lecture goes into the details of energy harvesting and conversion, while the second one shows related industrial system development experience.

The IoT paradigm requires a careful choice of energy sources, conversion and storage methodologies, taking into account the specific application that is being developed. This lecture shows some of the available methodologies and provides hints for the design of optimized systems.

From the point of view of system designers, this lecture describes the process that goes from the idea to the implementation of an IoT system, including system-level modeling, the selection of commercially available components (sensors, processing and communications) and optimized system management.

Chair:
Davide Quaglia, EDALab s.r.l., IT

Co-Chair:
Kim Grüttner, OFFIS - Institute for Information Technology, DE

Chair:
Kim Grüttner, OFFIS - Institute for Information Technology, DE

Co-Chair:
Davide Quaglia, EDALab s.r.l., IT

Panelist:
Bill Eklow, Cisco Systems, Inc., US

The introductive part of the tutorial will provide the motivation for board-level fault diagnosis and describe state-of-the-art in industry practice. It will also highlight the difficult problems being faced today that require new solutions. More in details, topics to be covered include:

• Structural and functional tests
• Rationale for board diagnosis and repair
• Review of available EDA tools and commercial solutions (including IEEE standards)
• Why system and ATE tests do not correlate
• Introduction to NTFs and troubleshooting NTFs
• Open problems and call to action.

Panelist:
Luca Cassano, Politecnico di Milano, IT

This part of the tutorial will first introduce the basic concepts of adaptive incremental functional diagnosis (AIFD) and it will discuss the main features that an automated AIFD approach should offer to the test/diagnosis engineer. Then, several machine learning techniques that can be exploited for AIFD will be introduced. More in details, the basic concepts related to the theory and application of the following machine learning techniques would be introduced:

• Decision Trees
• Data Mining
• Bayesian Belief Networks
• Support Vector Machines
• k-Nearest Neighbors
• Artificial Neural Networks

The results of a comparative analysis of the previously presented machine learning techniques applied to AIFD would be shown. Moreover, the three best approaches, i.e., the data mining-, the Bayesian belief network- and the decision trees-based ones, would be presented in details. Finally, a new statistical AIFD approach would be discussed. Results of the application of all the presented approaches to both synthetic and real-world electronic boards would be shown

Panelist:
Krishnendu Chakrabarty, Duke University, US

The accuracy of diagnosis and time needed for diagnosis also depend on the quality of syndromes (erroneous observations). Redundant or irrelevant syndromes not only lead to long diagnosis time, but also increase diagnosis complexity. This last part of the tutorial will review recent advances in enhancing diagnostic accuracy using various means, and include the following topics:

• Information-theoretic measures
• Ranking of syndromes and ambiguity analysis for test-set redesign
• Knowledge discovery and knowledge transfer
• Industry case studies

Chair:
Ilia Polian, University of Passau, DE

Chair:
Tim Güneysu, University of Bremen, DE

Chair:
Nicolas Sklavos, University of Patras, GR

Chair:
Stjepan Picek, Faculty of Electrical Engineering and Computing, HR

Chair:
Giorgio Di Natale, LIRMM, FR

Chair:
Nele Mentens, ESAT/COSIC and iMinds, KU Leuven, BE

Chair:
Nicolas Sklavos, University of Patras, GR

Chair:
Nicolas Sklavos, University of Patras, GR

Organisers:
Ian Harris, University of Californa Irvine, US
Mathias Soeken, Universität Bremen, DE

The life of a computing system arguably begins with architects developing architectural models, and tuning various design parameters for target performance and power consumption. The result of this process is the definition of the high-level architectural specification of the system, which defines the functional requirements for the system design. This specification is used as a guide for most downstream activities, e.g., decompose system functionality, implement various design blocks, perform code reviews, design pre-silicon and post-silicon validation test-benches, define assertions, etc. Unfortunately, architectural specifications are rarely developed with the rigor, discipline, and formality warranted for something used so extensively throughout the system life cycle. System functionality is typically described informally with prose mixed with charts, diagrams, and tables. Furthermore, these descriptions are spread across a large number of different documents, each document several hundreds of pages long and covering different aspects of the design (e.g., functionality, power, security, communication, etc.). Unsurprisingly, these documents contain inconsistencies, ambiguities, even errors. These are often discovered late in the implementation or validation phases or on field, leading to late design churns, complex patches, point-fixes, and de-featuring. The situation is exacerbated in recent years with fast increasing design complexity on the one hand and decreasing time-to-market on the other.

In this talk, we look at the industrial practice in defining design specification, the complexities in making them rigorous, and the impacts of specification ambiguity to design, validation, and production. Specific examples from industrial case studies will be used for demonstration. We look at recent efforts from different affected stake-holders (i.e., architects, designers, implementers, and validators) to converge on requirement descriptions. In spite of these efforts, a significant gap remains between the state of the practice and what is needed to define unambiguous specifications for trustworthy system designs, and we explore the critical research needs in this area.

Bio: Sandip Ray a Research Scientist at Intel's Strategic CAD Labs in Hillsboro, OR, USA. His research focuses on developing correct, dependable, and trustworthy computing systems through a synergy of specification, synthesis, verification, and validation techniques. At Intel, he leads research on development of a trustworthy and robust validation infrastructure for next-generation industrial SoC designs. Before joining Intel, Dr. Ray worked as a Research worked as a Research Scientist at the University of Texas at Austin, where he developed analysis frameworks for diverse computing systems ranging from synthesized hardware designs to software routines including binary and assembly programs. His work found application in major semiconductor companies, including AMD, Freescale, IBM, Intel, Galois, and Rockwell Collins. Dr. Ray is the author of three books (two upcoming), as well as more than 40 peer-reviewed research papers published in international journals and conferences. He has served on the technical program committee of more than 30 international meetings and conferences, and as general and program chair for ACL2 2009 and FMCAD 2013. He serves as an Associate Editor for IEEE Transactions on Multi-scale Computing Systems, and has served as guest Associate Editor for ACM TODAES and Springer JETTA. Dr. Ray has a Ph.D. from the University of Texas at Austin, and is a senior member of IEEE.

Algebraic Geometry is the study of the (geometry of) solutions to a system of polynomial equations. Modern algebraic geometry does not explicitly solve the system of equations to enumerate the solutions, but rather reasons about the solutions using abstract/computational algebra. Particularly, the theory and technology of Groebner bases provide a powerful set of tools to solve these polynomial decision problems. In this talk, I will describe how techniques from algebraic geometry and symbolic computation can be used to derive canonical (word-level) abstractions of the functions implemented by hardware designs.

Hardware designs and their functions often exhibit some structure or symmetry in the implementations. To improve our understanding of hardware designs, the functionality, symmetry and the structure of the circuits needs to be analyzed together. Can algebraic geometry help us achieve that? I will present Groebner bases techniques and applications that show glimpses of such a capability --- hopefully, this will motivate the DUHDe community to investigate the use of algebraic geometry to better understand hardware designs.

Bio: Priyank Kalla received the B.E. degree in electronics engineering from Birla Vishvakarma Mahavidyalaya, Sardar Patel University, Vallabh Vidyanagar, India, in 1993, and the M.S. and Ph.D. degrees from the University of Massachusetts, Amherst, in 1998 and 2002.

Since 2002, he has been first an Assistant Professor and now an Associate Professor with the Electrical and Computer Engineering Department at the University of Utah in Salt Lake City.

Dr. Kalla's research interests are in fundamental CAD techniques for the synthesis, optimization, and verification of digital VLSI circuits and systems.

Dr. Kalla was a recipient of the NSF CAREER award in 2006.

Chair:
Christian Fabre, CEA-LETI, Grenoble, FR

For 20 years, according to the top500 list, High Performance Computing has steadily increased its performance and is now seeking for the exaflop (10**18 double precision floating point operations per second). This increase is hiding drastic evolution in terms or architectures, moving from vector machines to GPGPU. Today, if the hardware is sustaining the pace, the applications are not getting easily benefits from it. Code has to be rewritten. Furthermore, performance implies on-the fly decisions by the processor impacting the performance: An obvious example is the "turbo". The consequence is that it's becoming more and more difficult to predict the performance of an application on a future architecture.

In this talk, Xavier will do an introduction about HPC trends and requirements, then, he will provide details about the impact of these evolutions on the application performance. Finally, he will expose what kind of tools and models he would need to predict the performance in the future architecture.

Speaker's bio: After a Ph.D. from Ecole normale superieure de Lyon in Distributed computing, he worked for several major companies in different positions. He has now been working for Bull for 10 years. He led the HPC benchmarking team for the first five years, then in charge of the "Education and Research" market for HPC at Bull, he is now managing de "Center for Excellence in Parallel Programming" of Bull. This CEPP activities focus on tackling issues in HPC application Performance

The utilisation of fast performance assessment technologies is crucial for bounding the cost of the design of efficient embedded systems. Accuracy is a prime concern, since performance models have to be sufficiently faithful to the actual implementations they reflect. In a design space exploration (DSE) context, sufficiently means that the performance models shall enable design decisions. In this context, this talk shows how native simulation, while providing a qualitative speed-up for DSE, can also preserve an accuracy (.e.g, <10% error vs binary translation in account of simulated instructions in bare processing modelling). This should provide the fidelity required for design space exploration in most scenarios. The generic ideas presented are supported by the experiments performed on top of an actual adaptation and extension of a native simulation tool called VIPPE, in order to enable time and energy estimation of specific target processors.

To be able to guarantee that real-time requirements of an application are met, the performance of the application running on a MPSOCs must be analysed at design time. Since exhaustive simulation is not possible practically and theoretically, the application and MPSOC must be modelled somehow.  A model can be as complex as the real implementation and contain all details of the application and MPSOC, or be very simple by omitting most of the implementation details. The question is how abstraction (the level of detail that is modelled) affects fidelity (model accuracy, or the correspondence of model and implementation). Intuitively, when abstracting more, the analysis effort decreases but the fidelity also decreases. In this talk we discuss our experiences with modelling the CompSOC MPSOC platform using several variants of dataflow at different levels of abstraction.

Chair:
Eugenio Villar, University of Cantabria, ES

Various models of computation for multi-core time-critical systems have been proposed in the literature, but there is a significant gap between the models of computation and the real-time scheduling and analysis techniques, that makes timing validation challenging. To overcome this difficulty, we represent both the models of computation and the scheduling policies by timed automata. While, traditionally, they are only used for simulation and validation, we use the automata for programming. We believe that using the same formal language for the model of computation and the scheduling techniques is an important step to close the gap between them. Our approach is demonstrated using a publicly available toolset, an industrial application use case and a multi-core platform.

Modern integrated circuits generate very high heat fluxes that can lead to a high temperature, degrading the performance and reducing the life time of the device. Thermal simulation is used to prevent this kind of issues, and many models were introduced in recent years. However, their validation is challenging: it is either based on established simulators (with reduced accuracy), or requires to produce a specific test chip with several thermal sensors. We present a thermal modelling approach with an associated methodology and measurement setup that uses existing commercial processors to validate thermal models. We use infrared thermography and a low-cost thermoelectric cooling, avoiding the issues of mineral oil setups. We show how our approach can be used to create validated models for two thermal simulators (our own approach, and a commercial tool).

 

Several robotic applications imply motion in complex unknown environments. Occupancy Grids model the surrounding obstacles through a partitioned spacial representation of the environment. A set of cells are filled iteratively with the interpretation of the information from sensors, considering their uncertainty through probabilistic models. Even if Occupancy Grids have been widely used in the state-of-the-art, the relation between the cell sizing and the inverse sensor model is usually neglected. In this paper, we propose a novel methodology to build inverse probabilistic model for single-target sensors. Since no additional limitation compared to the original formulation is introduced, our contribution allows to propagate the original precision of the sensor to the inverse model. In addition, it enables to properly choose the size of the cells. Our experiments apply our approach to a LIDAR sensor and to a Time-of-Flight camera, evaluating the grid resolution and the impact of the variation of the sensor precision.

Chair:
Adrian Evans, iRoC Technologies, FR

During this session, the workshop organizers will welcome the participants and give a very brief overview of the MorV and Clereco FP7 projects.

Chair:
Dimitris Gizopoulos, University of Athens, Department of Informatics & Telecommunications, GR

In this session two talks will be given by leaders in academia and industry, highlighting leading cross-layer solutions as well as the great challenges faced by industry.

Resilience to hardware failures is essential for a large class of future computing systems that are constrained by the so-called power wall: from embedded systems to supercomputers. To overcome this major challenge, we advocate and examine a cross-layer resilience approach. Two major components of this approach are: 1. System- and software-level effects of circuit-level faults are considered from early stages of system design; and, 2. resilience techniques are implemented across multiple layers of the system stack - from circuit and architecture levels to runtime and applications - such that they work together to achieve required degrees of resilience in a highly energy-efficient manner. Illustrative examples to demonstrate key aspects of cross-layer resilience will be discussed.

Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Before joining Stanford, he was a Principal Engineer at Intel.

Prof. Mitra's research interests include robust systems, VLSI design, CAD, validation and test, emerging nanotechnologies, and emerging neuroscience applications. His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. His work on carbon nanotubes, jointly with his students and collaborators, resulted in the demonstration of the first carbon nanotube computer, and it was featured on the cover of NATURE. The NSF presented this work as a Research Highlight to the US Congress, and it also was highlighted as "an important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide.

Prof. Mitra's honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation, "a test of time honor" for an outstanding technical contribution, the Semiconductor Research Corporation's Technical Excellence Award, and the Intel Achievement Award, Intel's highest corporate honor. He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology.

Prof. Mitra has served on numerous conference committees and journal editorial boards. He served on DARPA's Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.

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In this talk, Yongsheng Sun, will introduce HiSilicon (海思) and describe their cutting edge products. HiSilicon is one of the largest fabless companies and currently ships chips in the most advanced process technologies. Due to their success and huge number of products being shipped, reliability is a top concern. Sarinda Wang will describe the key challenges when designing highly reliable, silicon intenstive products. Specific issues will also be discussed to sensitisize the audience to the real-world reliability problems faced when shipping products in the most advanced technologies.

Yongsheng Sun received the B.S and M.S degree in Microelectronics from the University of Electronic Science and Technology of China in 2003 and 2006, respectively. In 2006, he joined Hisilicon Technologies Co., LTD. as a quality and reliability engineer, responsible for supplier's quality and reliability management. His current work is focus on Design for Reliability since 2011.

Chair:
Domenik Helms, OFFIS, DE

The poster sessions will be held during the coffee breaks in the morning (10:30..11:00) and from (14:30..15:00). During the workshop, each poster presenter will be give 1-2 minutes on the podium to quickly describe their work and entice participants to drop by and view their poster.

Chair:
Praveen Raghavan, IMEC, BE

During this sesion, participants are invited to demonstrate tools which help implement advance reliability flows.

Chair:
Alberto Bosio, LIRMM - University of Montpellier 2, FR

In this session, we will hear the perspectives of a major EDA vendor regarding the challenges in providing tools for meeting the reliability targets for automotive ICs.

Summary

Recent years, to enhance automotive functionalities for more driving enjoyment and hazard prevention, more and more electronic devices are used to monitor and control automotive operation. To ensure the safety of drivers and passengers, these electronic devices need higher reliability. In this talk, we will present what Mentor Graphics are doing to prepare for these reliability and safety challenges in pre-silicon, post-silicon and system operations.

 

About the Speaker

Wu-Tung Cheng is a Chief Scientist and Advanced Test Research Director in Mentor Graphics. He is an IEEE fellow since year 2000. He has over 150 publications and 50 patents in semiconductor manufacture test and diagnosis area. In 2006, he received ITC best paper award. In 2008, he received ITC honorable mention award. In 2014, he received ATS best paper award. He received his Ph.D. degree in Computer Science from the University of Illinois at Urbana-Champaign in 1985.

Chair:
Stefano Di Carlo, Politecnico di Torino, IT

Robert C. Aitken is an ARM Fellow and technology lead for ARM Research. His areas of responsibility include technology roadmapping, library architecture for advanced process nodes, and low power design. His research interests include design for variability, resilient computing, and memory robustness. His group has participated in numerous chip tape-outs, including 8 at or below the 16nm node. He has published over 70 technical papers, on a wide range of topics.  Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP.  He has given tutorials and short courses on several subjects at conferences and universities worldwide. He holds a Ph.D. from McGill University in Canada. Dr. Aitken is an IEEE Fellow, and serves on a number of conference and workshop committees.

Chair:
Praveen Raghavan, IMEC, BE

Summary

As FET devices scale toward ~10 nm gate lengths, the discreteness of matter and the particular arrangement of individual atoms in each device result in increased time-zero variability. Moreover, degradation mechanisms, such as TDDB and BTI, can be traced to as-fabricated and generated defects in the gate oxide. Since literally only a handful of defects will be present in each deeply scaled device, while the behavior of these defects is typically stochastic, voltage and temperature dependent, and widely distributed in time, each device will be behaving differently during operation, resulting in additional, time-dependent variability. We will argue that reliability and time-dependent variability of future deeply scaled devices can be understood from the perspective of individual defects. We will discuss the basic physical properties of individual defects. Finally, we will show how these properties can be described statistically, combined with actual workloads and propagated to higher design abstraction levels to project device and circuit lifetime distributions.

About the Speaker

Ben Kaczer is a Principal Scientist at imec, Belgium.  He received the M.S. degree in Physical Electronics from Charles University, Prague, in 1992 and the M.S. and Ph.D. degrees in Physics from The Ohio State University, in 1996 and 1998, respectively.   In 1998 he joined the reliability group of imec.  He has co-authored more than 350 journal and conference papers and 2 patents, presented a number of invited papers and tutorials, and received 5 IEEE IRPS Best and Outstanding Paper Awards, 2 IEEE IPFA Best Paper Awards, and the 2011 IEEE EDS Paul Rappaport Award. He has served or is serving at various functions at the IEDM, IRPS, SISC, INFOS, and WoDiM conferences.  He is currently serving on the IEEE T. Electron Dev. Editorial Board.

Overview

In the analog circuit design domain Spice simulators are the most commonly used tools for design exploration and verification.
Consequentially an integration of add-on models for aging effects like BTI and HCI using one of several available interfaces is
considered a straightforward enhancement allowing to address reliability analysis and verification. This talk will give an outline of all the not-so-straightforward challenges arising from the integration and deployment of complex aging models in the harsh environmental conditions of state-of-the-art EDA tool ecosystems.

About the Speaker

Peter Rotter was born in Germany in 1965. He received the diploma degree in physics from the University of Regensburg in Germany in 1994, followed by a Ph.D. degree from the same institute in 1997.

In 1998 he joined the central CAD department of the Infineon Technologies AG. In the section responsible for Infineon's Full Custom Design Flow development he worked over the years on various analog topics, like Spice simulator integration, PDK interfaces, post-layout simulation, analog model validation, statistical simulation, design for yield, design for reliability, general analog automation and analog sign-off methodology.

He current holds the position of a Senior Specialist Analog Sign-Off Methodology.

The research interests of Peter Rotter include analog and reliability verification, analog design automation and sign-off methodologies.

He has participated in various EU and national funded projects like Verona, Syena, Rely, Morv and Resist with a continuously strong interest in strengthening the collaboration of industry and academia.

Summary

Traditionally, aging of ICs was investigated by reliability departments and resulted in an overall guardband factor which needed to be considered during IC design. This approach is increasingly less appropriate. Transistor-level aging models, however, are not suitable for analyzing large circuits. Therefore, gate level timing models incorporating aging have been developed. We will show aging information can be abstracted further from gate to RT level - without loss of accuracy. We will also discuss how such RT level timing models can be employed to monitor the aging of digital circuits during their operation.

About the Speaker

Ulf Schlichtmann spent about 10 years in the semiconductor industry (Siemens, Infineon), in various engineering, management and executive positions. Among other assignments, he was responsible for Infineon's design libraries worldwide, managing about 125 engineers in Munich, Sophia Antipolis, San Jose and Singapore. In 2003, he joined TUM as head of the Institute for Electronic Design Automation. From 2007-2013 he served as Dean and Vice Dean of TUM's Department of Electrical and Computer Engineering.
His research focuses on algorithms for the efficient design of electronic circuits and systems. Abstraction levels from the transistor up to the system level are addressed. In recent years, he has put emphasis especially on the analysis and optimization of circuits and systems for reliability and resilience, with cross-layer techniques increasingly gaining in importance.

Panelists:
Ronald Newhart, IBM, US
Riccardo Mariani, YOGITECH SpA, IT
Tiberiu Seceleanu, ABB, SE

Permanent failures (EM, DB), Aging Failures (HCI, xBTI) and intermittent failures (radiation effects) are all serious threats to the reliable operation of integrated circuits. Which class of failures poses the most serious threat to today's large integrated circuits when they are deployed in the field? Pick one and defend your position. Please bring as much quantitative data as possible to defend your position.

Chair:
Dimitris Gizopoulos, University of Athens, Department of Informatics & Telecommunications, GR

Final remarks to thank the speakers, organizers and participants.

Discussion of plans for future sessions of the workshop.

Chair:
Gabriela Nicolescu, Polytechnique Montréal, CA

Co-Chair:
Mahdi Nikdast, Polytechnique Montréal/McGill University, CA

Chair:
Sébastien Le Beux, Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, FR

Abstract:

https://www.dropbox.com/s/qbs0gxions2zptg/OPTICS_2016_paper_19_Sebastien_Cremer.pdf?dl=0

Abstract:

https://www.dropbox.com/s/daazf1vznj69fem/OPTICS_2016_paper_7_Yoan_Leger.pdf?dl=0

Abstract:

https://www.dropbox.com/s/8clp8gyv21mmfct/OPTICS_2016_paper_21_Marc_Seifried.pdf?dl=0

Abstract:

https://www.dropbox.com/s/mctz8rn02mladx8/OPTICS_2016_paper_13_Akihiko_Shinya.pdf?dl=0

Paper:

https://www.dropbox.com/s/5ws9v5omzf4ilyi/OPTICS_2016_paper_3_PS1.pdf?dl=0

Paper:

https://www.dropbox.com/s/dgek42ai3svrhc5/OPTICS_2016_paper_4_PS2.pdf?dl=0

Paper: 

https://www.dropbox.com/s/twokkhg0fv64ntu/OPTICS_2016_paper_9_PS3CR.pdf?dl=0

Chair:
Mahdi Nikdast, Polytechnique Montréal/McGill University, CA

Abstract:

https://www.dropbox.com/s/kwlkyrogyf85s8n/OPTICS_2016_paper_6_Alan_Mickelson.pdf?dl=0

Abstract:

https://www.dropbox.com/s/tyejzrsvzqbyt3b/OPTICS_2016_paper_18_Jose_Flitch.pdf?dl=0

Abstract:

https://www.dropbox.com/s/iqbd43d77bq8wjk/OPTICS_2016_paper_17_Jiang_Xu.pdf?dl=0

Chair:
Jiang Xu, Hong Kong University of Science and Technology, HK

Abstract:

https://www.dropbox.com/s/qbjmiuklfwessdj/OPTICS_2016_paper_10_Keren_Bergman.pdf?dl=0

Abstract:

https://www.dropbox.com/s/uj8elr2c7xyio9g/OPTICS_2016_paper_16_Nikos_Hardavellas.pdf?dl=0

Abstract:

https://www.dropbox.com/s/to2jjhr4azvt4xe/OPTICS_2016_paper_2_Olivier_Sentieys.pdf?dl=0

Abstract:

https://www.dropbox.com/s/qc2kg4ga1zjxb30/OPTICS_2016_paper_14_Ayse_Coskun.pdf?dl=0

Chair:
Gabriela Nicolescu, Polytechnique Montréal, CA

Abstract:

https://www.dropbox.com/s/z5zgn7mn2m6n0dv/OPTICS_2016_paper_8_Philippe_Velha.pdf?dl=0

Abstract:

https://www.dropbox.com/s/28olz0wdtb8d1hh/OPTICS_2016_paper_12_Ruping_Cao.pdf?dl=0

Abstract:

https://www.dropbox.com/s/3mf9hm1ysgy4q84/OPTICS_2016_paper_20_Mahdi_Nikdast.pdf?dl=0

 

Abstract:

https://www.dropbox.com/s/ot5d3wrax3kgkfi/OPTICS_2016_paper_19_Davide_Bertozzi.pdf?dl=0

Abstract:

https://www.dropbox.com/s/sg8xk25o1gon47i/OPTICS_2016_paper_20_Ian_Connor.pdf?dl=0

Moderator:
Ian O'Connor, Lyon Institute of Nanotechnology, FR

Panelists:
Alan Mickelson, University of Colorado at Boulder, US
Gabriela Nicolescu, Polytechnique Montréal, CA
Sebastien Rumley, University of Columbia, US
Sebastien Cremer, STMicroelectronics, FR
Yoan Léger, CNRS – FOTON, FR

Chair:
Jiang Xu, Hong Kong University of Science and Technology, HK

Co-Chair:
Sébastien Le Beux, Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, FR

Chair:
Christian Weis, University of Kaiserslautern, DE

Abstract:
Energy and power costs are the primary reasons that our system-wide execution throughput (OPS) is no better than it currently is … while one could staple together 100 Oak Ridge Titans to create an exascale system, not many could afford to pay the resulting electric bill. And yet, a significant amount of research is still focused on increasing processor performance, rather than decreasing power and energy-to-solution. Modern high-performance systems are not throughput-bound; they are power-bound. Processing is so cheap it is effectively free; shaving power and energy costs at every opportunity, and at every level of the system, is the trick. Similarly, memory and communication are the primary reasons that our time-to-solution is no better than it currently is … the memory system is slow; the communication overhead is high; and yet a significant amount of research is still focused on increasing processor performance, rather than decreasing (the cost of) data movement. Modern high-performance systems are not compute-bound; they are data-bound. ALUs are so cheap that some propose to put them out in the memory … processing is free; getting the right data to the right place, cheaply, is the trick.  This talk will discuss recent technologies that our group has helped to develop in high-performance systems, including flash-based main memories and Micron's Hybrid Memory Cube, arguing that the design of exascale systems is almost entirely a memory-systems issue.

Bio:
Bruce Jacob is a Keystone Professor of Electrical and Computer Engineering and former Director of Computer Engineering at the University of Maryland in College Park. He received the AB degree in mathematics from Harvard University in 1988 and the MS and PhD degrees in CSE from the University of Michigan in Ann Arbor in 1995 and 1997, respectively. He holds several patents in the design of circuits for electric guitars and started a company around them. He also worked for two successful startup companies in the Boston area: Boston Technology and Priority Call Management. At Priority Call Management he was the initial system architect and chief engineer. He is a recipient of a US National Science Foundation CAREER award for his work on DRAM, and he is the lead author of an absurdly large book on the topic of memory systems. His research interests include system architectures, memory systems, operating systems, and electric guitars.

Chair:
Pascal VIVET, CEA-Leti, FR

Chair:
Rob Aitken, ARM, US

Abstract:
To continue reducing voltage in scaled technologies, both circuit and architecture-level resiliency techniques are needed to tolerate process-induced defects, variation, and aging in SRAM cells. Many different resiliency schemes have been proposed and evaluated, but most prior results focus on voltage reduction instead of energy reduction. At the circuit level, device cell architectures and assist techniques have been shown to lower Vmin for SRAM, while at the architecture level, redundancy and cache disable techniques have been used to improve resiliency at low voltages. This paper presents a unified study of error tolerance for both circuit and architecture techniques and estimates their area and energy overheads.  Optimal techniques are selected by evaluating both the error-correcting abilities at low supplies and the overheads of each technique in a 28nm.  The results can be applied to many of the emerging memory technologies.

Bio:
Borivoje Nikolić is the National Semiconductor Distinguished Professor of Engineering at the University of California, Berkeley.  He received the Dipl.Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Serbia, in 1992 and 1994,  respectively, and the Ph.D. degree from the University of California at Davis in 1999. His research activities include digital, analog and RF integrated circuit design and VLSI implementation of communications and signal processing algorithms. He is co-author of the book Digital Integrated Circuits: A Design Perspective, 2nd ed, Prentice-Hall, 2003. Dr. Nikolić received many awards in his career, including the NSF  CAREER award in 2003, and the best paper awards at the IEEE International Solid- State Circuits Conference, Symposium on VLSI Circuits, IEEE International SOI Conference, European Solid-State Circuits Research Conference, European Solid-State Device Research Conference, S3S conference and the ACM/IEEE International Symposium of Low- Power Electronics.

Moderator:
Rob Aitken, ARM, US

Panelists:
Ahmed Hemani, KTH, SE
Ivan Ivanov, Micron, DE
Ian O'Connor, ECL, FR
Yervant Zorian, Synopsys, US
Jan Van Houdt, IMEC, BE

Current memory systems consist of SRAMs, DRAMs and Flash memories/HDDs. The landscape of emerging memory technologies is changing quickly and memories differentiate in their availability, maturity, performance, power and endurance. Thus, this panel will highlight the cases where these new emerging memories potentially fit and where it is sensible to use them.

Chair:
Bastien Giraud, CEA-Leti, FR

Abstract:
Next-generation information technologies will process unprecedented amounts of loosely-structured data, including streaming video and audio, natural languages, real-time sensor readings, and contextual environments. These newly available data far exceed the processing capacity of existing computing architectures.
The N3XT (Nano-Engineered Computing Systems Technology) approach overcomes these challenges through recent advances across the computing stack: (a) one-dimensional carbon nanotubes and two-dimensional layered nanomaterials for high performance and energy efficiency, (b) high-density non-volatile resistive and magnetic memories, (c) Ultra-dense (e.g., monolithic) three-dimensional integration of logic and memory for fine-grained connectivity, (d) new architectures and runtimes for computation immersed in memory, and (e) new materials technologies and their integration for efficient heat removal.
Compared to conventional approaches, N3XT architectures promise to improve the energy efficiency of abundant-data applications significantly, in the range of three orders of magnitude, thereby enabling new frontiers of applications for both mobile devices and the cloud.

Bio:
Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Before joining Stanford, he was a Principal Engineer at Intel.
Prof. Mitra's research interests include robust systems, VLSI design, CAD, validation and test, emerging nanotechnologies, and emerging neuroscience applications.  His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer, and it was featured on the cover of NATURE. The US NSF presented this work as a Research Highlight to the US Congress, and it also was highlighted as "an important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide.
Prof. Mitra's honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, the ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation, "a test of time honor" for an outstanding technical contribution, the Semiconductor Research Corporation's Technical Excellence Award, and the Intel Achievement Award, Intel's highest corporate honor.  He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology.
Prof. Mitra has served on numerous conference committees and journal editorial boards. He served on DARPA's Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.

Chair:
Gregory Di Pendina, CNRS-Spintec, FR

Chair:
Matthias Jung, University of Kaiserslautern, DE

Abstract:
Computing systems as well as embedded systems have been continuously improved performance and power efficiency. In order to achieve this improvement, the systems have required high bandwidth memories, especially DRAM. One of good emerging solutions of high bandwidth memory is the High Bandwidth Memory (HBM), a JEDEC standard product, which can respond to next generation memory subsystem requirements.

Abstract:
Processing in Memory enables optimal bandwidth and latency thanks to the proximity with data. Significant performance improvements of data-centric applications can be measured when hundreds of co-processors are distributed in DRAM. At the same time, to facilitate integration and adoption, hardware and software should be open and compatible with legacy, including DDR/DIMM.

Chair:
Kaya Can Akyel, CEA-Leti, FR

Authors:

F.Oboril¹, R.Bishnoi¹, M.Ebrahimi¹, and M.Tahoori¹ , G. Di Pendina², K.Jabeur², G.Prenat^2
1Karlsruhe Institute of Technology, Germany
²Univ. Grenoble Alpes, CNRS, CEA, INAC-SPINTEC, Grenoble, France

Authors:

Yohei Umeki¹, Koji Yanagida¹, Hiroaki Kurotsu¹, Hiroto Kitahara¹, Haruki Mori¹, Shintaro Izumi¹, Masahiko Yoshimoto¹,Hiroshi Kawaguchi¹, Shusuke Yoshimoto², Koji Tsunoda³, Toshihiro Sugii³

¹ Graduate School of System Informatics Kobe University, Japan
² The Institute of Scientific and Industrial Research, Osaka University, Japan
³ Low-Power Electronics Association and Project (LEAP), Japan

 

 

Authors:

Ajay Kapoor, Nur Engin, NXP Semiconductors, NL

Authors:

Erfan Azarkhish¹, Davide Rossi¹, Igor Loi¹, Luca Benini^1,2

¹ DEI, University of Bologna, Bologna, Italy
² ITET, Swiss Federal Institute of Technology, Zurich, Switzerland

 

Authors:

Rou-Li Melody Wang, Yun-Chao Yu, and Jin-Fu

Department of Electrical Engineering National Central University , Taiwan

Chair:
Kaya Can Akyel, CEA-Leti, FR

Author:

Said Hamdioui, Computer Engineering, Delft University of Technology, NL

Authors:

Yong-Xiao Chen and Jin-Fu Li, Advanced Reliable Systems (ARES) Lab., Department of Electrical Engineering, National Central University, Taiwan

Authors:

Frank Vater and Mario Schoelzel, IHP GmbH, Germany

Authors:

Joseph Nguyen^1,2, D. Turgis¹, D. Bonciani¹, B. Lhomme¹, Y. Carminati¹, O. Callen¹, G. Guirleo¹, L. Ciampolini¹, G. Ghibaudo²

¹ STMicroelectronics, Crolles, France
²IMEP-LAHC, Grenoble, France

Authors:

Oskar Andersson, Babak Mohammadi, and Joachim Neves Rodrigues, Department of Electrical and Information Technology, Lund University, Sweden

Authors:

Nasim Farahini¹, Matthias Jung^2, Pei Liu¹, Smah Jafri¹, Christian Weis², Ahmed Hemani¹, Norbert Wehn²

¹KTH, Sweden
²University of Kaisertslautern, Germany

Authors:

Kaya Can Akyel, Fabien Clermidy, Jean-Francois Nodin, Luca Perniola

CEA-LETI, Grenoble, France

Authors:

Rotem Ben-Hur and Shahar Kvatinsky, Israel Institute of Technology, Israel

Chair:
Christian Weis, University of Kaiserslautern, DE

Co-Chair:
Bastien Giraud, CEA-Leti, FR

Chair:
Cristina Silvano, Politecnico di Milano, IT

End of Dennard scaling and increasing performance to cost ratios on multicore architectures have recently stimulated a new era of increasingly heterogeneous compute architectures and large diversification of integrated circuits has dawned. During this talk, we will elaborate on our ongoing efforts within the Xilinx research organization to shed light on the universal question what applications work on which architectures best, and benchmark and characterize a wide spectrum of applications and compute architectures including FPGAs, GPUs, Xeons and Xeon Phis.

Resource sharing and interferences of multiple threads of one, but even worse between multiple application programs running concurrently on a Multi-Processor System-on-a-Chip (MPSoC) today make it very hard to provide any timing or throughput-critical applications with time bounds.
Additional interferences result from the interaction of OS functions such as thread multiplexing and scheduling as well as complex resource
(e.g., cache) reservation protocols used heavily today. Finally, dynamic power and temperature management on a chip might also throttle down processor speed at arbitrary times leading to additional varations and jitter in execution time. This may be intolerable for many safety-critical applications such as medical imaging or automotive driver assistance systems.

Static solutions to provide the required isolation by allocating distinct resources to safety- or performance-critical applications may not be feasible for reasons of cost and due to the lack of efficiency and unflexibility.

In this invited talk, we first review and present novel definitions of predictability of execution qualities. Subsequently, we distinguish two techniques for improving predictability called restriction and isolation and present new definitions. Then, new techniques for adaptive isolation of resources including processor, I/O, memory as well as communication resources on demand on an MPSoC are introduced based on the paradigm of Invasive Computing.
In Invasive Computing, a programmer may specify bounds on the execution quality of a program or even segment of a program followed by an invade command that returns a constellation of exclusive resources called a claim that is subsequently used in a by-default non-shared way until being released
again by the invader. Through this principle, it becomes possible to isolate applications automatically and in an on-demand manner. In invasive computing, isolation is supported on all levels of hardware and software including the OS. Together with restriction (of input uncertainties), the level of on-demand predictability of program execution qualities may be fundamentally increased.

For a broad class of streaming applications, and a concrete demonstration based on a complex object detection application algorithm chain taken from robot vision, we show how jitter-minimized implementations become possible, even for statically unknown arrivals of other concurrent applications.

Chair:
Walter Stechele, TUM, DE

Numeric simulations and scientific computing cause an increasing demand for high performance computing resources. However, limitations due to energy consumption and limited application scalability require significant research efforts to build the next generation of even larger, yet more efficient supercomputers.
This talk will show the concepts and achievements of the EU funded DEEP-ER, and Mont-Blanc projects in researching and prototyping new computer architectures suited for future scientific computing applications and also explain the challenges when trying to tune application performance and energy efficiency at scale.

Chair:
Stephan Wong, TU Delft, NL

The variety of concerns developers may have to face when developing and compiling their applications overloads the development and deployment phases. When targeting contemporary systems (e.g., including heterogeneous many/multicore architectures) developers need to focus on specific mapping decisions and optimizations, specification of runtime adaptivity strategies, and features related to the tools being used. Monitoring, adaptivity, and tuning are three fundamental features developers may need to consider in order to achieve more efficient software and hardware/software solutions. One of the challenges is related to the way to express these features when considering General Programming Languages (GPLs), such as C and Java. In this talk we present our Domain-Specific Language (DSL) approach and the challenges we face to make the approach highly useful to developers. Our approach is based on LARA, an aspect-oriented programming (AOP) language, specifically designed for allowing developers to program code instrumentation strategies, to control the application of code transformations and compiler optimizations, and to effectively control different tools in a toolchain. LARA provides a separation of concerns, including non-functional requirements and strategies, while allowing to exploit the benefits of an automatic approach for various domain-specific and target component-specific compilation/synthesis tools. The experiments of using LARA in the context of different aspects of programming and compilation have revealed its cross-cutting and cross-layer benefits. In this talk, we will briefly introduce the LARA language, its current status and supporting tools, as well as some of the plans related to the extensions to LARA in the context of the H2020 ANTAREX project.

Capabilities of self-awareness have been shown to facilitate the sensible management of a system's resources in the presence of faults and when environmental conditions and demands change. This is not surprising since a detailed knowledge of the system's own state, its shortcomings, its performance as well as the environment's expectations is a precondition to allocate the available resource where they are most useful.

The talk will demonstrate this principle by way of the Cyber-physical SoC (CPSoC), which is a platform full of sensors to monitor delays, power consumption, temperature, and aging phenomena. This information is used to continuously adjust resource usage resulting in minimal power consumption and wear out for a given performance target.

Chair:
Jeronimo Castrillon, TU Dresden, Germany, DE

Speakers from morning & afternoon sessions are invited as panelists.

Chair: Michael Hübner