10.6 Circuit Design and Test: From Characterization to Measurement

Date: Thursday 12 March 2015
Time: 11:00 - 12:30
Location / Room: Bayard

Chair:
Salvador Mir, TIMA/CNRS, FR

Co-Chair:
Christoph Grimm, University of Kaiserslautern, DE

This session covers eye-diagram analysis for high-speed circuits, statistical digital library characterization, analog test ordering in the context of muti-site testing, and estimation of defect detection probability of analog test.

Time	Label	Presentation Title Authors
11:00	10.6.1	(Best Paper Award Candidate) FAST EYE DIAGRAM ANALYSIS FOR HIGH-SPEED CMOS CIRCUITS Speakers: Seyed Nematollah Ahmadyan¹, Chenjie Gu², Suriyaprakash Natarajan², Eli Chiprout² and Shobha Vasudevan¹ ¹University of Illinois at Urbana-Champaign, US; ²Intel, US Abstract We present an efficient technique for analyzing eye diagrams of high speed CMOS circuits in the presence of non-idealities like noise and jitter. Our method involves geometric manipulations of the eye diagram topology to find area within the eye contours. We introduce random tree based simulations as an approach to computing the desired area. We typically show $20X$ speedup in generating the eye diagram as compared to the state-of-the-art Monte Carlo simulation based eye diagram analysis. For the same number of samples, Monte Carlo produces an eye diagram that is $8.51\%$ smaller than the ideal eye diagram. We generate an eye diagram that is $53.52\%$ smaller than the ideal eye, showing a $47\%$ improvement in quality. Download Paper (PDF; Only available from the DATE venue WiFi)
11:30	10.6.2	STATISTICAL LIBRARY CHARACTERIZATION USING BELIEF PROPAGATION ACROSS MULTIPLE TECHNOLOGY NODES Speakers: Li Yu¹, Sharad Saxena², Christopher Hess², Ibrahim Elfadel³, Dimitri Antoniadis¹ and Duane Boning¹ ¹Massachusetts Institute of Technology, US; ²PDF Solutions, Inc, US; ³Masdar Institute of Science and Technology, AE Abstract In this paper, we propose a novel flow to enable computationally efficient statistical characterization of standard cell libraries. The distinguishing feature of the proposed method is the usage of a limited combination of output capacitance, input slew rate and supply voltage for the extraction of statistical timing metrics of an individual logic gate. The efficiency of the proposed flow stems from the introduction of a novel, ultra-compact, nonlinear, analytical timing model, having only four universal regression parameters. This novel model facilitates the use of maximum-a-posteriori belief propagation to learn the prior parameter distribution for the parameters of the target technology from past characterizations of library cells belonging to various other technologies, including older ones. The framework then utilizes Bayesian inference to extract the new timing model parameters using an ultra-small set of additional timing measurements from the target technology. The proposed method is validated and benchmarked on several production-level cell libraries including a state-of-the-art 14-nm technology node and a variation-aware, compact transistor model. For the same accuracy as the conventional lookup-table approach, this new method achieves at least 15x reduction in simulation runs. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	10.6.3	COMBINING ADAPTIVE ALTERNATE TEST AND MULTI-SITE Speaker: Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES Abstract Testing analog, mixed-signal and RF circuits represents one of the main cost components for complex SoCs. Multisite Testing is widely accepted as a straightforward technique to reduce the effective test time. This paper shows that an adaptive Alternate Test approach can be compatible with a multisite strategy. The proposed solution consists in ordering offline the signatures acquisition sequence and training incremental regression models for each new feature. These models can be used to diagnose the circuit as good, provided that the estimate of the performance is larger than the specification plus a guard-band related to the model error. If all the sites are diagnosed as good, the test program can be halted before completion. This decision is taken on-line and makes this scheme adaptive. We provide an analytical study of the expected test time reduction and of the test escape penalty that is incurred. Results obtained from post-layout MonteCarlo simulations of an LNA demonstrate the validity of the approach and show that significant test time improvements can be obtained, even for large number of sites, whenever the manufacturing yield is sufficiently high. Download Paper (PDF; Only available from the DATE venue WiFi)
12:15	10.6.4	A METHOD FOR THE ESTIMATION OF DEFECT DETECTION PROBABILITY OF ANALOG/RF DEFECT-ORIENTED TESTS Speakers: John Liaperdos¹, Angela Arapoyanni² and Yiorgos Tsiatouhas³ ¹Technological Educational Institute of Peloponnese, Dept of Computer Engineering, GR; ²National and Kapodistrian University of Athens, Dept. of Informatics and Telecommunications, GR; ³University of Ioannina, GR Abstract A method to realistically estimate the defect detection probability achieved by defect-oriented analog/RF integrated circuit tests at the circuit design level is presented in this paper. The proposed method also provides insight to the efficiency of the various available defect-oriented testing techniques, thus allowing the selection of the most suitable for a specific circuit. The effect of structural defects in the presence of process variations and device mismatches is taken into account, by the exploitation of the defect probability distributions and the statistical models of the used technology. Although the proposed methodology is generally applicable to the entire class of analog circuits, its application to simple RF circuits which consist of a few elements seems to be more practical, due to the affordable computational cost implied by circuits with shorter defect dictionaries. In order to obtain results without a reliability compromise, the number of required statistical simulation runs is reduced through regression. The application of the proposed method on a typical RF mixer, designed in a 0.18um CMOS technology, is also presented. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30	IP5-5, 212	EMPIRICAL MODELLING OF FDSOI CMOS INVERTER FOR SIGNAL/POWER INTEGRITY SIMULATION Speakers: Wael Dghais and Jonathan Rodriguez, Instituto de Telecomunicações, PT Abstract This paper presents a multiport empirical model based on artificial neural network for I/O memory interface (e.g. inverter) designed based on fully depleted silicon on isolator (FDSOI) CMOS 28 nm process for signal and power integrity assessments. The analog mixed-signal identification signals that carry the information about the I/O interface's nonlinear dynamic behavior are recorded from large signal simulation setup. The model's functions are extracted based on a nonlinear optimization algorithm and then implemented in Simulink software. The performance of the resulted model is validated in typical power and ground switching noise scenario. The developed empirical model accurately predicts the timing signal waveforms at the power, ground, and at the output port. Download Paper (PDF; Only available from the DATE venue WiFi)
12:31	IP5-6, 1003	ON-CHIP MEASUREMENT OF BANDGAP REFERENCE VOLTAGE USING A SMALL FORM FACTOR VCO BASED ZOOM-IN ADC Speakers: Osman Erol¹, Sule Ozev¹, Chandra K. H. Suresh², Rubin Parekhji³ and Lakshmanan Balasubramanian³ ¹ASU, US; ²NYU-Abu Dhabi, AE; ³TI, IN Abstract A robust and highly scalable technique for measuring the output voltage of a band-gap reference (BGR) circuit is described. The proposed technique is based on an ADC architecture that uses a voltage controlled oscillator (VCO) for voltage to frequency conversion. During production testing, an external voltage reference is used to approximate the voltage/frequency characteristics of the VCO with 5ms test time. The proposed zoom-in ADC approach is manufactured with 0.5um single well CMOS process. Measurement results indicate that 13 bits of resolution within the measurement range can be achieved with the zoom-in approach. Worst-case INL for the ADC is less than 0.25LSB (50V). Download Paper (PDF; Only available from the DATE venue WiFi)
12:30		End of session Lunch Break, Keynote lecture from 1320 - 1350 (Room Oisans) in Les Écrins Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch Break On Tuesday and Wednesday, lunch boxes will be served in front of the session room Salle Oisans and in the exhibition area for fully registered delegates (a voucher will be given upon registration on-site). On Thursday, lunch will be served in Room Les Ecrins (for fully registered conference delegates only). Tuesday, March 10, 2015 Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30; Keynote session from 13:20 - 14:20 (Room Oisans) sponsored by Mentor Graphics Coffee Break 16:00 - 17:00 Wednesday, March 11, 2015 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30, Keynote lectures from 12:50 - 14:20 (Room Oisans) Coffee Break 16:00 - 17:00 Thursday, March 12, 2015 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00, Keynote lecture from 13:20 - 13:50 Coffee Break 15:30 - 16:00