Date: Thursday 12 March 2015
Time: 08:30 - 10:00
Location / Room: Chartreuse
Chair:
Martin Trefzer, University of York, GB
Co-Chair:
Yvain Thonnart, CEA-Leti, FR
As technology evolves, "information" is no longer limited to charge-based representations of 1s and 0s. In this session, the first presented paper discusses work where qubits are stored as the internal states of an atomic ion. The second presentation considers labs on chip — where reactants are moved through valves and channels to solve problems such as protein analysis, disease diagnosis, etc. Finally, the last presentation discusses the use of optical waveguides to move data from point-to-point, thus eliminating higher latency electrical interconnect.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 9.4.1 | OPTIMIZATION OF QUANTUM COMPUTER ARCHITECTURE USING A RESOURCE-PERFORMANCE SIMULATOR Speakers: Muhammad Ahsan and Jungsang Kim, Duke University, US Abstract The hardware technology characterized by the device parameters often drives the architectural optimization in a novel computer design such as the quantum computer (QC). We highlight the role of these parameters, by quantifying the performance of a fully error-corrected 1024-bit quantum carry look-ahead adder on a modular, re-configurable architecture based on trapped ions. We develop a simulation tool that estimates the performance and resource requirements for running a quantum circuit on various quantum architectures as a function of the underlying device parameters. Using this tool, we found that (1) the latency of the adder circuit execution due to slow entanglement generation process for qubit communication, can be adequately eliminated with a small increase in entangling qubits and (2) the failure probability of the circuit is ultimately determined by the qubit coherence time, which needs to be improved in order to reliably execute the adders comprising core of the Shor's algorithm. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 9.4.2 | VOLUME-ORIENTED SAMPLE PREPARATION FOR REACTANT MINIMIZATION ON FLOW-BASED MICROFLUIDIC BIOCHIPS WITH MULTI-SEGMENT MIXERS Speakers: Chi-Mei Huang1, Chia-Hung Liu2 and Juinn-Dar Huang1 1Department of Electronics Engineering, National Chiao Tung University, TW; 2National Chiao Tung University, TW Abstract Sample preparation is one of essential processes in most biochemical reactions. In this process, raw reactants are diluted to achieve given target concentrations. So far, most of existing sample preparation techniques only consider mixing of two source solutions under the (1:1) mixing model. In this paper, we propose the first sample preparation algorithm VOSPA that not only blends several solutions in a dilution operation but also allows various mixing models on flow-based microfluidic biochips with multi-segment mixers. VOSPA is a volume-oriented sample preparation algorithm that enables segment-based intermediate solution reuse for better reactant minimization. Experimental results show that VOSPA can lower the reactant consumption and operation count by 72% and 59% as compared to the baseline bit-scanning method if an 8-segment mixer is used. Moreover, VOSPA outperforms an optimal algorithm, which merely allows the use of (1:1) mixing model; the reactant usage and operation count can be further reduced by 37% and 76%. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 9.4.3 | THERMAL AWARE DESIGN METHOD FOR VCSEL-BASED ON-CHIP OPTICAL INTERCONNECT Speakers: Hui Li1, Alain Fourmigue2, Sébastien Le Beux1, Xavier Letartre1, Ian O’Connor1 and Gabriela Nicolescu2 1Ecole Centrale de Lyon, FR; 2Ecole Polytechnique de Montréal, CA Abstract Optical Network-on-Chip (ONoC) is an emerging technology considered as one of the key solutions for future generation on-chip interconnects. However, silicon photonic devices in ONoC are highly sensitive to temperature variation, which leads to a lower efficiency of Vertical-Cavity Surface-Emitting Lasers (VCSELs), a resonant wavelength shift of Microring Resonators (MR), and results in a lower Signal to Noise Ratio (SNR). In this paper, we propose a methodology enabling thermal-aware design for optical interconnects relying on CMOS-compatible VCSEL. Thermal simulations allow designing ONoC interfaces with low gradient temperature and analytical models allow evaluating the SNR. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | IP4-11, 170 | TOPOLOGY IDENTIFICATION FOR SMART CELLS IN MODULAR BATTERIES Speakers: Sebastian Steinhorst and Martin Lukasiewycz, TUM CREATE, SG Abstract This paper proposes an approach to automatically identifying the topological order of smart cells in modular batteries. Emerging smart cell architectures enable battery management without centralized control by coordination of activities via communication. When connecting smart cells in series to form a battery pack, the topological order of the cells is not known and it cannot be automatically identified using the available communication bus. This order, however, is of particular importance for several battery management functions, including temperature control and active cell balancing which relate properties of the cells and their location. Therefore, this paper presents a methodology to automatically identify a topological order on the smart cells in a battery pack using a hybrid communication approach, involving both the communication and the balancing layer of the smart cell architecture. A prototypic implementation on a development platform shows the feasibility and scalability of the approach. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:01 | IP4-12, 993 | LVS CHECK FOR PHOTONIC INTEGRATED CIRCUIT - CURVILINEAR FEATURE EXTRACTION AND VALIDATION Speakers: Ruping Cao1, Julien Billoudet1, John Ferguson1, Lionel Couder2, John Cayo2, Alexandre Arriordaz1 and Ian O'Connor3 1Mentor Graphics Corp, FR; 2Mentor Graphics Corp, US; 3Lyon Institute of Nanotechnology, FR Abstract This work is motivated by the demand of an electronic design automation (EDA) approach for the emerging ecosystem of the photonic integrated circuit (PIC) technology. A reliable physical verification flow cannot be achieved without the adaption of the traditional EDA tools to the photonic design verification needs. We analyze how layout versus schematic (LVS) checking is performed differently for photonic designs, and propose an LVS flow that addresses the particular need of curvilinear feature validation (curved path length and bend curvature extraction). We show that it is possible to reuse and extend the current LVS tools to perform such critical but non-traditional checks, which ensures a more reliable photonic layout implementation in term of functionality and circuit yield. Going forward, we propose possible future studies that can further improve the flows. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area Coffee Break in Exhibition AreaOn all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch BreakOn Tuesday and Wednesday, lunch boxes will be served in front of the session room Salle Oisans and in the exhibition area for fully registered delegates (a voucher will be given upon registration on-site). On Thursday, lunch will be served in Room Les Ecrins (for fully registered conference delegates only). Tuesday, March 10, 2015Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30; Keynote session from 13:20 - 14:20 (Room Oisans) sponsored by Mentor Graphics Coffee Break 16:00 - 17:00 Wednesday, March 11, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30, Keynote lectures from 12:50 - 14:20 (Room Oisans) Coffee Break 16:00 - 17:00 Thursday, March 12, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00, Keynote lecture from 13:20 - 13:50 Coffee Break 15:30 - 16:00 |