Date: Tuesday 10 March 2015
Time: 17:00 - 18:30
Location / Room: Belle Etoile
Chair:
Francesco Regazzoni, AlaRI, CH
Co-Chair:
Georg Becker, RUB, DE
System designers need secure building blocks for robust security devices. This session presents novel implementation and verification strategies for hardware circuits, post-quantum cryptography schemes and true random number generators.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 4.2.1 | PRIVACY-PRESERVING FUNCTIONAL IP VERIFICATION UTILIZING FULLY HOMOMORPHIC ENCRYPTION Speakers: Charalambos Konstantinou1 and Michail Maniatakos2 1New York University Polytechnic School of Engineering, US; 2New York University Abu Dhabi, AE Abstract Intellectual Property (IP) verification is a crucial component of System-on-Chip (SoC) design in the modern IC design business model. Given a globalized supply chain and an increasing demand for IP reuse, IP theft has become a major concern for the IC industry. In this paper, we address the trust issues that arise between IP owners and IP users during the functional verification of an IP core. Our proposed scheme ensures the privacy of IP owners and users, by a) generating a privacy-preserving version of the IP, which is functionally equivalent to the original design, and b) employing homomorphically encrypted input vectors. This allows the functional verification to be securely outsourced to a third-party, or to be executed by either parties, while revealing the least possible information regarding the test vectors and the IP core. Experiments on both combinational and sequential benchmark circuits demonstrate up to three orders of magnitude IP verification slowdown, due to the computationally intensive fully homomorphic operations, for different security parameter sizes. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | 4.2.2 | EFFICIENT SOFTWARE IMPLEMENTATION OF RING-LWE ENCRYPTION Speakers: Ruan de Clercq, Sujoy Sinha Roy, Frederik Vercauteren and Ingrid Verbauwhede, KU Leuven - COSIC, BE Abstract Present-day public-key cryptosystems such as RSA and Elliptic Curve Cryptography (ECC) will become insecure when quantum computers become a reality. This paper presents the new state of the art in efficient software implementations of a post-quantum secure public-key encryption scheme based on the ring-LWE problem. We use a 32-bit ARM Cortex-M4F microcontroller as the target platform. Our contribution includes optimization techniques for fast discrete Gaussian sampling and efficient polynomial multiplication. Our implementation beats all known software implementations of ring-LWE encryption by a factor of at least 7. We further show that our scheme beats ECC-based public-key encryption schemes by at least one order of magnitude. At medium-term security we require 121166 cycles per encryption and 43324 cycles per decryption, while at a long-term security we require 261939 cycles per encryption and 96520 cycles per decryption. Gaussian sampling is done at an average of 28.5 cycles per sample. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:00 | 4.2.3 | EMBEDDED HW/SW PLATFORM FOR ON-THE-FLY TESTING OF TRUE RANDOM NUMBER GENERATORS Speakers: Bohan Yang1, Vladimir Rozic1, Nele Mentens1, Wim Dehaene2 and Ingrid Verbauwhede3 1ESAT/COSIC and iMinds, KU Leuven, BE; 2ESAT-MICAS, KU Leuven, BE; 3KU Leuven - COSIC, BE Abstract We present a HW/SW platform for on-the-fly detection of failures and weaknesses in entropy sources. By splitting the operations between hardware and software, we achieve sufficient flexibility to control the level of significance of the tests. This approach also enables sharing resources between different tests thereby reducing the area and power. Statistical tests were selected from the NIST test suite. We propose several versions of hardware co-processors for monitoring random bit sequences, ranging from 52 slices (5 tests) to 552 slices (9 tests) on Spartan-6 FPGA. We are the first to provide implementations of the Serial test and the Approximate entropy test for on-the-fly monitoring. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | IP2-1, 834 | COMPARISON OF MULTI-PURPOSE CORES OF KECCAK AND AES Speakers: Panasayya Yalla, Ekawat Homsirikamol and Jens-Peter Kaps, George Mason University, US Abstract Most widely used security protocols, Internet Protocol Security (IPSec), Secure Socket Layer (SSL), and Transport Layer Security (TLS), provide several cryptographic services which in turn require multiple dedicated cryptographic algorithms. A single cryptographic primitive for all secret key functions utilizing different mode of operations can overcome this constraint. This paper investigates the possibility of using AES and Keccak as the underlying primitives for high-speed and resource constrained applications. Even though a plain AES implementation is typically much smaller and has a better throughput to area ratio than a plain Keccak, adding additional cryptographic services changes the results dramatically. Our multi-purpose Keccak outperforms our multi-purpose AES by a factor of 4 for throughput over area on average. This underlines the flexibility of the Keccak Sponge and Duplex functions. Our multi-purpose Keccak achieves a throughput of 23.2 Gbps in AE-mode (Keyak) on a Xilinx Virtex-7 and 28.7 Gbps on a Altera Stratix-IV. In order to study this further we also implemented two versions of a dedicated Keyak and dedicated AES-GCM. Our dedicated Keyak implementation outperforms our dedicated AES-GCM on average by a factor 6 in terms of throughput over area reaching a throughput of 28.9 Gbps and 4.1 Gbps respectively on a Xilinx Virtex-7. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | End of session | |