Rolf Drechsler, University of Bremen/DFKI GmbH, DE (Contact Rolf Drechsler)
PhD Forum Committee ChairRolf Drechsler, University of Bremen/DFKI GmbH, DE (Contact Rolf Drechsler)
PhD Forum Committee MembersWalter Anheier, University of Bremen, DE
Laleh Behjat, University of Calgary, CA
Davide Bertozzi, Università degli studi di Ferrara, IT
Anupam Chattopadhyay, Nanyang Technological University, SG
Giorgio Di Natale, LIRMM, FR
Helmut Graeb, TU München, DE
Shiyan Hu, Michigan Technological University, US
Younghyun Kim, Purdue University, US
Xin Li, Carnegie Mellon University, US
Gi-Joon Nam, IBM, US
Sander Stuijk, Eindhoven University of Technology, NL
Daniel Tille, Infineon Technologies, DE
Miroslav N. Velev, Aries Design Automation, US
Natarajan Viswanathan, IBM, US
Robert Wille, University of Bremen/DFKI GmbH, DE
| Time | Label | Session |
|---|---|---|
| 19:00 | FM01.1 | Poster Session |
| 19:00 | FM01.1.1 | Selective Transistor-Redundancy Based Fault Tolerance Technique for Combinational Circuits Ahmad Sheikh, King Fahd University of Petroleum & Minerals, SA |
| 19:00 | FM01.1.2 | Definition of Methods and Tools for an Effective Smart Buildings Deployment Alessandro Antonio Nacci, Politecnico di Milano, IT |
| 19:00 | FM01.1.3 | Design Methods for Reliable Quantum Circuits Alexandru Paler, University of Passau, DE |
| 19:00 | FM01.1.4 | Energy Efficient Cache Memories in Deeply-Scaled Technologies Alireza Shafaei Bejestan, University of Southern California, US |
| 19:00 | FM01.1.5 | Hybrid Wire and Surface-wave Communication Fabrics for Future NoC-based Chip Multiprocessors Ammar Karkar, School of Electrical and Electronic Engineering, Newcastle University, Newcastle upon Tyne, GB |
| 19:00 | FM01.1.7 | High-level Constructive Synthesis of Domain-Specific Kernels of Cryptography Ayesha Khaild, RWTH Aachen, DE |
| 19:00 | FM01.1.8 | Safety-Assured Model-Based Implementation of the GPCA Infusion Pump Software BaekGyu Kim, University of Pennsylvania, US |
| 19:00 | FM01.1.9 | Improved Test Techniques for Network-on-Chip Based Memory Systems Bibhas Ghoshal, IIT, Kharagpur, IN |
| 19:00 | FM01.1.10 | Dedicated Hardware Accelerators for High Efficiency Video Coding Standard Cláudio Diniz, UFRGS, BR |
| 19:00 | FM01.1.11 | Heat Dissipation and Thermal Analysis for 3D ICs Cristiano Santos, PGMICRO-UFRGS / CEA-Leti, BR |
| 19:00 | FM01.1.12 | Fault Tolerance for Real-Time Systems: Analysis and Optimization of Roll-back Recovery with Checkpointing Dimitar Nikolov, Lund University, Department of Electrical and Information Technology, SE |
| 19:00 | FM01.1.13 | SyntHorus2: A Tool for Assertion-based Synthesis Fatemeh JAVAHERI, TIMA Lab, FR |
| 19:00 | FM01.1.14 | Multilevel Modeling, Formal Analysis, and Characterization of Soft Errors in Digital Systems Ghaith Bany Hamad, Polytechnique Montréal, CA |
| 19:00 | FM01.1.15 | RHetOS: A Reconfigurable and Heterogeneous Operating System Gianluca Durelli, Politecnico di Milano, IT |
| 19:00 | FM01.1.16 | Path-Based Program Repair Heinz Riener, University of Bremen, DE |
| 19:00 | FM01.1.17 | Theory and applications of quantum process calculus Ittoop Puthoor, University of Glasgow, GB |
| 19:00 | FM01.1.18 | Non-Invasive Extraction of SystemC Meta Data Jannis Stoppe, DFKI GmbH, DE |
| 19:00 | FM01.1.19 | Synthesis and Optimization of Reversible Logic Circuits Kamalika Datta, National Institute of Technology, Meghalaya, IN |
| 19:00 | FM01.1.20 | Optical Interconnects for Computing Systems: a Formal Study on Signal-to-Noise Ratio Mahdi Nikdast, Polytechnique Montréal, CA |
| 19:00 | FM01.1.21 | NoC-Centric Partitioning and Reconfiguration Technologies for the Efficient Sharing of Many-Core Platforms Marco Balboni, University of Ferrara, IT |
| 19:00 | FM01.1.22 | Post-Manufacturing One-Shot Calibration of RF Circuits Based on Non-Intrusive Sensors Martin Andraud, TIMA Laboratory, FR |
| 19:00 | FM01.1.23 | Range Based Analysis of Inner Systems Characteristics Michael Rathmair, Institute of Computer Technology, Vienna University of Technology, AT |
| 19:00 | FM01.1.24 | Making Homogeneous the Platform-Based Design of Heterogeneous Cyber-Physical Systems Michele Lora, University of Verona, IT |
| 19:00 | FM01.1.25 | Power Aware Test and Test of Low Power Devices Miroslav Valka, Post-Doc, FR |
| 19:00 | FM01.1.26 | Run-Time Resource Management of Networked Many-Core Systems Mohammad Fattah, University of Turku, FI |
| 19:00 | FM01.1.27 | Thermal Management Using Thermoelectric Coolers Mohammad Javad Dousti, University of Southern California, US |
| 19:00 | FM01.1.28 | Yield and Cost Analysis for 3D Stacked ICs Mottaqiallah Taouil, Delft University of Technology, NL |
| 19:00 | FM01.1.29 | Hardware-Software Co-Design for Next Generation Dark Silicon Multimedia Systems Muhammad Usman Karim Khan, Karlsruhe Institute of Technology (KIT), DE |
| 19:00 | FM01.1.30 | Design Space Exploration of Thread vs. Arithmetic Level Parallelism to Design a Computation Unit of the Multi-chip eBrain Supercomputer Nasim Farahini, KTH, SE |
| 19:00 | FM01.1.31 | Towards High Performance and Efficiency of Heterogeneous Systems Sam Skalicky, Rochester Institute of Technology, US |
| 19:00 | FM01.1.32 | Power: Its Manifestations in Digital Systems Testing Seetal Potluri, Indian Institute of Technology Madras, IN |
| 19:00 | FM01.1.33 | Managing the Complexity in Embedded and Cyber-Physical System Design - System Modeling and Design-Space Exploration Seyed-Hosein Attarzadeh-Niaki, KTH Royal Institute of Technology, SE |
| 19:00 | FM01.1.34 | Logic Rewiring: a Practical Bridging Technique between VLSI Logical and Physical Syntheses Xing Wei, Chinese University of Hong Kong, HK |
| 19:00 | FM01.1.35 | Distributed Thermal Management for Large-Scale Chip-Multiprocessors Yingnan Cui, Nanyang Technological University, SG |
| 19:00 | FM01.1.36 | High-level Modeling, Estimation and Exploration of Reliability for MPSoC Zheng Wang, RWTH-Aachen University, DE |
| 19:00 | FM01.1.37 | Modeling, Analysis and Exploration of Layers: A 3D Computing Architecture Zoltán Endre Rákossy, Institute for Communication Technologies and Embedded Systems (ICE), RWTH Aachen, DE |
Patrick Cogez, STMicroelectronics, FR (Contact Patrick Cogez)
Rangharajan Venkatesan, Purdue, US (Contact Rangharajan Venkatesan)
Invited SpeakersKaushik Roy, Purdue University, US (Contact Kaushik Roy)
Anand Raghunathan, Purdue University, US (Contact Anand Raghunathan)
| Time | Label | Session |
|---|---|---|
| 09:30 | M01.1 | Session 1 |
| 09:30 | M01.1.1 | Introduction to Spintronics Kaushik Roy, Purdue University, US |
| 10:00 | M01.1.2 | Spintronic Memories: Devices and Bit-cells Kaushik Roy, Purdue University, US |
| 10:45 | M01.1.3 | Spintronic Memory Hierarchies Rangharajan Venkatesan, Purdue, US |
| 12:00 | M01.2 | Session 2 |
| 12:00 | M01.2.1 | Spintronic Logic Devices Kaushik Roy, Purdue University, US |
| 12:20 | M01.2.2 | Boolean and Non-Boolean Computing with Spintronic Devices Anand Raghunathan, Purdue University, US |
Mehdi Tahoori, Karlsruhe Institute of Technology, DE (Contact Mehdi Tahoori)
| Time | Label | Session |
|---|---|---|
| 14:30 | M02.1 | Spin-Orbit-Torque spintronic device and technology Chair: The interaction between spin and orbital magnetism is responsible for some of the most important magnetic phenomena, such as the magnetocrystalline anisotropy and the anisotropic magnetoresistance. By locking the spin to the direction of motion, the spin-orbit interaction can additionally give rise to strong torques on the magnetization when an electric current is injected in the plane of a ferromagnet/heavy metal bilayer. Such torques are strong enough to induce magnetization reversal, and can be reversed by inverting the polarity of the current. These features, together with the in-plane current injection geometry, allow for fabricating three-terminal magnetic tunnel junction devices for novel memory and logic applications. Furthermore, spin-orbit torque magnetization switching is an ultrafast process with minimum incubation time, thus leading to a short read/write access time. In this talk we will present an overview of:
|
| 14:30 | M02.1.1 | Spin-Orbit-Torque spintronic device and technology Pietro Gambardella, Department of Materials, ETH Zurich, CH |
| 15:30 | M02.2 | Hybrid CMOS/Magnetic Non-volatile Standard Cell Design Flow Chair: Most of recent research on MRAM-based non-volatile logic and memories is considering Spin Transfer Torque Magnetic Tunnel Junctions with perpendicular-to-plane anisotropy (STTpe-MTJ). However, this technology suffers from limitations mainly due to the fact that it uses the same writing and reading paths. It is subject to high read disturb failure rates, meaning that a Magnetic Tunnel Junction (MTJ) can be written during a reading phase, in particular in case of high speed writing. Moreover, it has a limited endurance since the writing current flows through the tunnel barrier and damages it, especially when the polarization of the MTJ is approaching its breakdown voltage when writing. A much more recent technology enables to avoid such problems. Indeed Spin Orbit Torque Magnetic Tunnel Junctions (SOT-MTJ) have 3 terminals, enabling to separate the writing path from the reading path. These leads to a quasi-infinite endurance since the writing current flows underneath the SOT-MTJ in a conducting layer, and to a high reliability since there is no read disturb risk thanks to the use of 2 separate paths. This talk will address the following topics:
|
| 15:30 | M02.2.1 | Hybrid CMOS/Magnetic Non-volatile Standard Cell Design Flow Gregory Di Pendina and Guillaume Prenat, Spintec / CEA-CNRS, FR |
| 17:00 | M02.3 | Memory and System Architecture Design using SOT-MRAM Chair: This talk overviews the architecture and system-level aspects in the design of SOT-MRAM as a part of the cache hierarchy. We will discuss how various features of the SOT-MRAM can be modeled by the memory system simulators and the design space for a hybrid memory architecture consisting of various flavors of MRAM and SRAM can be explored. Particularly this session presents performance, power, area, and reliability tradeoffs in the design of SOT-MRAM at various levels of cache hirerachy and compares them with STT-MRAM counterpart as well as traditional SRAM memories. |
| 17:00 | M02.3.1 | Memory and System Architecture Design using SOT-MRAM Mehdi Tahoori, Karlsruhe Institute of Technology, DE |
Swaroop Ghosh, University of South Florida, US (Contact Swaroop Ghosh)
Conventional CMOS memory i.e., Static Random Access Memory (SRAM) has been the popular choice for embedded memory application for last several decades. However, SRAM seems to be approaching a brick wall. On one hand process variability and leakage power is posing severe obstruction towards SRAM scaling to future nodes and on the other hand, emerging energy-constrained and bandwidth hungry electronic gadgets demand for larger as well as energy-efficient on-chip cache which cannot be satisfied with SRAM. To address the changing landscape of consumer market, there is a corresponding need of changing the design paradigm. What is really needed is a memory technology that s at least 50-100X denser, 1000X energy-efficient and as fast as SRAM. Several emerging memory technologies are on the horizon but there is no clear universal choice for embedded application. This tutorial will explore the latest trends in the embedded memory segment and discuss the fundamental limitations of SRAM in meeting the new needs of the electronic systems. The complex (and not very well understood) inter-relationships between memory density, bandwidth, latency, power and speed will be elaborated. The tutorial will discuss most promising emerging memory technologies where storage element is based on charge, spin and resistance. The specific focus will be on the operating principles, design challenges and solutions of non-volatile memories (NVM) such as Spin Transfer Torque RAM (STTRAM), Domain Wall Memory (DWM) and Resistive RAM (RRAM). New applications of the emerging memory technologies for exciting applications such as memory-based computations, hardware security and neuromorphic computing will also be presented.
The first part of the tutorial will describe the fundamental barriers e.g., process variations and leakage power towards SRAM scaling. It will cover some of the state-of-the-art design practices followed in industry and academia to keep the SRAM scaling alive. Techniques ranging from devices all the way to circuits and systems will be presented to address SRAM design challenges. Different topologies of SRAM such as 6T-14T coupled with Vmin enhancement techniques will also be discussed to achieve robustness and energy-efficiency. Moreover, recent trends in SRAM design for Internet of Things (IoT) and sensor circuits will be discussed.
The second part of the tutorial will describe STTRAM and DWM which are two promising spin-based memory technologies. The basics of spintronic memory operating principles, benefits and limitations will be covered. That will be followed by discussion on various design metrics such as read/write power, speed, robust sensing, reliability and retention. The tutorial will address the modeling and simulation methodology for design and analysis of STTRAM and DWM arrays. State-of-the-art circuit and system design methodologies from industry and academia will be elaborated to solve the spintronic memory limitations and expose the benefits. The methods will include adaptive biasing, current boosting, data encoding, error-correction, trade-off with data retention etc. This section will conclude with applications of spintronics in new areas such as hardware security and non-Boolean computation models.
The last part of this tutorial will describe another promising memory technology, namely RRAM, where the storage element is resistive in nature. We will cover device-circuit-architecture level design issues and solutions associated with application of RRAM to both storage as well as adaptive computing. Typical RRAM cells suffer from high access power and poor sense margin. Design techniques to lower the power consumption such as data encoding, write pause, and circuit-level solution for addressing the sneak path issue will be discussed to mitigate the power while maintaining required robustness. Multi-level RRAM, design challenges and solutions will also be described. We will cover applications of RRAM in the processor memory hierarchy as well as in efficient reconfigurable computing fabric. We will describe the challenges and opportunities in building RRAM based reconfigurable hardware – both purely spatial (such as FPGA), as well as spatio-temporal. For wide array of data-intensive applications, energy dissipation is primarily contributed by transportation of the data from off-chip memory to on-chip computing elements– a limitation referred to as the "Von-Neumann bottleneck". An application of RRAM for Memory-Based Computing (MBC) will also be introduced to effectively overcome the bottleneck. Finally, we will describe the opportunities of using RRAM in brain-inspired computing, e.g. developing a synaptic network, for highly parallel and ultralow-power information processing.
The audiences will be able to takeaway following key points from this tutorial: (a) changing landscape of emerging electronic systems and inability of SRAM to cater to these new needs in scaled technologies, (b) emerging memory technologies for embedded applications and their relative merits in terms of density, power, speed and reliability, (c) challenges, design methodologies and potential solutions to enable these emerging memories for embedded applications, and, (d) new and exciting applications of emerging memory technologies in internet-of-things, non-Boolean computing, memory-based computing, brain-inspired computing and hardware security.
Tutorial Organization:
1. Introduction and Motivation – 15 min
a. Need for embedded memory
b. Challenges with Static Random Access Memory
• Process variations, leakage, aging
• Impact on key system metrics - power, reliability, performance
c. Emerging technologies
• Overview
• Resistive: ReRAM, memrister
• Spintronic- Magnetic RAM, STTRAM, DWM, spintronic memrister
d. Summary
2. Static Random Access Memory - 50 min
a. 6T SRAM design challenges and solutions
• Device design
• Assist circuits
• Architecture
b. 6T+ SRAM Designs
• 8T SRAMs (Register Files) – Assist Techniques
• 10T and 14T topologies with circuit assist
c. SRAMs for Wearbles, IoT and sensor circuits
• Sub-threshold SRAMs
• Low leakage SRAMs
d. Summary
3. Spintronic Memory – 50 min
a. Basics of spintronics
• Operating principles
• Flavors of spintronic memories
• Opportunities and limitations
b. Spin-Transfer Torque RAM
• Challenges- Write latency, write power, asymmetric read/write, process variations
• Circuit solutions- adaptive design, robust sensing
• System-level solutions- error-correcting codes, data encoding, trade-offs with retention
c. Domain Wall Memory
• Challenges- Shift latency, write latency, write power, process variations
• Circuit solutions- current boosting, shift-based writing
• System-level solutions- workload-aware boosting, cross-layer design
d. Applications in hardware security
• Security-specific properties
• Example security primitive- Physically Unclonable Functions
e. Summary
4. Resistive RAM – 50 min
a. Basics of RRAM
• History of resistive storage element
• Operating principles
• Comparison of RRAM with other memory technologies
• Single-Level Cell (SLC) vs. Multi-Level Cell (MLC)
• Opportunities and limitations
b. Design methodologies
• Circuit level design solutions - adaptive design, robust sensing, approaches to address sneak path issue
• Architecture level design including challenges and approaches with RRAM cache
• System-level solutions - data encoding, xxx
c. RRAM based reconfigurable hardware
• RRAM based FPGA architecture
• Memory-based spatio-temporal computing with RRAM
d. Brain-inspired computing
• Synaptic electronics with RRAM
• Design principles and case studies
e. Summary
5. Conclusions and Discussions – 15 min
a. Current industrial practices
b. Emerging trends
c. Future research directions
Speakers:
Swaroop Ghosh
Biography: Swaroop Ghosh received his B.E. (Hons.) from Indian Institute of Technology, Roorkee, India in 2000 and Ph.D. from Purdue University in 2008. He joined the faculty of University of South Florida in Fall 2012. Dr. Ghosh was a senior research and development engineer in Advanced Design, Intel Corp from 2008 to 2012. At Intel, his research was focused on low power and robust embedded memory design in scaled technologies. He has filed seven US patents, published over 45 papers and authored a book chapter. His research interests include low-power, energy-efficient and robust circuit/system design and digital testing for nanometer technologies. Dr. Ghosh is a senior member of IEEE.
Swarup Bhunia
Biography: Swarup Bhunia received his B.E. (Hons.) from Jadavpur University, Kolkata, India, and the M.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur. He received his Ph.D. from Purdue University, IN, USA, in 2005. Currently, Dr. Bhunia is T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, OH, USA. He has over ten years of research and development experience with over 150 publications in peer-reviewed journals and premier conferences in the area of VLSI design, CAD and test techniques. His research interests include low power and robust design, hardware security and protection, adaptive nanocomputing and novel test methodologies. He has worked in the semiconductor industry on RTL synthesis, verification, and low power design for about three years. Dr. Bhunia received IBM Faculty Award (2013), National Science Foundation (NSF) career development award (2011), Semiconductor Research Corporation (SRC) technical excellence award as a team member (2005), SRC Inventor Recognition Award (2009), best paper award in International Conference on VLSI Design (2012), best paper award in International Conference on Computer Design (2004), best paper award in Latin American Test Workshop (2003), and several best paper nominations. He is an associate editor of IEEE Transactions on CAD and ACM Journal of Emerging Technologies. He has served as a guest editor of IEEE Design & Test of Computers (2010, 2013), in the editorial board of Journal of Low Power Electronics (JOLPE) and in the technical program committee of several premier IEEE/ACM conferences. He has served as a panelist and given tutorial in major conferences. He is a senior member of IEEE.
Jaydeep Kulkarni
Biography: Jaydeep P. Kulkarni (M'09) received the B.E. degree from the University of Pune, India in 2002, the M. Tech. degree from the Indian Institute of Science (IISc) Bangalore, India in 2004 and Ph.D. degree from Purdue University, West Lafayette, IN, in 2009 all in electrical engineering. During 2004–05, he was with Cypress Semiconductors, Bangalore, India where he was involved in low power SRAM design. He is currently working as a staff research scientist in the Circuit Research Lab, Intel Corporation Hillsboro, OR. His research is focused on device/circuit co-design of novel transistors, low voltage logic and memory circuits and power management circuits. Dr. Kulkarni received the Best M. Tech Student Award from IISc Bangalore in 2004, SRC Inventor Recognition Awards, 2008 ISLPED Design Contest Award, 2008 Intel Foundation Ph.D. Fellowship Award, best paper in session award at 2008 SRC TECHCON, and 2010 Outstanding Doctoral Dissertation Award from Purdue School of ECE. He has served on ASQED, ISLPED, A-SSCC technical program committees and serves as an industrial liaison at the Semiconductor Research Corporation.
| Time | Label | Session |
|---|---|---|
| 16:13 | M03.1 |
Florian Letombe, Synopsys, FR (Contact Florian Letombe)
General ChairAli Abbara, Synopsys, FR (Contact Ali Abbara)
Invited SpeakersJean-Marc Forey, Synopsys, FR (Contact Jean-Marc Forey)
Susanne Kandl, Vienna University of Technology, AT (Contact Susanne Kandl)
Stéphane Bouvier, ST Microelectronics, FR (Contact Stéphane Bouvier)
Jürgen Hanisch, Robert Bosch GmbH, DE (Contact Jürgen Hanisch)
| Time | Label | Session |
|---|---|---|
| 14:30 | M04.1 | Mutation-Based Testing: Origins, Concepts, and Applications Chair: Co-Chair: A first presentation will introduce the origins and main concepts of Certitude, a functional qualification tool commercialized by Synopsys. The second speaker will give an overview on mutation-based techniques for verification purposes. |
| 14:30 | M04.1.1 | Certitude-C/C++ : A functional qualification tool for fault injection in C/C++/SystemC models Jean-Marc Forey and Ali Abbara, Synopsys, FR This presentation will introduce the origins and main concepts of Certitude, a functional qualification tool commercialized by Synopsys. Certitude can measure and help to improve all aspects of functional verification quality at different levels of abstraction, including HDL and C/C++/SystemC languages. Certitude is a mutation-based testing tool. It automatically inserts bugs (also called faults) into the hardware or software models. Then it determines whether the verification environment can activate the faulty code, propagate the effects to an observable point, and detect the presence of the fault. |
| 15:30 | M04.1.2 | How Mutations Can Help to Prove That Your System Does Not Contain (Unwanted) Mutations Susanne Kandl, Vienna University of Technology, AT In this tutorial presentation we give an overview on mutation-based techniques for verification purposes. A mutation is a modification of a component of the verification environment. Whereas the main aim of verification is to detect unwanted mutations in the system (colloquial: bugs), intended and reproducible mutations can help to assess, reveal weaknesses, and, by this, improve the verification environment. Mutations may be applied to the system itself (e.g., software), to system properties, to test cases, or to other verification components. Besides explaining the basic principles, we will address the powerfulness and possible restrictions of the proposed mutation-based techniques for verification. |
| 16:30 | M04.2 | Applying Certitude on Automotive and Multimedia C/C++/SystemC Models Chair: Co-Chair: In this session, we will discuss Certitude usage to ensure the highest level of confidence on Multimedia IPs in STMicroelectronics on C/C++ models which are inputs of the HLS flow. Another presentation from Bosch will consider an example of an automotive Microcontroller IP modeled on TLM in SystemC. |
| 16:30 | M04.2.1 | Multimedia IPs Verification Quality Improvement - Usage of Certitude on C/C++ Models Stéphane Bouvier, STMicroelectronics, FR Verifying multimedia IPs is very challenging due to its infinite possibility of combination. The proposed presentation will discuss about Certitude usage in STMicroelectronics to ensure the highest level of confidence on these IPs. It will show how Certitude is applied on C/C++ models which are inputs of the HLS flow to ensure a robust verification environment. It will also describe the developed strategies to automate this flow and find early weaknesses in the verification environment. |
| 17:00 | M04.2.2 | Automotive Microcontroller Peripheral IP Verification - Applying Certitude on SystemC Models Juergen Hanisch, Robert Bosch GmbH, DE This presentation shows the usage of Certitude on an Automotive Microcontroller IP which is available in a VHDL implementation for a SoC integration and a SystemC implementation usable as a reference model in simulation environments. |
Davide Quaglia, EDALab s.r.l., IT (Contact Davide Quaglia)
Invited SpeakersMartin Lukasiewycz, TUM CREATE, SG (Contact Martin Lukasiewycz)
Riccardo Muradore, University of Verona, IT (Contact Riccardo Muradore)
Sebastian Steinhorst, TUM CREATE, SG (Contact Sebastian Steinhorst)
| Time | Label | Session |
|---|---|---|
| 09:30 | M05.1 | Session 1 Chair: |
| 09:30 | M05.1.1 | Introduction to electric vehicles: key aspects and design challenges Martin Lukasiewycz, TUM CREATE, SG |
| 10:15 | M05.1.2 | Battery management in electric vehicles Sebastian Steinhorst, TUM CREATE, SG |
| 11:30 | M05.2 | Session 2 Chair: |
| 11:30 | M05.2.1 | Joint controller-communication design in electric vehicles Riccardo Muradore, University of Verona, IT |
| 12:15 | M05.2.2 | System-level simulation of electric vehicles Davide Quaglia, EDALab s.r.l., IT |
Samarjit Chakraborty, TU Munich, DE (Contact Samarjit Chakraborty)
Invited SpeakersSamarjit Chakraborty, TU Munich, DE (Contact Samarjit Chakraborty)
Rafik Henia, Thales, FR (Contact Rafik Henia)
Arne Hamann, Robert Bosch GmbH, DE (Contact Arne Hamann)
| Time | Label | Session |
|---|---|---|
| 16:13 | M06.1 |
Olivier Sentieys, INRIA - University of Rennes 1, FR (Contact Olivier Sentieys)
Invited SpeakersDaniel Menard, INSA Rennes/IETR, FR (Contact Daniel Menard)
David Novo, EPFL, CH (Contact David Novo)
Karthick Parashar, IMEC, Leuven, BE (Contact Karthick Parashar)
| Time | Label | Session |
|---|---|---|
| 09:30 | M07.1 | Fixed-point refinement, a guaranteed approach towards energy efficient computing: Part I Organiser: |
| 09:30 | M07.1.1 | 1. Introduction Olivier Sentieys, INRIA - University of Rennes 1, FR
|
| 09:45 | M07.1.2 | 2. Fixed-point arithmetic Olivier Sentieys, INRIA - University of Rennes 1, FR
|
| 10:15 | M07.1.3 | 3. Finite word-length effect analysis Daniel Menard, INSA Rennes/IETR, FR
|
| 11:30 | M07.2 | Fixed-point refinement, a guaranteed approach towards energy efficient computing: Part II Organiser: |
| 11:30 | M07.2.1 | 4. High-level synthesis under accuracy constraint Karthick Parashar, IMEC, BE
|
| 12:15 | M07.2.2 | 5. SIMD vectorization under accuracy constraint David Novo, EPFL, CH
|
| 12:35 | M07.2.3 | 6. Opportunistic run-time precision adaptation David Novo, EPFL, CH
|
| 12:50 | M07.2.4 | 7. Conclusion and open research directions David Novo, EPFL, CH |
Massimo Poncino, Politecnico di Torino, IT (Contact Massimo Poncino)
Invited SpeakersDavide Quaglia, EDALab s.r.l., IT (Contact Davide Quaglia)
Alain Pegatoquet, LEAT/University of Nice Sophia Antipolis, FR (Contact Alain Pegatoquet)
| Time | Label | Session |
|---|---|---|
| 14:30 | M08.1 | Session 1 Chair: |
| 14:30 | M08.1.1 | Introduction to autonomous wireless smart systems and design challenges Davide Quaglia, EDALab s.r.l., IT Autonomous wireless smart systems will be defined with reference to current applications. Their architecture and functionality will be described with particular emphasis on communicating aspects. Finally, design challenges will be presented with particular emphasis on mechanisms to guarantee energy sustainability. |
| 15:00 | M08.1.2 | Energy Storage Devices: Characteristics, Non-Idealities and Design Challenges Massimo Poncino, Politecnico di Torino, IT This section of the tutorial will discuss the main peculiarities of energy storage devices, and battery in particular, used in autonomous smart systems. The presentation will describe the main non-idealities and how they results in some misconception about the usage of energy in electronic systems. Part of the discussion will be also devoted to the issue of energy conversions that can results in significant energy inefficiency in the overall power budget of smart systems. |
| 16:30 | M08.2 | Session 2 Chair: |
| 16:30 | M08.2.1 | Managing power to enable autonomous communicating objects Alain Pegatoquet, LEAT/University of Nice Sophia Antipolis, FR The main goal of this presentation is to describe efficient power management policies and protocols for energy neutral systems. This talk also covers different aspects related to autonomous systems, such as energy storage sizing, multi-hop network, transmission power control, etc. An architecture suitable to harvest different sources of energy is introduced as well. Experiments, conducted either in simulation or with a real hardware platform, demonstrate the benefits of the proposed power management policies on the system quality of service. This presentation ends with trends for future wireless smart systems. |
| 17:30 | M08.2.2 | Holistic modeling and simulation techniques Davide Quaglia, EDALab s.r.l., IT Because of the increasing optimization needed in future wireless smart systems, the designer should jointly take into account aspects from different domains, such as digital (hardware, software, network) and analog (electronic, electromechanical, etc., as for instance RF, MEMS, power sources, thermal issues, sensors and actuators). Therefore the joint verification of such aspects requires new methodologies and tools for multi-disciplinary and multi-scale modeling and simulation. This presentation will start by providing a survey on modeling fundamentals and then it will focus on a novel approach for joint software-hardware-energy-network simulation which was proposed in SMAC European Project. |
Haralampos Stratigopoulos, TIMA Laboratory, FR (Contact Haralampos Stratigopoulos)
Yiorgos Makris, The University of Texas at Dallas, US (Contact Yiorgos Makris)
| Time | Label | Session |
|---|---|---|
| 09:30 | M09.1 | Introduction |
| 09:30 | M09.1.1 | Data analytics opportunities in semiconductor manufacturing and test Yiorgos Makris, The University of Texas at Dallas, US |
| 09:45 | M09.2 | Wafer-level variation analysis and applications |
| 09:45 | M09.2.1 | Fundamentals of spatial and spatiotemporal variation modeling Yiorgos Makris, The University of Texas at Dallas, US |
| 10:15 | M09.2.2 | Test cost reduction through statistical estimation using inter-die correlations Yiorgos Makris, The University of Texas at Dallas, US |
| 10:45 | M09.2.3 | Process monitoring, outlier detection, and yield learning Yiorgos Makris, The University of Texas at Dallas, US |
| 11:30 | M09.3 | Statistical learning in test |
| 11:30 | M09.3.1 | Fundamentals of machine learning and its applications in test Haralampos-G. Stratigopoulos, TIMA Laboratory, FR |
| 12:00 | M09.3.2 | Adaptive test Haralampos-G. Stratigopoulos, TIMA Laboratory, FR |
| 12:30 | M09.3.3 | Probabilistic test metrics for evaluating alternative low-cost tests Haralampos-G. Stratigopoulos, TIMA Laboratory, FR |
Said Hamdioui, Delft University of Technology, NL (Contact Said Hamdioui)
| Time | Label | Session |
|---|---|---|
| 16:13 | M10.1 |
Giorgio Di Natale, LIRMM, FR (Contact Giorgio Di Natale)
Dominique Borrione, TIMA Labs, FR (Contact Dominique Borrione)
Suzanne Lesecq, CEA LETI-MINATEC Campus, FR (Contact Suzanne Lesecq)
Anca Molnos, CEA-LETI, Grenoble, FR (Contact Anca Molnos)
Saddek Bensalem, Université Joseph Fourier, FR (Contact Saddek Bensalem)
Kees Goossens, Eindhoven Univ. of Technology, NL (Contact Kees Goossens)
Koji Inoue, Kyoto University, JP (Contact Koji Inoue)
Vania Joloboff, INRIA, FR (Contact Vania Joloboff)
Diana Marculescu, Carnegie Mellon University, US (Contact Diana Marculescu)
Eugenio Villar, University of Cantabria, ES (Contact Eugenio Villar)
Christian Fabre, CEA-LETI, Grenoble, FR (Contact Christian Fabre)
Julien Mottin, CEA, FR (Contact Julien Mottin)
| Time | Label | Session |
|---|---|---|
| 08:30 | W01.1 | Opening Session Co-Chairs: |
| 08:30 | W01.1.1 | Opening Session |
| 08:45 | W01.2 | Session 1: Performance and power models of parallel systems Chair: |
| 08:45 | W01.2.1 | Keynote: Empowering mixed-critical system engineers in the dark silicon era: Towards power, temperature and aging analysis of heterogeneous MPSoCs at system-level. Kim Grüttner, OFFIS - Institute for Information Technology, DE Kim Grüttner is head of the Hardware/Software Design Methodology group at OFFIS - Institute for Information Technology in Oldenburg. Since 2005, he holds a Diploma degree in Computer Science from the University of Oldenburg, Germany, joined OFFIS in 2005 as researcher and works since 10/2008 as group manager. Kim Grüttner was involved in the EU-Projects ICODES (Interface and Communication-based Design of Embedded Systems) and ANDRES (Analysis and Design of run-time Reconfigurable, heterogeneous Systems). He has coordinated the COMPLEX (Codesign and power Management in Platform-based design space Exploration) European integrated project. Currently, he is coordinating the CONTREX (Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties) European integrated project, which constitutes the European Mixed-Criticality Cluster together with the running projects DREAMS and PROXIMA. His research topics include Electronic System-Level design and synthesis for Multi-Processor System on Chips (MPSoC), system-level design methodologies and languages for HW and SW systems with a focus on HW/SW communication, interface synthesis, power and temperature modelling for mixed-criticality MPSoCs. |
| 09:30 | W01.2.2 | Regular paper: Power-proportional modelling fidelity Ashur Rafiev1, Fei Xia2, Alexei Iliasov1, Rem Gensh1, Ali Aalsaud1, Alexander Romanovsky1 and Alex Yakovlev1 1Newcastle University, GB; 2University of Newcastle upon Tyne, GB |
| 10:00 | W01.2.3 | Regular paper: Implementation-Aware Buffer-Throughput Tradeoff in Embedded Stream Applications Kamyar Mirzazad Barijough1, Matin Hashemi1, Volodymyr Khibin2 and Soheil Ghiasi2 1Sharif University of Technology, IR; 2University of California, Davis, US |
| 10:30 | W01.3 | Coffee break |
| 11:00 | W01.4 | Session 2: SoC design-flows for fast platform prototyping Chair: |
| 11:00 | W01.4.1 | Regular paper: SimSoC: A Fast Proven Faithful Full System Virtual Prototyping Framework Vania Joloboff1, Jean-Francois Monin2 and Xiaomu Shi2 1INRIA, FR; 2University of Grenoble, FR |
| 11:30 | W01.4.2 | Regular paper: A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications Seyed-Hosein Attarzadeh-Niaki1, Ekrem Altinel1, Martijn Koedam2, Anca Molnos3, Ingo Sander4 and Kees Goossens5 1KTH Royal Institute of Technology, SE; 2Eindhoven university of technology, NL; 3CEA LETI, FR; 4Royal Institute of Technology, SE; 5Eindhoven Univ. of Technology, NL |
| 12:00 | W01.5 | Lunch break |
| 13:00 | W01.6 | Session 3: Verification and implementation of embedded systems from high-level models Chair: |
| 13:00 | W01.6.1 | Keynote: Building Faithful High-level Models and Performance Evaluation of Embedded System Saddek Bensalem, Université Joseph Fourier, FR Saddek Bensalem, is Professor in Computer Science at VERIMAG laboratory, University of Grenoble, France. His research interests are in the study of embedded systems, formal specification and verification, algorithmic verification techniques, complex systems, real-time systems, automata and logics. His work has been on the topic of automatic formal verification of systems that have unbounded numbers of states. He has pioneered development of techniques that combine the complementary strengths of deductive and algorithmic methods. He has made significant research contributions on several aspects of this problem, among which the theory of property-preserving abstraction and relationship to compositional verification, automatic invariant discovery, predicate abstraction and a verification method for parametrized systems. |
| 13:45 | W01.6.2 | Regular paper: Analysis and Implementation of Embedded System Mode Bojan Nokovic and Emil Sekerinski, McMaster University, CA |
| 14:30 | W01.7 | Coffee break |
| 14:30 | W01.8 | Demo and poster session Chair: |
Naehyuck Chang, Korea Advanced Institute of Science and Technology (KAIST), KR (Contact Naehyuck Chang)
Massimo Poncino, Politecnico di Torino, IT (Contact Massimo Poncino)
Sebastian Steinhorst, TUM CREATE, SG (Contact Sebastian Steinhorst)
| Time | Label | Session |
|---|---|---|
| 08:30 | W02.1 | Battery Challenges in EV Design Chair: |
| 08:30 | W02.1.1 | Electric Vehicle Design - Battery Pack Challenges Patrick Groeneveld, Synopsys, US |
| 09:30 | W02.1.2 | From Electrochemistry to Battery Cells - Control and Monitoring Challenges Jochen Friedl, TUM CREATE, SG |
| 10:00 | W02.2 | Coffee Break |
| 10:30 | W02.3 | Efficient Battery Management System Design Chair: |
| 10:30 | W02.3.1 | Characterization and Modeling of Electric Vehicle Power Consumption and Battery Usage Naehyuck Chang1 and Sheldon Tan2 1Korea Advanced Institute of Science and Technology (KAIST), KR; 2UC Riverside, US |
| 11:00 | W02.3.2 | Active Cell Balancing and Verification Methodologies in the BMS Domain Martin Lukasiewycz, TUM CREATE, SG |
| 11:30 | W02.3.3 | Smart Cell Architectures for Scalable Battery Packs Sebastian Steinhorst, TUM CREATE, SG |
| 12:00 | W02.4 | Lunch Break |
| 13:00 | W02.5 | Modeling and Simulation for Better Batteries Chair: |
| 13:00 | W02.5.1 | Modeling Issues for Battery Packs: Accuracy vs. Simulation Complexity Massimo Poncino, Politecnico di Torino, IT |
| 13:30 | W02.5.2 | Multiphysics, Multiscale Simulation of a Complete Li-ion Battery Pack and Sub-Systems Vincent Delafosse, ANSYS, US |
| 14:00 | W02.5.3 | Correlated Statistical Model of Battery Capacity and Resistance and Management of Cell-to-Cell Variation in Multiple-Cell Battery Pack Donghwa Shin, Yeungnam University, KR |
| 14:30 | W02.5.4 | Battery Simulation in the ETAS LABCAR Environment Ingo Altmann, ETAS, DE |
| 15:00 | W02.6 | Poster Session / Coffee Break |
Philippe Coussy, Universite de Bretagne Sud / Lab-STICC, FR (Contact Philippe Coussy)
Nikil Dutt, University of California, Irvine, US (Contact Nikil Dutt)
Jeff Krichmar, University of California, US (Contact Jeff Krichmar)
Philippe Coussy, Universite de Bretagne Sud / Lab-STICC, FR (Contact Philippe Coussy)
Romain Brette, ENS, FR (Contact Romain Brette)
Yiran Chen, Dept. of Electrical and Computer Engineering University of Pittsburgh, US (Contact Yiran Chen)
Jorg Conradt, Technische Universitat Munchen, DE (Contact Jorg Conradt)
Nikil Dutt, University of California, Irvine, US (Contact Nikil Dutt)
Karlheinz Meier, Heidelberg University, DE (Contact Karlheinz Meier)
Vijaykrishnan Narayanan, Pennsylvania State University, US (Contact Vijaykrishnan Narayanan)
Steve Furber, University of Manchester, GB (Contact Steve Furber)
Narayan Srinivasa, HRL, US (Contact Narayan Srinivasa)
Marcel Eckert, Helmut-Schmidt-University Hamburg, DE (Contact Marcel Eckert)
Giacomo Indiveri, ETHZ, CH (Contact Giacomo Indiveri)
Romain Brette, ENS, FR (Contact Romain Brette)
Rajit Manohar, Cornell University, US (Contact Rajit Manohar)
Jorg Conradt, Technische Universitat Munchen, DE (Contact Jorg Conradt)
Steve Furber, University of Manchester, GB (Contact Steve Furber)
Anders Lansner, KTH, SE (Contact Anders Lansner)
Kristofor Carlson, University of California – Irvine, US (Contact Kristofor Carlson)
| Time | Label | Session |
|---|---|---|
| 08:30 | W03.1 | Session 0 (08:30 - 09:00) |
| 08:30 | W03.1.1 | The SPiNNaker Project Steve Furber, University of Manchester, GB |
| 09:00 | W03.2 | Session 1 (09:00 - 10:00) |
| 09:00 | W03.2.1 | On-line learning in real-time behaving neuromorphic systems Giacomo Indiveri, ETHZ, CH |
| 09:30 | W03.2.2 | The Brain simulator Romain Brette, ENS, FR |
| 10:00 | W03.3 | Break & Poster/demo session 1 (10:00 - 11:00) |
| 10:00 | W03.3.1 | TBD |
| 11:00 | W03.4 | Session 2 (11:00 - 12:00) |
| 11:00 | W03.4.1 | Digital Neuromorphic Systems Rajit Manohar, Cornell Univ., US |
| 11:30 | W03.4.2 | Computational Neuroscience for Technology: Event-based Vision Sensors and Information Processing Jorg Conradt, Technische Universitat Munchen, DE |
| 13:00 | W03.5 | Session 3 (13:00 - 14:30) |
| 13:00 | W03.5.1 | The design and design automation of memristor-based neuromorphic computing systems Yiran Chen, Dept. of Electrical and Computer Engineering University of Pittsburgh, US |
| 13:30 | W03.5.2 | Biological inspiration, functionality and hardware implementation aspects of BCPNN Anders Lansner, KTH, SE |
| 14:00 | W03.5.3 | Tools and Frameworks for Constructing Spiking Neural Network Models of Brain Circuits Kristofor Carlson, University of California – Irvine, US |
| 14:30 | W03.6 | Break & Poster/demo session 2 (14:30 - 16:00) |
| 14:30 | W03.6.1 | TBD |
| 16:13 | W03.7 | Session 4: Wrap-up & Close (16:00) |
Goerschwin Fey, Univ. of Bremen, DE (Contact Goerschwin Fey)
Emmanuelle Encrenaz-Tiphene, UPMC/LIP6, FR (Contact Emmanuelle Encrenaz-Tiphene)
Valeria Bertacco, University of Michigan, US (Contact Valeria Bertacco)
Lyes Benalycherif, STMicroelectronics, FR (Contact Lyes Benalycherif)
Ian Harris, University of Californa Irvine, US (Contact Ian Harris)
Masahiro Fujita, University of Tokyo, JP (Contact Masahiro Fujita)
Franco Fummi, Universita' di Verona, IT (Contact Franco Fummi)
Maksim Jenihhin, Tallinn University of Technology, EE (Contact Maksim Jenihhin)
Tun Li, National University of Defense Technology, School of Computer, CN (Contact Tun Li)
Eli Arbel, IBM, IL (Contact Eli Arbel)
Maksim Jenihhin, Tallinn University of Technology, EE (Contact Maksim Jenihhin)
| Time | Label | Session |
|---|---|---|
| 08:30 | W04.1 | Opening session |
| 08:30 | W04.1.1 | Opening session Goerschwin Fey1 and Emmanuelle Encrenaz-Tiphene2 1Univ. of Bremen, DE; 2UPMC/LIP6, FR |
| 08:40 | W04.2 | Invited talk 1 |
| 08:40 | W04.2.1 | Practical applications of hardware design understanding using formal methods Eli Arbel, IBM Research, Haifa, IL |
| 09:20 | W04.3 | Technical session 1 |
| 09:20 | W04.3.1 | SystemC-Based Loose Models: RTL Abstraction for Design Understanding Saif Abrar Syed, Maksim Jenihhin and Jaan Raik, Tallinn University of Technology, EE |
| 09:45 | W04.3.2 | Ecore Model Generation from SystemC/C++ Implementations Jannis Stoppe1 and Rolf Drechsler2 1Universität Bremen, DE; 2University of Bremen/DFKI GmbH, DE |
| 10:10 | W04.3.3 | Towards analysing feature locations through testing traces with BUT4Reuse Jabier Martinez1, Jan Malburg2, Tewfik Ziadi3 and Goerschwin Fey4 1SnT, University of Luxembourg, LU; 2University of Bremen, DE; 3LiP6, University Pierre and Marie Curie, FR; 4Univ. of Bremen, DE |
| 10:35 | W04.4 | Coffee break |
| 11:00 | W04.5 | Invited talk 2 |
| 11:00 | W04.5.1 | Assertion Mining Shobha Vasudevan, University of Illinois at Urbana-Champaign, US |
| 11:50 | W04.6 | Poster teasers |
| 11:50 | W04.6.1 | Poster teasers |
| 12:00 | W04.7 | Lunch |
| 13:00 | W04.8 | Technical session 2 |
| 13:00 | W04.8.1 | Learning Grammars for Assertion Creation from Natural Language Christopher Harris1 and Ian Harris2 1University of California Irvine, US; 2University of Californa Irvine, US |
| 13:25 | W04.8.2 | A Binding Method for Hierarchical Testability Using Results of Test Environment Generation Jun Nishimaki1, Toshinori Hosokawa2 and Hideo Fujiwara3 1Graduate School of Industrial Technology, Nihon University, JP; 2Nihon University, JP; 3Faculty of Informatics, Osaka Gakuin University, JP |
| 13:50 | W04.9 | Invited talk 3 |
| 13:50 | W04.9.1 | Parallelization of SystemC-TLM simulations, and modelling of time and power consumption Matthieu Moy, Verimag, Grenoble, FR |
| 14:40 | W04.10 | Poster session and coffee break |
| 14:40 | W04.10.1 | Is there a chance that computers understand analog design? Ramy Iskander1, Farakh Javid2 and marie-Minerve Louerat3 1Université Pierre et Marie Curie, FR; 2LIP6 Laboratory, FR; 3UNiversity Pierre & Marie Curie, LIP6, FR |
| 14:40 | W04.10.2 | Understanding the Heterogeneous Hardware: Do not forget the interconnection! Liliana Andrade1, Cédric Ben Aoun1, Benoît Vernay2, Torsten Maehne3, Francois Pecheux4 and marie-Minerve Louerat5 1UPMC - LIP6, FR; 2SU-UPMC/CNRS, LIP6, FR; 3Sorbonne Universités, UPMC Univ Paris 06, FR; 4UPMC/LIP6, FR; 5UNiversity Pierre & Marie Curie, LIP6, FR |
| 14:40 | W04.10.3 | AMS System-level exploration and verification using UVM in SystemC and SystemC AMS Yao Li1, Zhi Wang1, Francois Pecheux2, marie-Minerve Louerat3, Martin Barnasconi4, Thilo Voertler5 and Karsten Einwich5 1UPMC-LIP6, FR; 2UPMC/LIP6, FR; 3UNiversity Pierre & Marie Curie, LIP6, FR; 4NXP Semiconductors, NL; 5Fraunhofer IIS/EAS, DE |
| 14:40 | W04.10.4 | Debugging Hardware Designs Using Dynamic Dependency Graphs Jan Malburg1, Alexander Finder2 and Goerschwin Fey3 1University of Bremen, DE; 2Aventon GmbH, DE; 3Univ. of Bremen, DE |
| 15:30 | W04.11 | Technical session 3 |
| 15:30 | W04.11.1 | A simulator to understand the effects of fault injection attacks on a microcontroller Nicolas Moro1, Karine Heydemann2, Bruno Robisson3 and Emmanuelle Encrenaz-Tiphene4 1CEA, FR; 2LIP6 / University Pierre et Marie Curie, FR; 3CEA-Leti, FR; 4UPMC/LIP6, FR |
| 15:55 | W04.12 | Panel |
| Panelists: Panelists: Lyes Benalycherif1, Dominique Borrione2, Franco Fummi3 and Jaan Raik4 1STMicroelectronics, FR; 2TIMA, FR; 3Universita' di Verona, IT; 4Tallinn University of Technology, Department of Computer Engineering, EE |
Saqib Khursheed, University of Liverpool, GB (Contact Saqib Khursheed)
Pascal VIVET, CEA-LETI, FR (Contact Pascal VIVET)
Françoise von Trapp, 3D InCites, US (Contact Françoise von Trapp)
Programme Committee ChairsChristian Weis, Microelectronic System Research Group, DE (Contact Christian Weis)
, , (Contact )
Erik Jan Marinissen, IMEC, BE (Contact Erik Jan Marinissen)
Qiang Xu, The Chinese University of Hong Kong, HK (Contact Qiang Xu)
Bjørn B. Larsen, NTNU, NO (Contact Bjørn B. Larsen)
Andy Heinig, Fraunhofer IIS/EAS, DE (Contact Andy Heinig)
| Time | Label | Session |
|---|---|---|
| 08:15 | W05.1 | SESSION 1: OPENING and 1st Keynote Chair: |
| 08:15 | W05.1.1 | Welcome Address Pascal VIVET, CEA-Leti, FR |
| 08:20 | W05.1.2 | Keynote: "Computing in 3D" Paul Franzon, North Carolina State University, US Abstract:3DIC technology refers to stacking and interconnecting chips and substrates ("interposers") with Through Silicon Vias (TSVs). Industry is gearing up for widespread introduction of this technology with the 22 nm node. At NCSU, we have been pursuing a range of approaches to enable low power computing. As well as 3DIC these include heterogeneous computing, powered optimized SIMD units, optimized memory hierarchies, and MPI with post-silicon customized interconnect. Heterogeneous computing refers to the concept of building a mix of CPUs and memories that in turn enable in-situ tuning of the compute load to the compute resources. We introduce the concept of Fast Thread Migration using 3DIC technologies. We present the design of a power optimized SIMD unit in which over half of the power is employed in the FP units. A parallel computer is built using an MPI paradigm. Codes are analyzed so that the MPI interconnect can be power optimized post-silicon. Emerging 3D memories have potential to be employed as Level 2 and Level 3 caches, and this is explored using the Tezzaron 3D memory. As scaling and power optimization occurs, the main memory increasingly dominates the power consumption. Main memory redesign, using both DRAM and RRAM, is explored to show potential for an order of magnitude reduction. Possible extensions to Cortical Processing are discussed. Bio:Paul D. Franzon is currently a Distinguished Alumni Professor of Electrical and Computer Engineering at North Carolina State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and three companies he cofounded, Communica, LightSpin Technologies and Polymer Braille Inc. His current interests center on the technology and design of complex microsystems incorporating VLSI, MEMS, advanced packaging and nano-electronics. He has lead several major efforts and published over 300 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, received the Alcoa Research Award in 2005, and the Board of Governors Teaching Award in 2014. He served with the Australian Army Reserve for 13 years as an Infantry Solider and Officer. He is a Fellow of the IEEE. |
| 09:00 | W05.2 | Special Session: "3D Memories" Chair: What are current 3D memory technologies offering? This special session will put a spot on TSV stacking for high bandwidth memories, the influence of 3D memory on computing and real facts about 3D memories. |
| 09:00 | W05.2.1 | TSV stacking design and packaging for high bandwidth memories with 1GHz sampling digitized noize monitor Kazuki Fukuoka, Renesas Electronics, JP |
| 09:20 | W05.2.2 | How 3D Memory is Changing Computing Robert Patti, Tezzaron Semiconductor, US |
| 09:40 | W05.2.3 | 3D Memories: Facts and Fiction Andreas Hansson, ARM Ltd, GB |
| 10:00 | W05.2.4 | Poster Session and Coffee Break For the list of posters see below. |
| 10:30 | W05.3 | SESSION 2: Invited Talk and Panel Moderator: |
| Panelists: Speaker: Krishnendu Chakrabarty, Duke University, US Panelists: Brendan Farley1, Denis Dutoit2, Hsien-Hsin S. Lee3, Geert Van der Plas4 and Mustafa Badaroglu5 1XILINX, US; 2CEA LETI, FR; 3TSMC, TW; 4IMEC, BE; 5Qualcomm, US It's official. Memory has moved into the interposer and 3D stacked IC space with many companies announcing stacked Memory products for high-end computing applications including networking, data servers, and gaming. But does this solve the memory bandwidth issue across the board? Will we see similar memory stacks in consumer products? And if so, what has to happen? What requirements transpire for TSV-based interconnects and interposers? This provocative panel (with interactive audience participation!) will offer perspectives from R&D, manufacturing, and end-users. | ||
| 13:00 | W05.4 | Special Session: "Die-package co-design benefits and challenges" Chair: Interposer and 3D-IC designs pack more functionality into a smaller space (cm3). While saving total power dissipation (in Watts) they significantly increase power density (in Watts/cm3). To keep the junction temperatures of the closely packed dies within limits and guarantee functionality, parametrics and reliability, all at an acceptable unit cost, the IC package and its components play a major role. Only by considering the package characteristics already during the IC design process, an optimal solution can be found. Close cooperation between EDA tools developers, IC designers and IC manufacturers is required to develop and agree upon a user friendly and cost-effective die-package co-design environment. The presenters will detail the current challenges and outline key benefits of an emerging die-package co-design methodology. After this special session, there is time for 10 minutes wrap-up and discussion. |
| 13:00 | W05.4.1 | The 3D-IC EcoSystem today and how to strengthen it further Herb Reiter, EDA2ASIC, US |
| 13:20 | W05.4.2 | Data Handling for Chip-Package-Board Co-Design and Design Rule Check Andy Heinig, Fraunhofer IIS/EAS, DE |
| 13:40 | W05.4.3 | Silicon-Package Co-Design Challenges from 2D to 3D Georg Kimmich, STMicrolectronics, FR |
| 14:00 | W05.4.4 | IC design aspects of die-package co-design John Ferguson, Mentor Graphics Corp, US |
| 14:30 | W05.4.5 | Poster Session and Coffee Break For the list of posters see below. |
| 15:00 | W05.5 | SESSION 3: Test and Technology Challenges for 3D ICs Chair: |
| 15:00 | W05.5.1 | Impact of Multi-Vt technique in Eliminating Thermal Runaway during Testing of 3D chips Seetal Potluri1, Satya Trinadh Adireddy2, S. G. Singh2, Sobhan Babu Ch.2 and Kamakoti Veezhinathan1 1IIT Madras, IN; 2IIT Hyderabad, IN |
| 15:18 | W05.5.2 | 3D-IC Session-based vs Session-less Test Scheduling: a case study Marie-Lise Flottes, Joao Azevedo, Giorgio Di Natale and Bruno Rouzeyre, LIRMM, FR |
| 15:36 | W05.5.3 | 3D IC Test through Low Noise Power Line Methodology Alberto Pagani and Allessandro Motta, STMicroelectronics, IT |
| 15:54 | W05.5.4 | Broadband Metal-Insulator-Metal Capacitors on Silicon Interposer for Low Impedance Power Distribution Network Nao Ueda1, Cesar Roda Neve2, Mikael Detalle2, Eric Beyne2, Geert Van der Plas2 and Makoto Nagata1 1Kobe University, JP; 2IMEC, BE |
| 16:12 | W05.5.5 | A TSV to TSV, A TSV to Metal Interconnects, and A TSV to Active Device Coupling Capacitance: Analysis and Recommendations Khaled Mohamed, Mentor, EG |
| 16:28 | W05.6 | Poster List |
| 16:28 | W05.6.1 | A New Contactless Substrate Shipper for ultrathin, 3D, lensed or bumbed Wafers Jorgen Lundgren, Entegris GmbH, DE |
| 16:28 | W05.6.2 | Test and reconfiguration of TSV defect in 3D-IC Mohamed Benabdeladhim, Dept. of Physics, Faculty of Science of Monastir, TN |
| 16:28 | W05.6.3 | MEMS Sensor and IC Developement: Innovative Tools, Methods, Design Practive Grzegorz Janczyk and Tomasz Bieniek, ITE Warsaw, PL |
| 16:28 | W05.6.4 | Pathfinding for 3D Designs Based on Interposer Vladimir Pasca1, Claudia Rusu1, Meycène Toumi2 and Pascal VIVET3 1Atrenta, Grenoble, FR; 2CEA Leti, FR; 3CEA-Leti, FR |
| 16:28 | W05.6.5 | Modeling of Rentention Time Errors of 3D-stacked DRAMs based on Real Chip Measurements Christian Weis1, Matthias Jung2, Pascal VIVET3, Cristiano Santos4 and Norbert Wehn2 1Microelectronic System Research Group, DE; 2University of Kaiserslautern, DE; 3CEA-Leti, FR; 4CEA-LETI, Grenoble and UFRGS, Porto Alegre, Brazil, FR |
Lorena Anghel, TIMA, FR (Contact Lorena Anghel)
Olivier Heron, CEA, FR (Contact Olivier Heron)
Elena Gramatova, University of Technology in Bratislava, SK (Contact Elena Gramatova)
Maksim Jenihhin, Tallinn University of Technology, EE (Contact Maksim Jenihhin)
Oliver Bringmann, University of Tübingen, DE (Contact Oliver Bringmann)
Florian Cacho, STMicroelectronics, FR (Contact Florian Cacho)
Luigi Dilillo, LIRMM, FR (Contact Luigi Dilillo)
Adrian Evans, Iroc, FR (Contact Adrian Evans)
Dimitris Gizopoulos, University of Athens, Department of Informatics & Telecommunications, GR (Contact Dimitris Gizopoulos)
Said Hamdioui, Delft University of Technology, NL (Contact Said Hamdioui)
Domenik Helms, OFFIS, DE (Contact Domenik Helms)
Viacheslav Izosimov, The Royal Institute of Technology (KTH), SE (Contact Viacheslav Izosimov)
Artur Jutman, Testonica Lab, EE (Contact Artur Jutman)
Zdenek Kotasek, FIT VUT in Brno, CZ (Contact Zdenek Kotasek)
Hans Manhaeve, Ridgetop Europe, BE (Contact Hans Manhaeve)
Alberto Nannarelli, DTU, DK (Contact Alberto Nannarelli)
Ozcan Ozturk, Bilkent University, TR (Contact Ozcan Ozturk)
Zdenek Pliva, Technical University Liberec, CZ (Contact Zdenek Pliva)
Salvatore Pontarelli, University of Rome "Tor Vergata", IT (Contact Salvatore Pontarelli)
Dhiraj Pradhan, University of Bristol, GB (Contact Dhiraj Pradhan)
Mihalis Psarakis, University of Piraeus, GR (Contact Mihalis Psarakis)
Jaan Raik, Tallinn University of Technology, Department of Computer Engineering, EE (Contact Jaan Raik)
Chiara Sandionigi, CEA, FR (Contact Chiara Sandionigi)
Andreas Steininger, Vienna University of Technology, AT (Contact Andreas Steininger)
Walter Stechele, Technische Universität München, DE (Contact Walter Stechele)
Viera Stopjakova, FEI STU, SK (Contact Viera Stopjakova)
Mehdi Tahoori, KIT, DE (Contact Mehdi Tahoori)
Elena Vatajelu, Politecnico de Torino, IT (Contact Elena Vatajelu)
Heinrich T. Vierhaus, BTU Cottbus, DE (Contact Heinrich T. Vierhaus)
Marco Ottavi, University of Roma, IT (Contact Marco Ottavi)
| Time | Label | Session |
|---|---|---|
| 08:30 | W06.1 | Opening session Co-Chairs: |
| 08:30 | W06.1.1 | Welcome presentation |
| 08:40 | W06.2 | Keynote Chair: |
| 08:40 | W06.2.1 | Reliability Challenges for Cyber-Physical Systems Zebo Peng, Linköping University, SE |
| 09:40 | W06.3 | Paper session I: Fault Tolerance and Test Techniques for Low Power Design Chair: |
| 09:40 | W06.3.1 | BTI Analysis for High Performance and Low power SRAM Sense Amplifier Designs Innocent Agbo1, Mottaqiallah Taouil1, Said Hamdioui2, Halil Kukner3, Pieter Weckx4, Praveen Raghavan3 and Francky Catthoor3 1Delft UT, NL; 2Delft University of Technology, NL; 3IMEC, BE; 4IMEC vzw, BE |
| 10:00 | W06.3.2 | Power-Aware Online Detection of Hardware Defects for Manycore Systems with DVFS Support Mohammad-Hashem Haghbayan1, Amir-Mohammad Rahmani2, Mohammad Fattah1, Pasi Liljeberg1, Juha Plosila1 and Hannu Tenhunen1 1University of Turku, FI; 2Turku Center for Computer Science (TUCS), Finland, FI |
| 10:20 | W06.4 | Poster session and coffee break |
| 10:20 | W06.4.1 | A new adaptive system for software-based test generation of processors Jan Hudec1 and Elena Gramatova2 1Slovak UT, SK; 2University of Technology in Bratislava, SK |
| 10:20 | W06.4.2 | Radiation Impact on Mechanical Application Driven by FPGA-based Controller Jakub Podivínský1, Marcela Simkova2 and Zdenek Kotasek2 1Brno UT, CZ; 2FIT VUT in Brno, CZ |
| 10:20 | W06.4.3 | A Fault Resilient Routing Algorithm for Heterogeneous 3D NoCs Masoumeh Ebrahimi1, Ronak Salamat2, Nader Bagherzadeh3 and Masoud Daneshtalab4 1university of Turku, FI; 2Univ. California, US; 3University of California Irvine, US; 4UTU, FI |
| 10:20 | W06.4.4 | Mixed Criticality Metric for Safety-Critical Cyber-Physical Systems on Multi-Core Architectures Viacheslav Izosimov1 and Erik Levholt2 1The Royal Institute of Technology (KTH), SE; 2Svenska Grindmatriser AB, SE |
| 10:20 | W06.4.5 | Secured Connectivity of Distributed Agents in Presence of Many NoC Fault. Mohammad Fattah, Pasi Liljeberg and Juha Plosila, University of Turku, FI |
| 10:20 | W06.4.6 | On Aging of Latches' Robustness Martin Omana1, Luz Antuanet Adanaque Infante1, Cecilia Metra2 and Daniele Rossi3 1Univ. Bologna, IT; 2Università di Bologna, IT; 3Univ. Southampton, GB |
| 10:20 | W06.4.7 | Influence of Reconfiguration Techniques for Dynamically Scheduled Superscalar Processors on Power Consumption Tobias Koal1, Robert Karas1, Heinrich Theodor Vierhaus1 and Mario Schölzel2 1BTU Cottbus, DE; 2IHP and Univ. Potsdam, DE |
| 10:20 | W06.4.8 | Extended Checkers for Control Part of Routers in Network-on-Chips Ranganathan Hariharan1, Behrad Niazmand1, Thomas Hollstein2, Jaan Raik2 and Gert Jervan1 1Tallinn UT, EE; 2Tallinn University of Technology, EE |
| 10:20 | W06.4.9 | Simulation framework for optimizing SRAM power consumption under reliability constraint Florian Cacho1, Erwan Piriou2, Olivier Heron3 and Vincent Huard1 1STMicroelectronics, FR; 2CEA LIST, FR; 3CEA, FR |
| 11:20 | W06.5 | Paper session II: Verification and Test Techniques for Reliable Design Chair: |
| 11:20 | W06.5.1 | Evaluation of Failures Masking Across the Software Stack Thiago Santini1, Paolo Rech1, Anderson Luiz Sartor2, Ulisses Brisolara Corrêa3, Luigi Carro4 and Flavio Wagner4 1Federal University of Rio Grande do Sul, BR; 2Federal University of Rio Grande do Sul (UFRGS), BR; 3Instituto Federal de Educação, Ciência e Tecnologia Sul-rio-grandense, BR; 4UFRGS, BR |
| 11:40 | W06.5.2 | A novel Formal Verification Framework for future MPSoC Architectures Christian Schöler1, René Krenz-Baath1 and Roman Obermaisser2 1Hochschule Hamm-Lippstadt, DE; 2University of Siegen, DE |
| 12:00 | W06.6 | Lunch |
| 13:00 | W06.7 | Invited talk Chair: |
| 13:00 | W06.7.1 | Technology Scaling and Reliability Challenges in the Multicore Era Vincent Huard, STMicroelectronics, FR |
| 13:40 | W06.8 | Paper session III: Dependable Systems and Components Chair: |
| 13:40 | W06.8.1 | Efficient online testing of an array of reconfigurable RISC Processors S. Pagliarini1, Salvatore Pontarelli2, JImson Mathew3, Dhiraj K. Pradhan3, Ioannis Sourdis4, D.A. Khan5, A. Malek5, S. Tzilis5, Georgios Smaragdos6 and Christos Strydis6 1Univ. of Bristol, GB; 2University of Rome "Tor Vergata", IT; 3University of Bristol, GB; 4Chalmers Univeristy of Technology, SE; 5Chalmers UT, SE; 6Erasmus Medical Center, NL |
| 14:00 | W06.8.2 | Measuring and Identifying Aging-Critical Paths in FPGAs Petr Pfeifer1, Jaan Raik2, Maksim Jenihhin2, Raimund Ubar2 and Zdenek Pliva1 1Technical University Liberec, CZ; 2Tallinn University of Technology, EE |
| 14:20 | W06.8.3 | Dynamic Voltage Scaling with Fault-Tolerance for Lifetime Operation Jorge Semião1, Carlos Leong2, Ruben Cabral2, Marcelino Santos2, Isabel Teixeira2 and Paulo Teixeira2 1Univ. Algarve, PT; 2INESC-ID, PT |
| 14:40 | W06.9 | Coffee break |
| 15:00 | W06.10 | Paper session IV: Dependable Multicore Systems and Processors Testing and Self-repair Chair: |
| 15:00 | W06.10.1 | Software-Based Self-Repair for Heterogenous Multi-Core Systems Sebastian Müller1, Heinrich Theodor Vierhaus1 and Mario Schölzel2 1BTU Cottbus, DE; 2IHP and Univ. Potsdam, DE |
| 15:20 | W06.10.2 | Universal Pseudo-random Generation of Assembler Codes for Processors Ondrej Cekan, Marcela Simkova and Zdenek Kotasek, FIT VUT in Brno, CZ |
| 15:40 | W06.10.3 | Exploring check-pointing and rollback recovery under selective SBST in Chip Multi-Processors Michael Skitsas1, Chrysostomos Nicopoulos2 and Maria Michael2 1Univ. Cyprus, CY; 2University of Cyprus, CY |
| 16:00 | W06.11 | Discussion and Closing session Co-Chairs: |
| 16:00 | W06.11.1 | Discussion and Closing session |
James Alfred Walker, University of York, GB (Contact James Alfred Walker)
Andy M. Tyrrell, University of York, GB (Contact Andy M. Tyrrell)
Martin A. Trefzer, University of York, GB (Contact Martin A. Trefzer)
Simon J. Bale, University of York, GB (Contact Simon J. Bale)
| Time | Label | Session |
|---|---|---|
| 08:30 | W07.1 | Opening Session |
| 08:30 | W07.1.1 | Opening Session Andy M. Tyrrell, University of York, GB |
| 08:40 | W07.2 | Invited Keynote 1 Chair: |
| 08:40 | W07.2.1 | PAnDA: Programmable Analogue and Digital Array James Alfred Walker, University of York, GB |
| 09:20 | W07.3 | Session 1 Chair: Short talks of accepted abstracts. |
| 09:20 | W07.3.1 | Thermal-aware Adaptive Energy Minimization of OpenMP Parallel Applications Rishad Shafik, Anup Das, Sheng Yang, Geoff Merrett and Bashir Al-Hashimi, University of Southampton, GB |
| 09:30 | W07.3.2 | Characterization of Random Telegraph Noise and its impact on reliability of SRAM sense amplifiers Javier Martin-Martinez1, Javier Diaz Fortuny1, Montserrat Nafria Maqueda1, Xavier Aymerich Humet1, Elisenda Roca Moreno2, Francisco Fernandez3 and Antonio Rubio4 1Universitat Autònoma de Barcelona (UAB), ES; 2de Microelectrónica de Sevilla, CSIC and Universidad de Sevilla, ES; 3IMSE, CSIC and University of Sevilla, ES; 4Universitat Politècnica de Catalunya (UPC), ES |
| 09:40 | W07.3.3 | Reliable Computation with Unreliable Computers Kier Dugan1, Andrew D. Brown1, Jeff S. Reeve1, Rob M. Mills1 and Steve Furber2 1University of Southampton, GB; 2University of Manchester, GB |
| 09:50 | W07.3.4 | A Multi Cycle Capture Test Generation Method for Low Capture Power Dissipation Hiroshi Yamazaki1, Jun Nishimaki2, Toshinori Hosokawa1 and Masayoshi Yoshimura3 1Nihon University, JP; 2Graduate School of Industrial Technology, Nihon University, JP; 3Kyoto Sangyo University, JP |
| 10:00 | W07.3.5 | Probabilistic Analysis of Power and Temperature Under Process Variation for Electronic System Design Ivan Ukhov, Petru Eles and Zebo Peng, Linköping University, SE |
| 10:10 | W07.3.6 | Measuring the Impact of Variability on the PAnDA Architecture Simon J. Bale, James Alfred Walker, Martin A. Trefzer and Andy M. Tyrrell, University of York, GB |
| 10:30 | W07.4 | Coffee/Tea Break |
| 10:30 | W07.4.1 | Coffee/Tea Break |
| 11:00 | W07.5 | Invited Keynote 2 Chair: |
| 11:00 | W07.5.1 | Predictive Technology for Advanced Node Design Exploration Robert Aitken, ARM, US |
| 11:40 | W07.6 | Session 2 Chair: Short talks of accepted abstracts. |
| 11:40 | W07.6.1 | Abstracting TCAD models above the circuit level Domenik Helms1, Reef Eilers1, Malte Metzdorf1 and Wolfgang Nebel2 1OFFIS, DE; 2Oldenburg University and OFFIS, DE |
| 11:50 | W07.6.2 | On the Hardware Trojans Detection, using Mixed-Signal ICs Georgina Kalogeridou1, Nicolas Sklavos2, Andew W. Moore1 and Odysseas Koufopavlou3 1Computer Laboratory, University of Cambridge, GB; 2Technological Educational Institute of Patras, GR; 3Electrical & Computer Engineering Department, University of Patras, HELLAS, GR |
| 12:00 | W07.7 | Lunch Break |
| 12:00 | W07.7.1 | Lunch Break |
| 13:00 | W07.8 | Invited Keynote 3 Chair: |
| 13:00 | W07.8.1 | Factoring variability in the TCAD based Design-Technology Co-Optimisation Asen Asenov, University of Glasgow, GB |
| 13:40 | W07.9 | Session 3 Chair: Short talks of accepted abstracts. |
| 13:40 | W07.9.1 | Statistical Lifetime Analysis in Memristive Crossbar Peyman Pouyan1, Esteve Amat1 and Antonio Rubio2 1Universitat Politècnica de Catalunya (UPC), Barcelona, ES; 2Universitat Politècnica de Catalunya (UPC), ES |
| 13:50 | W07.9.2 | Fast Parametric Fault Modeling of Nanoscale Integrated Circuits Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon and Giovanni De Micheli, EPFL, CH |
| 14:00 | W07.9.3 | Reliability Analysis of Comparators Illani Mohd Nawi, Basel Halak and Mark Zwolinski, University of Southampton, GB |
| 14:10 | W07.9.4 | High-Sigma Performance Analysis using Multi-Objective Evolutionary Algorithms James Alfred Walker, Simon J. Bale, Martin A. Trefzer and Andy M. Tyrrell, University of York, GB |
| 14:30 | W07.10 | Coffee/Tea Break |
| 14:30 | W07.10.1 | Coffee/Tea Break |
| 15:00 | W07.11 | Invited Keynote 4 Chair: |
| 15:00 | W07.11.1 | Configurable Analogue Design: Conquering Variability in an Uncertain World Peter Wilson, university of southampton, GB |
| 15:40 | W07.12 | Networking Session Chair: |
| 15:40 | W07.12.1 | Poster presentations of the short talks from Sessions 1, 2 & 3. |
| 16:20 | W07.13 | Closing Session |
| 16:20 | W07.13.1 | Closing Session Andy M. Tyrrell, University of York, GB |
Dietmar Fey, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE (Contact Dietmar Fey)
Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE (Contact Frank Hannig)
Anton Lokhmotov, ARM Research, Cambridge, GB (Contact Anton Lokhmotov)
Albert Cohen, INRIA, FR (Contact Albert Cohen)
Andrew Davison, Imperial College London, GB (Contact Andrew Davison)
Diana Goehringer, Ruhr-University Bochum, DE (Contact Diana Goehringer)
Richard Membarth, DFKI, Saarbrücken, DE (Contact Richard Membarth)
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David Thomas, Imperial College London, GB (Contact David Thomas)
Zain Ul-Abdin, Halmstad University, SE (Contact Zain Ul-Abdin)
Dong Ping Zhang, AMD, Sunnyvale, CA, US (Contact Dong Ping Zhang)
| Time | Label | Session |
|---|---|---|
| 08:30 | W08.1 | Welcome and Introduction |
| 08:30 | W08.1.1 | Welcome and Introduction Dietmar Fey and Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE |
| 08:45 | W08.2 | Keynote Speech 1 |
| 08:45 | W08.2.1 | Vision Sensors with Pixel-Parallel Cellular Processor Arrays Piotr Dudek, University of Manchester, GB |
| 09:30 | W08.3 | Session 1: Smart Vision Architectures and Heterogeneous MPSoCs Chair: |
| 09:30 | W08.3.1 | Invited Talk: Approaching Application Requirements with Adaptive Heterogeneous MPSoC Diana Goehringer, Ruhr-University Bochum, DE |
| 10:00 | W08.3.2 | Estimating the Potential Speedup of Computer Vision Applications on Embedded Multiprocessors Vítor Schwambach1, Cleyet-Merle Sebastien2, Alain Issard1 and Stéphane MANCINI3 1STMicroelectronics, FR; 2ST Micorelectronics, FR; 3TIMA Laboratory, FR |
| 10:30 | W08.4 | Coffee Break |
| 11:00 | W08.5 | Session 2: Domain-Specific Languages and Scheduling Techniques for Heterogeneous Computing Chair: |
| 11:00 | W08.5.1 | Invited Talk: AnyDSL: A Compiler-Framework for Domain-Specific Libraries & Languages (DSLLs) Richard Membarth, DFKI, Saarbrücken, DE |
| 11:30 | W08.5.2 | A Comparative Study of Scheduling Techniques for Multimedia Applications on SIMD Pipelines Mehmet Ali Arslan, Flavius Gruian and Krzysztof Kuchcinski, Lund University, SE |
| 12:00 | W08.6 | Lunch |
| 13:00 | W08.7 | Keynote Speech 2 |
| 13:00 | W08.7.1 | DreamCam: A modular FPGA-Based Smart Camera Architecture François Berry, Université Blaise Pascal Clermont-Ferrand, FR |
| 13:45 | W08.8 | Session 3: Cameras and Accelerators Chair: |
| 13:45 | W08.8.1 | Invited Talk: Accelerated Image Processing: Experience from the CARP Project Elnar Hajiyev, Realeyes, GB |
| 14:15 | W08.8.2 | Automatic Optimization of Hardware Accelerators for Image Processing Oliver Reiche, Konrad Häublein, Marc Reichenbach, Frank Hannig, Jürgen Teich and Dietmar Fey, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE |
| 14:45 | W08.9 | Fast-Forward Presentation of Posters |
| 14:45 | W08.9.1 | Efficient Implementation of Givens QR Decomposition on VLIW DSP Architecture for Orthogonal Matching Pursuit Image Reconstruction Mohamed Najoui, Anas Hatim, Mounir Bahtat and Said Belkouch, University of Cadi Ayyad, Marrakech, MA |
| 14:49 | W08.9.2 | A Graph-Partition Based Scheduling Policy for Heterogeneous Architectures Hao Wu, Daniel Lohmann and Wolfgang Schröder-Preikschat, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE |
| 14:53 | W08.9.3 | A Holistic Approach for Modelling and Synthesis of Image Processing Applications to Heterogeneous Computing Christian Hartmann, Anna Yupatova, Marc Reichenbach, Dietmar Fey and Reinhard German, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE |
| 14:57 | W08.9.4 | Generation and Validation of Custom Multiplication IP Blocks from the Web Minas Dasygenis, Department of Informatics and Telecommunications Engineering, University of Western Macedonia, Greece, GR |
| 15:00 | W08.10 | Coffee Break and Posters |
| 16:00 | W08.11 | Session 4: Technologies for Smart Sensors Chair: |
| 16:00 | W08.11.1 | Invited Talk: Smart and Ultrafast CMOS Image Sensors: The Dream Come True with 3D Heterogeneous Microelectronic Wilfried Uhring, Université de Strasbourg, FR |
| 16:30 | W08.11.2 | Concept for a CMOS Image Sensor Suited for Analog Image Pre-Processing Lan Shi1, Christopher Soell1, Andreas Baenisch1, Robert Weigel1, Jürgen Seiler1 and Thomas Ussmueller2 1Friedrich-Alexander-Universität Erlangen-Nürnberg, DE; 2University of Innsbruck, AT |
| 17:00 | W08.12 | Closing |
| 17:00 | W08.12.1 | Closing |
Gabriela Nicolescu, Polytechnique Montréal, CA (Contact Gabriela Nicolescu)
Jiang Xu, Hong Kong University of Science and Technology, CN (Contact Jiang Xu)
Sébastien Le Beux, Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, FR (Contact Sébastien Le Beux)
Mahdi Nikdast, Polytechnique Montréal, CA (Contact Mahdi Nikdast)
Invited SpeakersAntonio La Porta, IBM, Zurich Research Laboratory, CH (Contact Antonio La Porta)
Davide Bertozzi, University of Ferrara, IT (Contact Davide Bertozzi)
Fabiano Hessel, PUCRS, BR (Contact Fabiano Hessel)
Ian O'Connor, Lyon Institute of Nanotechnology, FR (Contact Ian O'Connor)
John Ferguson, Mentor Graphics Corp, US (Contact John Ferguson)
Josè Flich, Universidad Politecnica de Valencia, ES (Contact Josè Flich)
Olivier Sentieys, INRIA - University of Rennes 1, FR (Contact Olivier Sentieys)
Sandro Bartolini, Università di Siena, IT (Contact Sandro Bartolini)
Sebastien Cremer, STMicroelectronics, FR (Contact Sebastien Cremer)
Yaoyao Ye, Huawei Technologies Co. Ltd., CN (Contact Yaoyao Ye)
Yvain Thonnart, CEA, LETI, MINATEC, FR (Contact Yvain Thonnart)
| Time | Label | Session |
|---|---|---|
| 08:30 | W09.1 | Introduction Chair: |
| 08:30 | W09.1.1 | Introduction to OPTICS workshop Gabriela Nicolescu1 and Mahdi Nikdast2 1Ecole Polytechnique de Montreal, CA; 2Ecole Polytechnique de Montréal, CA |
| 08:40 | W09.2 | Morning Session on System Design, Architecture, Modelling, and Applications Chair: |
| 08:40 | W09.2.1 | Scalable Optical Interconnects for Computing Systems and the Need for Electro-Optical Integration Antonio La Porta, IBM, Zurich Research Laboratory, CH |
| 09:15 | W09.2.2 | Towards a Vertically Integrated Synthesis Flow for Predictable Design of Wavelength-Routed Optical NoCs Davide Bertozzi, University of Ferrara, IT |
| 09:35 | W09.2.3 | Inter/Intra-Chip Optical Networks: Opportunities and Challenges Jiang Xu, Hong Kong University of Science and Technology, CN |
| 09:55 | W09.2.4 | A Force-Directed Placement Algorithm for 3D Optical Networks-on-Chip Anja von Beuningen and Ulf Schlichtmann, Technische Universität München, DE |
| 10:15 | W09.2.5 | System-Level Design Space Exploration for SoCs Integrating Optical Networks on Chip Fabiano Hessel, Pontifícia Universidade Católica do Rio Grande do Sul, BR |
| 10:35 | W09.2.6 | Coffee break |
| 11:00 | W09.2.7 | Meet in the Middle: Leveraging Optical Interconnection Opportunities in Chip Multi Processors Sandro Bartolini, Università di Siena, IT |
| 11:20 | W09.2.8 | Electronic vs Photonic NoCs: Should They Compete or Collaborate? Josè Flich, Universidad Politecnica de Valencia, ES |
| 11:40 | W09.2.9 | Bandwidth Requirements in Manycore Architectures: What Can 3D Bring? Olivier Sentieys, INRIA - University of Rennes 1, FR |
| 12:00 | W09.2.10 | Lunch |
| 13:00 | W09.3 | Afternoon Session on Silicon Photonics Devices, Circuits, and Challenges Chair: |
| 13:00 | W09.3.1 | Building a Scalable Design Environment for Silicon Photonics through PDKs John Ferguson, Mentor Graphics Corp, US |
| 13:35 | W09.3.2 | Recent Development of Si-Photonics in 300mm Fab Sebastien Cremer, STMicroelectronics, FR |
| 13:55 | W09.3.3 | Silicon Photonics for Interposer Yvain Thonnart, CEA, LETI, MINATEC, FR |
| 14:15 | W09.3.4 | Thermal Management of Optical Interconnects Yaoyao Ye, Huawei Technologies Co. Ltd., CN |
| 14:35 | W09.3.5 | Coffee break |
| 15:00 | W09.3.6 | Parametric Exploration of Vertical Tapered Coupler for 3D Optical Interconnection Romain Schuster1, Alberto Parini2 and Gaetano Bellanca2 1Telecom Bretagne, Campus Brest, FR; 2University of Ferrara, IT |
| 15:20 | W09.3.7 | The Last Mile? Remaining Challenges in Optical Interconnect Ian O'Connor, Lyon Institute of Nanotechnology, FR |
| 15:30 | W09.4 | Panel Moderator: |
| Panelists: Panelists: John Ferguson1, Antonio La Porta2, Gabriela Nicolescu3, Olivier Sentieys4, Davide Bertozzi5 and Jiang Xu6 1Mentor Graphics Corp, US; 2IBM, Zurich Research Laboratory, CH; 3Ecole Polytechnique de Montreal, CA; 4INRIA - University of Rennes 1, FR; 5University of Ferrara, IT; 6Hong Kong University of Science and Technology, CN | ||
| 16:20 | W09.5 | Concluding Remarks and Closing Session Chair: |
| 16:20 | W09.5.1 | Concluding remarks Sébastien Le Beux, Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, FR |
| 16:30 | W09.5.2 | Closing |
Giorgio Di Natale, LIRMM, FR (Contact Giorgio Di Natale)
General Vice-ChairIlia Polian, University of Passau, DE (Contact Ilia Polian)
Programme Committee ChairBossuet Lilian, University of St. Etienne, FR (Contact Bossuet Lilian)
Programme Committee Vice-ChairNicolas Sklavos, Technological Educational Institute of Patras, GR (Contact Nicolas Sklavos)
| Time | Label | Session |
|---|---|---|
| 08:30 | W10.1 | Opening Session |
| 08:30 | W10.1.1 | TRUDEVICE: Trustworthy Manufacturing and Utilization of Secure Devices Giorgio Di Natale1, Ilia Polian2, Bossuet Lilian3 and Nicolas Sklavos4 1LIRMM, FR; 2University of Passau, DE; 3University of St. Etienne, FR; 4KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR |
| 08:45 | W10.2 | Keynote Talk 1 Chair: |
| 08:45 | W10.2.1 | The pros and cons of technological dispersion for security: PUF, TRNG and side-channel countermeasures Jean-Luc Danger, Télécom ParisTech, FR |
| 09:30 | W10.3 | Session 1 Chair: |
| 09:30 | W10.3.1 | Analysis and utilization of deviations in RO-PUFs under altered FPGA designs Linus Feiten, Tobias Martin and Bernd Becker, University of Freiburg, DE |
| 09:45 | W10.3.2 | Ring Oscillators Analysis for FPGA Security Purposes Mario Barbareschi1, Lionel TORRES2 and Giorgio Di Natale3 1University of Naples Federico II, IT; 2LIRMM - University Montpellier 2, FR; 3LIRMM, FR |
| 10:00 | W10.3.3 | Enhanced TERO-PUF design and characterization with FPGA Cedric Marchand, Abdelkarim Cherkaoui and Bossuet Lilian, University of St. Etienne, FR |
| 10:15 | W10.3.4 | Implementing Reliable Mechanisms for IP Protection on Low-End FPGA devices Mario Barbareschi, Antonio Mazzea and Pierpaolo Bagnasco, University of Naples Federico II, IT |
| 10:30 | W10.4 | Poster Session 1 Chair: |
| 10:30 | W10.4.1 | Functional Locking Modules for Design Protection of Intellectual Property Cores Brice Colombier and Bossuet Lilian, University of St. Etienne, FR |
| 10:30 | W10.4.2 | 3D-NoC protection capabilities and threats: The TSV risk Martha Johanna Sepulveda1, Guy Gogniat2 and Marius Strum1 1University of São Paulo, BR; 2Universite de Bretagne-Sud / Lab-STICC, FR |
| 10:30 | W10.4.3 | Hardware Trojans in TRNGs Honorio Martin1, Pedro Paris-Lopez1, Enrique San Millan1, Juan E. Tapidor1 and Nicolas Sklavos2 1University Carlos III of Madrid, ES; 2KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR |
| 10:30 | W10.4.4 | Development of a Layout-Level Hardware Obfuscation Tool Shweta Malik1, Georg T. Becker2, Christof Paar2 and Wayne P. Burleson1 1University of Massachusetts, US; 2Horst Görtz Institute for IT-Security, Ruhr-University Bochum, DE |
| 10:30 | W10.4.5 | GET - Program for the Generation and Analysis on Nonlinear Elements Stjepan Picek1 and Lejla Batina2 1Faculty of Electrical Engineering and Computing, HR; 2Radboud University Nijmegen, NL |
| 10:30 | W10.4.6 | Why you should care about leading-edge Software Engineering? Tiziana Margaria, University of Limerick (Ireland) and Lero - The Irish Software Research Center, IE |
| 10:30 | W10.4.7 | Error detection and correction for lightweight cryptographic algorithms Francesco Regazzoni1, Andrey Bogdanov2, Luca Breveglieri3 and Israel Koren4 1Université catholique de Louvain and ALaRI, CH; 2Technical University of Denmark, DK; 3Polimi, IT; 4University of Massachusetts, US |
| 10:30 | W10.4.8 | Fine grain partial reconfiguration for fault emulation and precise LUT modification L.A. Cardona1, Bibiana Lorente2 and C. Ferrer3 1IEEC-UAB, ES; 2CNM-CSIC, ES; 3EEC-UAB, ES |
| 11:30 | W10.5 | Session 2 Chair: |
| 11:30 | W10.5.1 | Hierarchical Secure DfT Mafalda Cortez1, Said Hamdioui2, Giorgio Di Natale3, Marie-Lise Flottes3 and Bruno Rouzeyre3 1TU Delft, NL; 2Delft University of Technology, NL; 3LIRMM, FR |
| 12:00 | W10.5.2 | Integrated Sensors: A Backdoor for Hardware Trojan Activation Xuan-Thuy Ngo, Zakaria Najm, Shivam Bhasin, Sylvain Guilley and Jean-Luc Danger, Télécom ParisTech, FR |
| 13:00 | W10.6 | Keynote Talk 2 Chair: |
| 13:00 | W10.6.1 | Protecting Cryptographic Implementations on Reconfigurable Devices Tim Güneysu, Ruhr University Bochum, DE |
| 13:45 | W10.7 | Session 3 Chair: |
| 13:45 | W10.7.1 | Towards Generic Countermeasures Against Fault Injection Attacks Pablo Rauzy and Sylvian Guilley, Télécom ParisTech, FR |
| 14:00 | W10.7.2 | Analysis of laser-induced errors: RTL fault model versus layout locality characteristics Athanasios Papadimitriou1, David Hely2, Vincent Beroulle2, Paolo Maistri3 and Regis Leveugle3 1Univ. Grenoble Alpes, LCIS Laboratory, FR; 2Univ. Grenoble Alpes, FR; 3TIMA Laboratory, FR |
| 14:15 | W10.7.3 | Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technology Stephan De Castro and Giorgio Di Natale, LIRMM, FR |
| 14:30 | W10.7.4 | Dynamic Fault Model for Long Duration Laser-Induced Fault Simulation Feng Lu, Giorgio Di Natale, Marie-Lise Flottes and Bruno Rouzeyre, LIRMM, FR |
| 14:30 | W10.8 | Poster Session 2 Chair: |
| 14:30 | W10.8.1 | The Influence of Real-Time Scheduling on Differential Power Analysis Attacks Ke Jiang1, Lejla Batina2, Petru Eles1 and Zebo Peng1 1Linköping University, SE; 2Radboud University Nijmegen, NL |
| 14:30 | W10.8.2 | Exploring RNS in the design of improved RSA implementations Juvenal Araujo, Pedro Matutino, Leonel Sousa and Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT |
| 14:30 | W10.8.3 | CAESAR and NORX - Developing the Future of Authenticated Encryption Jean-Philippe Aumasson1, Philipp Jovanovic2 and Samuel Neves3 1Kudelski Security, CH; 2University of Passau, DE; 3University of Coimbra, GR |
| 14:30 | W10.8.4 | Power and Electromagnetic Analysis for Online Template Attacks Margaux Dugardin1, Louiza Papachristodoulou2, Zakaria Najm1, Lejla Batina3, Jean-Luc Danger1, Sylvain Guilley1, Jean-Christophe Courrege4, Anne-Sophie Rivemale4 and Carine Therond4 1Télécom ParisTech, FR; 2Radboud University Nijmegen,, NL; 3Radboud University Nijmegen, NL; 4Thales Communications & Security, FR |
| 14:30 | W10.8.5 | Search Strategy for Fault Injection using Memetic Algorithms Stjepan Picek1, Pieter Buzing2 and Lejla Batina3 1Faculty of Electrical Engineering and Computing, HR; 2Riscure BV, NL; 3Radboud University Nijmegen, NL |
| 14:30 | W10.8.6 | Insights into the Correlation between the Processed Data and its Power Traces Miryam Haber, Binyamin Frankel, Moshe Avital, Itamar Levi, Osnat Keren and Alexander Fish, Bar-Ilan University, IL |
| 14:30 | W10.8.7 | Tuning of randomized windows against simple power analysis for scalar multiplication on elliptic curves Simon Pontie1, Paolo Maistri2 and Regis Leveugle2 1University Grenoble Alpes, FR; 2TIMA Laboratory, FR |
| 15:00 | W10.9 | Session 4 Chair: |
| 15:00 | W10.9.1 | Public Key cryptographic primitive design and protection against fault and power analysis attacks Apostolos P. Fournaris and Nicolas Sklavos, KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR |
| 15:15 | W10.9.2 | On the Use of Error Detecting and Correcting Codes to Boost Security in Caches against Side Channel Attacks. Madalin Neagu1, Salvador Manich2 and Liniu Miclea1 1Technical University of Cluj-Napoca, RO; 2Universitat Politecnica de Catalunya, ES |
| 15:30 | W10.9.3 | A Side-Channel Attack Against Secret Permutation on an Embedded McEliece Cryptosystem Tania Richmond1, Martin Petrvalsky2 and Milos Drutarovsky2 1Univ. St. Etienne, FR; 2Technical University of Kosic, SK |
| 15:45 | W10.10 | Session 5 Chair: |
| 15:45 | W10.10.1 | Investigating TERO for Hardware Trojan Horse Detection Paris Kitsos1 and Artemios G. Voyiatzis2 1Technological Educational Institute of Western Greece, GR; 2ISI, GR |
| 16:00 | W10.10.2 | Insertion and evaluation of Hardware Trojans in Processors Ioannis Voyiatzis, Costas Efstathiou and Thanos Milidonis, Technological Educational Institute of Athens, GR |
| 16:15 | W10.10.3 | Security of ICs from Hardware Trojans Georgina Kalogeridou1, Andrew W. Moore1, Nicolas Sklavos2 and Odysseas Koufopavlou3 1Computer Laboratory, University of Cambridge, GB; 2KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR; 3University of Patras, GR |
| 16:30 | W10.10.4 | HINT: Holistic Approaches for Integrity of ICT-Systems Ingrid Verbauwhede and Dave Singelee, KU Leuven and UCLA, BE |
| 16:45 | W10.11 | Closing Session |
| 16:45 | W10.11.1 | Conclusions & Outlook: Round Table Giorgio Di Natale1, Ilia Polian2, Bossuet Lilian3 and Nicolas Sklavos4 1LIRMM, FR; 2University of Passau, DE; 3University of St. Etienne, FR; 4KNOSSOSnet Research Group / Technological Educational Institute of Western Greece, GR |
FD-SOI technology enables low cost and energy efficient designs best suited for today consumer, IoT and automotive applications, in continuity with traditional planar technologies simpler to design and manufacture with. The talks will illustrate the availability of a full FD-SOI technology ecosystem, encompassing IC fabrication, IP availability and design experiences.
The Academic Network was launched by Cadence in 2007. The aim was to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. A knowledge network among selected universities, research institutes, industry advisors and Cadence was established to facilitate the sharing of technology expertise in the areas of verification, design and implementation of microelectronic systems.
Specific examples of research directions in the cadence academic network will be given in three talks.
Session 6.8 is part of the exhibition program open to all exhibition visitors, but takes place as session 6.6 in the larger room Bayard (no presentations in room Les Diguières). Please refer to session 6.6 for the details.
Increasing demands of electrification arise from connected vehicles, medical devices, smart-grid and microgrid technologies, and the IoT evolution of devices into smart, interconnected systems. Those systems must meet market requirements for not only more sophisticated functionality, but also improved performance and robustness. As a result, companies need to transform how they design, analyze, implement, and verify their systems. At the same time, embedded-system platforms have become increasingly diverse combinations of digital/analog electronics and software, ranging from FPGA/ARM platforms (e.g,. Xilinx Zynq and Altera SoC) to a diverse range of heterogeneous manycore systems.
To help companies leverage these trends in their product and system development, EDA and embedded-system researchers are called upon to focus their research on new kinds of issues that arise. This panel will explore the key research needs and opportunities that come from the transformations that industries must embrace.
Today most innovations in the major industries include the use of dedicated chips. However, extremely high IC fabrication costs and foundries accepting only orders with high quantities are substantial obstacles for innovations developed from SMEs, start-ups, universities and research organisations.
The solution is that many of these innovators team up and share a fab run by using the opportunities offered by Multi Project Wavers (MPWs). European service providers like Europractice and CMP provide the access to MPW runs as well as the required know-how and tooling.
In the tutorial part of this session first-time users as well as experienced users will be provided with comprehensive information about the available semiconductor technologies, new design methodologies and possible applications. In the best practice part of the session users of such services will share their experience with the MPW concept with the audience and present projects and products realized by utilizing MPW opportunities.
IPs are today part of any Electronic Systems and it is more and more urgent to trace, monitor and more generally "manage" IPs in systems or products. The key feature of such a management is its multidisciplinary facet implying multiple management views and actors (IP Engineering, IP Sourcing, IP Procurement..).
Today an IP management platform needs to be a next generation web application hosted on an intranet server and receiving data from multiple sources (Design DB, IP Delivery DB, Product Shipment DB, Legal and Financial reports..). It aims at providing a reliable follow up to all of these departments such as IP Entry, IP Delivery, IP tracing in products… It delivers results (fee and royalty calculation for instance) as well as expertise for decision making (planning the future in terms of IP expenses, cost per product..).
The introductory talk will show how such a portal can be configured to fulfill the needs of an enterprise and what are the required "special" technical features missing in management tools presently available on the market.
Specific views namely Engineering view and Legal aspects will be commented by 2 speakers from companies veteran in IP management.
It will also be demonstrated that an amazing and straightforward extension concerns EDA Tool license management and optimization including integrated license monitoring. Such an extension aims at optimizing the tool cost for large enterprises using extensively and at a large scale a variety of development tools and gives an unique corporate global view on IP and Tools.
Will I ever travel in an autonomous vehicle? Will my refrigerator really order food automatically from my grocery store? Can the watch I wear in the future warn me about an impending heart attack? Innovations at the SoC and board level are poised to provide the necessary computational power with low cost and high flexibility to make these products. However, designing the systems of the future -- whether an automobile, connected industrial machinery, medical device, consumer electronics, or an aerospace guidance system -- requires advances not only in embedded systems and software, but how they are designed and verified.
In this keynote, an expert from industry will discuss trends and innovations in systems that are incorporating more electronic content than ever before, and describe model-based development approaches that companies are using to create the system functionality that will power our connected autonomous future.
MATLAB and Simulink provide a rich environment for embedded-system development, with libraries of proven, specialized algorithms ready to use for specific applications. The environment enables a model-based design workflow for fast prototyping and implementation of the algorithms on heterogeneous embedded targets, such as MPSoC. A system-level design approach enables architectural exploration and partitioning, as well as coordination between SW and HW development workflows. Functional verification throughout the design process improves coverage and test-case generation while reducing the time and resources required.
In this set of tutorial sessions, you will learn