Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design, statistical timing analysis, timing closure; hierarchical and non-hierarchical controller synthesis; state assignment; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; PLD and FPGA synthesis; arithmetic circuits.
Chair: José Monteiro, INESC-ID / IST, TU Lisbon, PT, Contact
Co-Chair: Valentina Ciriani, University of Milano, IT, Contact
Members: