Agenda
| 8:30 - 8:45 | Opening session Chairs: Görschwin Fey, Emmanuelle Encrenaz-Tiphéne |
| 8:45 - 9:30 | Invited talk Managing Design Knowledge for IP Cores – State-of-the-art and Open Questions Alexander Rath Infineon Technologies AG, Munich, Germany |
| 9:30 - 10:30 | Technical session: Formal and semi-formal Automatic identification of logical relationships among internal signals with small numbers of test vectors Masahiro Fujita, Takeshi Matsumoto and Satoshi Jo University of Tokyo, Japan Using Natural Language Documentation in the Formal Verification of Hardware Designs Christopher Harris and Ian Harris University of California, Irvine, USA Understanding Compound Systems from their Components' Properties Syed-Hussein Syed-Alwi and Emmanuelle Encrenaz Université Pierre et Marie Curie Paris 6, France Design Understanding with Fast Prototyping from Assertions Katell Morin-Allory, Fatemeh Javaheri and Dominique Borrione Univ. Grenoble Alpes, Grenoble, France |
| 10:30 - 11:00 | Coffee break & poster presentations Posters: Detecting Concurrency Problems in System Level Designs Alper Sen and Onder Kalaci Bogazici University, Istanbul, Turkey Automatically connecting hardware blocks via light-weight matching techniques Jan Malburg1, Niklas Krafczyk1 and Goerschwin Fey1,2 1University of Bremen, Germany 2German Aerospace Center, Bremen, Germany Exact Solution for Trace Signal Selection with Pseudo Boolean Optimization (PBO) Shridhar Choudhary, Kousuke Oshima, Amir Masoud Gharehbaghi, Takeshi Matsumoto and Masahiro Fujita The University of Tokyo, Tokyo, JAPAN |
| 11:00 - 12:00 | Invited talk Capturing and Validating Design Understanding using Formal Properties Raik Brinkmann OneSpinSolutions GmbH, Munich, Germany |
| 12:00 - 13:00 | Lunch |
| 13:00 - 13:45 | Invited talk Design Understanding in SOC Development - Recent Advances and New Challenges Lyes Benalycherif ST Microelectronics, Grenoble, France |
| 13:45 - 14:15 | Technical session: System level productivity DiplodocusDF: Analyzing Hardware/Software Interactions with a Dinosaur Andrea Enrici, Ludovic Apvrille and Renaud Pacalet Telecom ParisTech, Biot, France Towards a Multi-dimensional and Dynamic Visualization for ESL Designs Jannis Stoppe1, Marc Michael2, Mathias Soeken1,2, Robert Wille1,2,3 and Rolf Drechsler1,2 1DFKI GmbH, Bremen, Germany 2University of Bremen, Bremen, Germany 3Technical University Dresden, Germany |
| 14:15 - 15:00 | Invited talk Software Reverse Engineering Rainer Koschke [1] University of Bremen, Germany |
| 15:00 - 15:30 | Coffee break & poster presentations |
| 15:30 - 16:15 | Technical session: Reverse and automatic engineering Increasing Verilog’s Generative Power Cherif Salama1 and Walid Taha2 1Ain Shams University, Cairo, Egypt 2Halmstad University, Halmstad, Sweden zamiaCAD: Understand, Develop and Debug Hardware Designs Maksim Jenihhin1, Valentin Tihhomirov1, Syed Saif Abrar1, Jaan Raik1 and Guenter Bartsch2 1Tallinn University of Technology, Estonia 2zamiaCAD, Germany Mutation based Feature Localization Jan Malburg1, Emmanuelle Encrenaz-Tiphene2 and Goerschwin Fey1,3 1University of Bremen, Germany 2Université Pierre et Marie Curie Paris 6, France 3German Aerospace Center, Bremen, Germany |
| 16:15 - 17:00 | Panel Design understanding – where do industry and acdemia team up? Panelists: Ian Harris, Lyes Benalycherif, Raik Brinkmann The panel will summarize the results of the day and prioritize topics focusing on three questions:
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