Scheduled Poster Presentations
- Agathoklis Papadopoulos (University of Cyprus, CY): Accelerating Bioinformatics and Biomedical Applications via Massively Parallel Reconfigurable Systems
- Angeliki Kritikakou (ONERA, Toulouse, F): Scalable & Near-optimal methodologies for memory management & processing of embedded systems
- Antonio Salazar (University of Porto, PT): Mixed-signal Test and Measurement Framework for Wearable Monitoring System
- Anup Das (National University of Singapore, SG): Design Methodology for Reliable and Energy Efficient Multiprocessor Systems
- Arnaldo Cruz (Kyushu University, JP): Compiler optimization space exploration using machine learning techniques
- Benoit Vernay (University Pierre et Marie Curie, Paris, F): A Novel Method of MEMS System-Level Modeling via Multi-Domain Virtual Prototyping in SystemC-AMS
- Daniele Bortolotti (University of Bologna, I): A Process and Environmental Variation Tolerance Scheme for ULP Shared-memory Processor Cluster
- Danila Gorodecky (Academy of Sciences, Minsk, Belarus): Mathematical Models and Synthesis Methods of Computing Devices in Modular Arithmetic
- Domitian Tamas-Selicean (Technical University of Denmark, DK): Design of Mixed-Criticality Applications on Distributed Real-Time Systems
- Emad Ebeid (University of Verona, I): Modeling and Synthesis of the Network in Distributed Embedded Systems
- Fabian Oboril (Karlsruhe Institute of Technology, D): Cross-Layer Approaches for Aging-Aware Design of Nanoscale Microprocessors
- Fatemeh Negin Javaheri (TIMA Lab, F): Designing from Assertions: from PSL Properties to a Compliant Hardware Prototype
- Fazal Hameed (Karlsruhe Institute of Technology, D): DRAM Aware Last Level Cache Policies for Multi-Core Systems
- Jai Narayan Tripathi (Indian Institute of Technology Mumbai, IN): Power Integrity Analysis and Discrete Optimization of Decoupling Capacitors
- Karthik Chandrasekar (Delft University of Technology, NL): High-Level Power Estimation of DRAMs
- Lars Middendorf (University of Rostock, D): Dynamic Task Mapping on Multi-Core Architectures using Stream Rewriting
- Leonidas Kosmidis (Barcelona Supercomputing Center, ES): Enabling Caches in Probabilistic Timing Analysis
- Luca Cassano (University of Pisa, I): Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs
- Marco Indaco (Politecnico di Torino, I): Service Oriented Non Volatile Memories
- Matheus Moreira (Pontifical Catholic University of Rio Grande do Sul, BR): Quasi-Delay-Insensitive Return-to-One Design
- Mathias Soeken (University of Bremen, D): Formal Specification Level
- Milan Pavlovic (Barcelona Supercomputing Center, ES): Data Placement in HPC Architectures with Heterogeneous Off-chip Memory
- Mirela Alistar (Technical University of Denmark, DK): Compilation and Synthesis for Fault-Tolerant Digital Microfluidic Biochips
- Miroslav Valka (University of Montpellier II, F): Power Aware Test and Test of Low Power Devices
- Mohamed Bamakhrama (Leiden University, NL): On Hard Real-Time Scheduling of Cyclo-Static Dataflow and its Application in System-Level Design
- Namita Sharma (Indian Institute of Technology Delhi, IN): Data Memory Optimizations for SPM based Baseband Processor Architectures
- Nikola Rajovic (Barcelona Supercomputing Center, ES): High Performance Computing with Mobile SoCs: Opportunities and Challenges
- Norma Montealegre (Heinz Nixdorf Institut, Paderborn, D): Immunorepairing of Hardware Systems
- Ogun Turkyilmaz (CEA-LETI, Grenoble, F): Using 3D technologies to reduce power consumption of FPGAs
- Oliver Arnold (TU Dresden, D): Dynamic Task Scheduling for heterogeneous MPSoCs
- Pydi Bahubalindruni (University of Porto, PT): Analog/Mixed – Signal Circuits using a-GIZO TFTs
- Robert Reicherdt (Technische Universität Berlin, D): Formal Veri?cation of Discrete-Time MATLAB/Simulink Models using Boogie
- Saman Kiamehr (Karlsruhe Institute of Technology, D): Cross layer resiliency modeling and optimization: A device to circuit approach
- Samaneh Ghandali (University of Tehran, IR): High-level Synthesis and Optimization of Datapath-intensive Embedded System Designs
- Sudip Roy (Indian Institute of Technology Kharagpur, IN): Algorithms for Design Automation of Sample Preparation on Digital Microfluidic Biochips
- Turbo Majumder (Indian Institute of Technology Delhi, IN): On-Chip Network-Enabled Many-Core Architectures for Computational Biology Applications
- Vito Giovanni Castellana (Politecnico di Milano, I): C-Based High Level Synthesis of Adaptive Hardware Components